KR20110002245A

KR20110002245A - A non volatile memory device and method of programming thereof

Info

Publication number: KR20110002245A
Application number: KR1020090059741A
Authority: KR
Inventors: 김기환
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-07-01
Filing date: 2009-07-01
Publication date: 2011-01-07

Abstract

PURPOSE: A non volatile memory device and a method of programming thereof are provided to improve the retention characteristics of a device by suppressing the deterioration of a tunnel insulating film. CONSTITUTION: First and second normal memory cell strings are respectively connected to an even bit line(BLe) and an odd bit line. The first and second dummy strings(120, 130) are respectively connected to the even bit line and the odd bit line. The first and the second dummy string are connected in parallel with the first and second normal memory cells. The first and second dummy string are arranged between the first and second normal memory cell string.

Description

A nonvolatile memory device and method of programming thereof

The present invention relates to a nonvolatile memory device and a program method thereof, and to a nonvolatile memory device and a program method thereof capable of improving retention characteristics of the nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals. In order to develop a large-capacity memory device capable of storing a large amount of data, researches on a high integration technology of the memory device have been actively conducted. Here, the term 'program' refers to an operation of writing data to a memory cell, and 'erase' refers to an operation of removing data written to the memory cell.

As a result, a plurality of memory cells are connected in series, i.e., structures in which drains or sources are shared between adjacent cells for high integration of memory devices. A NAND-type flash memory device has been proposed. Unlike NOR-type flash memory devices, NAND flash memory devices are memory devices that read information sequentially and use a Fowler-Nordheim (FN) tunneling scheme. The program and erase operations are performed by controlling the threshold voltage of the memory cell while injecting or emitting electrons into the floating gate.

However, in the flash memory device according to the related art, as the program and erase operations are repeated, the FN tunneling operation in which electrons pass through the tunnel insulation layer is repeatedly performed, thereby causing degradation of the tunnel insulation layer. As a result, trap sites are generated in the tunnel insulating film, so that the overprogram and retention characteristics of the device are degraded.

SUMMARY OF THE INVENTION The present invention provides a dummy string in which dummy memory cells are connected in series next to a string of normal memory cells connected in series to a bit line, so that the normal memory cell is affected by an interference effect caused by the dummy memory cell during a program operation. The present invention provides a nonvolatile memory device and a program method thereof, by which the threshold voltage of a normal memory cell increases by a target threshold voltage, thereby suppressing deterioration characteristics of the tunnel insulating layer and improving retention characteristics of the device.

A nonvolatile memory device according to an embodiment of the present invention is connected to first and second normal memory cell strings respectively connected to an even bit line and an odd bit line, respectively, and is connected to the even bit line and the odd bit line. And first and second dummy strings connected in parallel with a second normal memory cell string, wherein the first and second dummy strings are disposed between the first and second normal memory cell strings.

The first and second dummy strings include dummy cells corresponding to memory cells included in the first and second normal memory cell strings.

The coupling ratio of the dummy cells is higher than the coupling ratio of the memory cells.

The first and second dummy strings further include a precharge control transistor for controlling a potential precharged from the even bit line and the odd bit line.

According to an embodiment of the present disclosure, a program method of a nonvolatile memory device includes a normal memory cell string connected between a bit line and a source line, and a dummy connected in parallel with the normal memory cell string between the bit line and the source line. A program method of a nonvolatile memory device including a string, wherein the program voltage is applied to a selected memory cell of the normal memory cell string at a word line and the program voltage is applied to a dummy cell of the dummy string corresponding to the selected memory cell. A program verifying the selected memory cell by applying a verify voltage to the word line, and increasing the program voltage when the threshold voltage of the selected memory cell is lower than the verify voltage. Include steps to redo the steps In addition, in the programming step, the threshold voltage of the selected memory cell is increased by the program voltage, and the threshold voltage is increased by the interference effect of the dummy cell.

After precharging the bit line to a high level prior to the programming step, controlling the bit line potential applied to the dummy string to control the threshold voltage value rising by the interlace effect.

According to an embodiment of the present invention, by placing a dummy string in which dummy memory cells are connected in series next to a string of normal memory cells connected in series to a bit line, the normal memory cell may have an interference effect caused by the dummy memory cell during a program operation. By increasing the threshold voltage of the normal memory cell by the target threshold voltage, the degradation characteristic of the tunnel insulating film can be suppressed to improve the retention characteristics of the device.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. Only this embodiment is provided to complete the disclosure of the present invention and to fully inform those skilled in the art, the scope of the present invention should be understood by the claims of the present application.

1 is a circuit diagram illustrating a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device may include a first normal string 110, a first dummy string 120, and an odd bit line BLo connected to an even bit line BLe. And a second normal string 140 and a second dummy string 130 connected to each other. The even bit line BLe and the odd bit line BLO are connected to one page buffer PB.

In more detail, the first normal string 110 and the first dummy string 120 are connected in parallel between the even bit line BLe and the common source line CSL, and the second normal string 140 and The second dummy string 130 is connected in parallel between the odd bit line BLo and the common source line CSL. In addition, the first dummy string 120 and the second dummy string 130 are disposed between the first normal string 110 and the second normal string 140.

Each of the first normal string 110 and the second normal string 140 may include a drain select transistor DST and a plurality of memory cells between the even bit line BLe or the odd bit line BLO and the common source line CSL. MC0 to MC31, and the source select transistor SST are connected in series. Each of the first dummy string 120 and the second dummy string 130 may select a precharge control transistor PRET and a dummy drain between the even bit line BLe or the odd bit line BLO and the common source line CSL. The transistor DDST, the plurality of dummy memory cells DMC0 to DMC31, and the dummy source select transistor DSST are connected in series.

FIG. 2 is a cross-sectional view of a device for describing the structures of a normal cell and a dummy cell shown in FIG. 1.

2, a normal cell and a dummy cell are formed adjacent to each other on a semiconductor substrate 200, and dummy cells of other bit lines are formed in other adjacent regions of the dummy cell. In general, a normal cell and a dummy cell are formed by stacking a tunnel insulating film 201, a floating gate 202, a dielectric film 204, and a control gate 205 on a semiconductor substrate 200. At this time, it is desirable to reduce the distance between the normal cell and the dummy cell than the prior art to increase the interference effect. In addition, when the height of the device isolation film 203A between the adjacent dummy cells is lower than that of the normal cell and the device isolation film 203B, the area of the dielectric film 204 in contact with the floating gate is greater than that of the normal cell. Is formed more widely in. Therefore, the coupling ratio of the dummy cell is formed to be higher than that of the normal cell.

3 is a waveform diagram of signals and a threshold voltage rising graph for explaining a method of programming a nonvolatile memory device according to an exemplary embodiment of the present invention.

A method of programming a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 3 as follows.

The program method of the present invention repeatedly executes the program operation and the verify operation, and uses an incremental step pulse programming (ISPP) method that uses a new program voltage increased by the step potential during the program operation.

First, the even bit line BLe is precharged to a high level during a program operation of the first normal string 110 connected to the even bit line BLe. Thereafter, during the program operation, the dummy bit line precharge signal DBLe_PRE is controlled according to the interference value applied from the dummy cell to adjust the amount of potential applied to the first dummy string 120. For example, the potential of the dummy bit line precharge signal DBLe_PRE is decreased to increase the interference value, and the potential of the dummy bit line precharge signal DBLe_PRE is increased to reduce the interference value.

Thereafter, a program voltage is applied to a word line connected to a selected memory cell (for example, MC29) among the plurality of memory cells MC0 to MC31. At this time, the dummy memory cell DMC29 connected to the same word line as the selected memory cell MC29 is also programmed at the same time.

In the above-described program operation, since the coupling ratio of the dummy memory cell DMC29 is greater than the coupling ratio of the memory cell MC29, the programming ratio is programmed to have a higher threshold voltage. In addition, the threshold voltage of the memory cell MC29 is transferred to the floating gate 202 by tunneling the tunnel insulating film 201 according to the program voltage applied to the word line, so that the threshold voltage increases and is adjacent to the threshold voltage of the memory cell MC29. The threshold voltage increases due to the interference effect caused by the program operation of the dummy memory cell DMC29.

Thereafter, a verify operation is performed to determine whether the threshold voltage of the memory cell MC29 is higher than the verify voltage. If the threshold voltage of the memory cell MC29 is lower than the verify voltage, the program voltage applied to the word line is increased by the step potential to repeat the above-described program operation and the verify operation. If the threshold voltage of the memory cell MC29 is higher than the verify voltage, the program operation is terminated.

As described above, when the memory cell MC29 and the dummy memory cell DMC29 are programmed simultaneously, when the threshold voltage is programmed above the verify voltage, all electrons are transferred to the floating gate by FN tunneling as in the prior art, so that the threshold voltage is increased. Since the threshold voltage is increased by the FN tunneling method and the interference effect, the trap site of the tunnel insulating film 201 is reduced, and the deterioration phenomenon is reduced. In addition, during the program operation, the interference value may be adjusted by controlling the bit line potential applied to the first dummy string 120.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

Claims

A normal memory cell string coupled between the bit line and the source line; And

A dummy string connected in parallel with the normal memory cell string between the bit line and the source line,

And the dummy string includes dummy memory cells corresponding to memory cells of the normal memory cell string.

The method of claim 1,

And the dummy memory cells are programmed simultaneously when the memory cells of the normal memory cell string are programmed.

First and second normal memory cell strings connected to the even bit line and the odd bit line, respectively;

And first and second dummy strings connected to the even bit line and the odd bit line, respectively, and connected in parallel with the first and second normal memory cell strings.

And the first and second dummy strings are disposed between the first and second normal memory cell strings.

The method of claim 3, wherein

And the first and second dummy strings include dummy cells corresponding to memory cells included in the first and second normal memory cell strings.

The method of claim 4, wherein

And a coupling ratio of the dummy cells is higher than a coupling ratio of the memory cells.

The method of claim 3, wherein

A method of programming a nonvolatile memory device comprising a normal memory cell string connected between a bit line and a source line, and a dummy string connected in parallel with the normal memory cell string between the bit line and the source line.

A program step of applying a program voltage to a word line to a selected memory cell of the normal memory cell string and applying the program voltage to a dummy cell of the dummy string corresponding to the selected memory cell;

Verifying the selected memory cell by applying a verify voltage to the word line;

If the threshold voltage of the selected memory cell is lower than the verification voltage, increasing the program voltage to perform the program step again;

In the programming step, the selected memory cell increases the threshold voltage due to the program voltage and simultaneously increases the threshold voltage due to the interference resistance caused by the dummy cell.

The method of claim 7, wherein

After precharging the bit line to a high level prior to the programming step, controlling the bit line potential applied to the dummy string to control a threshold voltage value rising by the interlace effect. Program method of volatile memory device.