KR20110001893A - Electronic device including a well region - Google Patents

Abstract

PURPOSE: An electronic device including the well region is provided to realize the miniaturizing of the electronic device and to improve the performance of the electronic device by reducing the parasitic resistance and the inductance. CONSTITUTION: A semiconductor layer(104) is formed on a flasking conducting region(102). A vertical conductive structure is electrically connected to the flasking conducting region. A first doping structure(106) is electrically connected to the flasking conducting region. A well region comprises a first part of the semiconductor layer.

Description

ELECTRONIC DEVICE INCLUDING A WELL REGION}

The present invention relates to an electronic device and a process for forming the electronic device, and more particularly, to an electronic device comprising an isolated well region and a process for forming the electronic device.

Metal oxide field effect transistors (MOSFETs) are a common type of power switching device. The MOSFET includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure provided adjacent to the channel region. The gate structure includes a gate electrode layer adjacent to the channel region and positioned separately from the channel region by a thin dielectric layer.

When the MOSFET is in the on state, a voltage is applied to the gate structure to form a conduction channel region between the source and drain regions, which can cause current to flow in the device. In the off state, any voltage applied to the gate structure is sufficiently low that no conduction channel is formed and therefore no current flow occurs. While in the off-state, the device must support high voltages between the source and drain regions.

In certain uses, a pair of power transistors may be used to generate an output that switches between two different voltages. The output may be connected to a source of a high-side power transistor and to a drain of a low-side power transistor. When the high side power transistor is activated, the output will be at a voltage corresponding to the voltage of the drain of the high side power transistor, and when the low side power transistor is activated, the output will be at a voltage corresponding to the source of the low side power transistor. will be. In certain embodiments, high side power transistors and low side power transistors are discrete element transistors on separate dies that are typically interconnected by bonded wires or other similar interconnects. Moreover, the control circuitry for the two power transistors is also on separate dies. The interconnect increases unwanted parasitic characteristics for electronic devices including high side and low side power transistors.

Embodiments are shown by way of example and not by way of limitation in the figures thereof.
1 shows a cross-sectional view of a work piece comprising a buried conductive region, a semiconductor layer and a buried doped region.
FIG. 2 shows a cross sectional view of the working member of FIG. 1 after forming another semiconductor layer and other buried doped regions. FIG.
3 shows a cross sectional view of the working member of FIG. 2 after forming another semiconductor layer to complete the formation of the composite semiconductor layer.
4 shows a cross-sectional view of the working member of FIG. 3 after forming an implant screen layer and a vertical doped portion in the semiconductor layer.
FIG. 5 shows a cross sectional view of the working member of FIG. 4 after forming a pad layer, a stopping layer, another masking layer, and a vertical doped region in the semiconductor layer. .
FIG. 6 shows a cross-sectional view of the working member of FIG. 5 after forming a sacrificial sidewall spacer, a trench extending through the semiconductor layer, and an insulating sidewall spacer.
FIG. 7 shows a cross sectional view of the working member of FIG. 6 after forming a conductive structure. FIG.
8 shows a cross-sectional view of the working member of FIG. 7 after forming a conductive plug. FIG.
9 shows a cross sectional view of the working member of FIG. 8 after forming an insulating layer and a patterned conductive layer.
10 shows a cross-sectional view of the working member of FIG. 9 after forming the high side power transistor and the low side power transistor.
11-15 illustrate cross-sectional views of the working member of FIG. 9 after forming exemplary electronic components in one or more sections as described with respect to FIGS. 1-9.
16 illustrates a cross-sectional view of the working member of FIG. 1 after forming a semiconductor layer and a doped region within the semiconductor layer in accordance with an alternative embodiment.
17 illustrates a cross-sectional view of the working member of FIG. 4 after forming the trench, the conductive structure, and the conductive plug in accordance with an alternative embodiment.
FIG. 18 illustrates a cross-sectional view of the working member of FIG. 4 after forming a trench, a doped semiconductor spacer, an insulating sidewall spacer, and a conductive structure in accordance with an alternative embodiment.
19 illustrates a cross-sectional view of the working member of FIG. 4 after forming trench and insulated sidewall spacers in accordance with an alternative embodiment.
20 illustrates a cross-sectional view of the working member of FIG. 18 after stretching the trench and forming the conductive structure and the conductive plug in accordance with an alternative embodiment.
Those skilled in the art will understand that elements of the drawings are shown for brevity and clarity and are not necessarily to scale. For example, some of the elements have been exaggerated compared to other elements to improve the understanding of embodiments of the present invention.

The following description, in combination with the drawings, is provided to aid in understanding the disclosure disclosed herein. The following description will focus on specific embodiments and examples of the present disclosure. This is intended to help explain the present disclosure and should not be construed as limiting the scope or applicability of the disclosure. Other content may of course also be used for the application.

As used herein, the terms "horizontally oriented" and "vertically oriented" associated with an area or structure refer to the main direction of the current flowing through that area or structure. More specifically, the current can flow through the region or structure in a vertical direction, horizontal direction, or a combination of vertical and horizontal directions. If current flows through the region or structure in a vertical direction or a combination of directions, where the vertical element is larger than the horizontal element, it will be said that this region or structure is vertically oriented. Similarly, when current flows through a region or structure in a horizontal direction or a combination of directions, where the horizontal element is larger than the vertical element, it will be said that this region or structure is vertically oriented.

The terms "normal operation" and "normal operation state" refer to states in which electronic components or devices are designed to operate. This state can be obtained from data sheets or other information regarding voltage, current, capacitance, resistance, or other electrical parameters. Thus, normal operation does not include the operation of electrical components or devices that far exceed design limitations.

Terms such as "comprising", "comprising", "comprising" and the like are intended to cover non-exclusive inclusions. For example, a method, product, or device that includes a feature list is not necessarily limited to that feature, and may include other features that are not listed, or features that are specific to the method, product, or device. In addition, "or" means "inclusive-or", not "exclusive-or". For example, condition A or B means any one of the following cases. That is, A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B It means any one of the truth (or existence).

In addition, in describing the elements and components described herein, singular surfaces were used. This is for convenience only and to provide a general awareness of the scope of the invention. Thus, unless stated to the contrary, the specification is to be understood to include one or more than one, and to include a plural number as well as vice versa. For example, where a single item is described, more than one item may be used in place of a single item. Similarly, if more than one item is described, a single item may replace more than one item.

The family number corresponding to the column in the periodic table of elements is CRC Handbook of Chemistry and New Physics , 81 ^st Edition (2000-2001), use the "New Notation" convention.

Unless defined otherwise, technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing behaviors are conventional and may be found in textbooks and other materials within semiconductor and electronic courses.

In Figures 1-9, six different sections of the work piece are shown to increase understanding of the effect of process operation when forming different types of electronic components on the same work piece. Electronic components may be part of the same integrated circuit. Shown at the top of the figure corresponds to a high side power transistor, electronic components are potentially connected to or otherwise associated with the high side power transistor, shown at the bottom of the same figure corresponds to a low side power transistor, Electronic components are potentially connected to or otherwise associated with the low side power transistor.

1 shows a cross-sectional view of a portion of a work member 100. Several other sections of the integrated circuit are shown in FIG. 1. More specifically, section 122 includes a portion of an integrated circuit in which a p-well region is to be formed that is electrically connected to buried conductive region 102 and section 124 is formed. Includes another portion of the integrated circuit in which the n-well region is to be formed, and section 126 includes another portion of the integrated circuit in which the high side power transistor is to be formed. Section 132 includes a portion of an integrated circuit where a p-well region is to be formed, section 134 includes another portion of an integrated circuit where another n-well region is to be formed, and section 136 is a row. And another part of the integrated circuit in which the side power transistor is to be formed.

In certain embodiments, electronic components that support the high side transistors of section 126, or are used in conjunction with the high side transistors, may be formed in sections 122 and 124, support low side transistors, or low side transistors. Electronic components used in conjunction with may be formed in sections 132 and 134.

In FIG. 1, the working member 100 includes a buried conductive region 102. Buried conducting region 102 may comprise a Group 14 element (eg, carbon, silicon, germanium, or any combination thereof) and may be heavily doped in n-type or p-type. For purposes of this specification, high doping has a maximum dopant concentration of 10 ¹⁹ atoms / cm ^3. Low doping means that the highest dopant concentration is less than 10 ¹⁹ atoms / cm ³ . The buried conductive region 102 may be part of a heavily doped substrate (eg, an n-type heavily doped wafer) or may be placed on a substrate of opposite conductivity type, or between the substrate and the buried conductive region 102. It may be a buried doped region overlying a buried insulating layer (not shown). In one embodiment, the buried conducting region 102 is heavily doped with n-type dopants such as phosphorus, arsenic, antimony, or any combination thereof. In certain embodiments, the buried conductive region 102 may comprise arsenic or antimony when the diffusion of the buried conductive region 102 is maintained at a low concentration, and in certain embodiments, the buried conductive region 102 is followed by Antimony may be included (as compared to arsenic) to lower the level of automatic doping while forming the semiconductor layer to be formed. The buried conducting region 102 will be used to electrically connect the source of the high side power transistor and the drain of the low side power transistor to each other and become part of the output node for the electronic device. Accordingly, the buried conducting region 102 can vary according to the control signal for the control electrodes of the high side and low side power transistors, so that the voltage of the buried conducting region 102 is not substantially constant, and the time or It may vary depending on other parameters.

The semiconductor layer 104 is formed over the buried conductive region 102. The semiconductor layer 104 may be a Group 14 element (eg, carbon, silicon, germanium, or any combination thereof), any dopant as described with respect to the buried conducting region 102, or a dopant of opposite conductivity type. It may include. In an embodiment, the semiconductor layer 104 is a lightly doped n-type or p-type epitaxial silicon layer, the silicon layer having a thickness of about 0.2 microns to about 1.0 microns and about 10 ¹⁷ atoms / cm ³ or less (In another embodiment, a doping concentration of approximately 10 ¹⁴ atoms / cm ³ or more). The semiconductor layer 104 is formed on all the work members 100.

Portions of the semiconductor layer 104 in the high side power transistor and in the sections 122, 124, and 134 are heavily doped with dopants of a conductivity type opposite to the buried conducting region 102, thereby buried doped regions. Form 106. The buried doped region 106 may help isolation within the high side power transistor and reduce many of the parasitic features within the high side power transistor, and electronic components within other portions of the integrated circuit. In a particular embodiment, the buried doped region 106 has a p-type dopant having a highest dopant concentration of approximately 10 ¹⁹ atoms / cm ³ or greater. The buried doped region 106 in the sections 122, 124, 126 and 134 may be a horizontal portion of the doped structure to be formed.

Referring to FIG. 2, a semiconductor layer 204 is formed over the semiconductor layer 104 (not shown) and the buried conductive region 106. In certain embodiments, semiconductor layers 104 and 204 have the same conductivity type and may both be lightly doped. Thus, the dotted line in the illustration of FIG. 2 shows the approximate location where the semiconductor layer 104 ends and the semiconductor layer 204 begins. The semiconductor layer 204 may be a Group 14 element (eg, carbon, silicon, germanium, or any combination thereof), any of the dopants as described with respect to the buried conducting region 102, or the opposite conductivity type. It may include a dopant of. In an embodiment, the semiconductor layer 204 is a lightly doped n-type or p-type epitaxial silicon layer, the silicon layer having a thickness of about 0.5 microns to about 5.0 microns and about 10 ¹⁷ atoms / cm ³ or less (In another embodiment, a doping concentration of approximately 10 ¹⁴ atoms / cm ³ or more).

Portions of semiconductor layer 204 in sections 124 and 134 are heavily doped with n-type dopants to form other buried doped regions 206. The buried doped region 206 is optional and may help further isolate the n-well region to be formed. In a particular embodiment, the buried doped region 206 has an n-type dopant having a highest dopant concentration of approximately 10 ¹⁹ atoms / cm ³ or greater. A portion of semiconductor layer 204 in section 132 is heavily doped with p-type dopant to form another buried doped region 208. In a particular embodiment, the buried doped region 208 is approximately 10 ¹⁹ atoms / cm ³ It has a p-type dopant having the highest dopant concentration of above. Buried doped regions 206 and 208 in sections 124, 132, and 134 are horizontal portions of the doped structure to be formed.

Referring to FIG. 3, a semiconductor layer 302 is formed over the semiconductor layer 204 and the buried doped regions 206 and 208. The combination of semiconductor layer 104 (not shown in FIG. 3), 204, and 302 forms a composite semiconductor layer 304. In certain embodiments, semiconductor layers 104, 204, and 302 have the same conductivity type and may be lightly doped. Thus, the dotted line in FIG. 3 shows the approximate location where the semiconductor layer 204 ends and the semiconductor layer 302 begins. The semiconductor layer 302 may be a Group 14 element (eg, carbon, silicon, germanium, or any combination thereof), any of the dopants, such as those described with respect to the buried conductive region 102, or the opposite conductivity type. It may include a dopant of. In an embodiment, the semiconductor layer 302 is a lightly doped n-type or p-type epitaxial silicon layer, the silicon layer having a thickness ranging from approximately 0.5 microns to approximately 5.0 microns and approximately 10 ¹⁷ atoms / cm ^3. And a doping concentration of about 10 ¹⁴ atoms / cm ³ or more in another embodiment.

The composite semiconductor layer 304 has a major surface 305. The dopant concentration in the composite semiconductor layer 304 outside the buried doped regions 106, 206, and 208, and the dopant concentration prior to any optional selective doping with respect to the region in the composite semiconductor layer 304 are the background dopant concentration. May be referred to as. In subsequent embodiments the combination of semiconductor layers 104, 204, and 302 will be referred to as semiconductor layer 304, and no dashed lines between the individual layers making up composite semiconductor layer 304 will be included. In one embodiment, the buried doped regions 206 and 208 are raised at an intermediate point between the major surface of the semiconductor layer 304 and one or more of the buried conductive regions 102, or the buried doped region 106. ) In another embodiment, the buried doped region 106 is spaced apart from the major surface 305 and lies closer to the surface of the semiconductor layer 304 opposite the major surface 305 than the major surface 305.

As shown in FIG. 4, an implant screen layer 402 may be formed over the major surface 305. The injection barrier layer 402 may comprise an oxide, nitride, or oxynitride and may have a thickness in the range of approximately 2 nm to 50 nm. The injection barrier layer 402 may be formed by thermal growth or deposition techniques.

A masking layer (not shown) is formed over the injection barrier layer 402 and is patterned to form only openings in which the vertical portion 406 of the doped structure 416 will be formed. A portion of semiconductor layer 304 in sections 124 and 134 is heavily doped with n-type dopant to form vertical portion 406 of doped structure 416. In a particular embodiment, vertical portion 406 has an n-type dopant having a highest dopant concentration of approximately 10 ¹⁹ atoms / cm ³ or greater. The mask layer is removed, and another mask layer (not shown) is formed over the injection barrier layer 402 and patterned to form only the opening in which the vertical portion 408 of the doped structure 418 is to be formed. A portion of semiconductor layer 304 in section 132 is heavily doped with p-type dopant to form vertical portion 408 of doped structure 418. In a particular embodiment, vertical portion 408 has a p-type dopant having a highest dopant concentration of approximately 10 ¹⁹ atoms / cm ³ or greater. After that, the remaining mask layer is removed.

The doping structure 416 includes a vertical portion 406 and a horizontal portion (eg, investment doped region 206), and the doping structure 418 includes a vertical portion 408 and a horizontal portion (eg, investment doped region 208). )). Doped structures 416 and 418 are tubular (as shown in the three-dimensional depiction (not shown)) and U-shaped in the cross-sectional view shown in FIG. Doped structures 416 and 418 form inner portions 426 and 428 of semiconductor layer 304, respectively. Inner portions 426 and 428 have lower dopant concentrations as compared to doping structures 416 and 418. The inner portions 426 and 428 may have the same or different conductivity types, dopants and concentrations with respect to each other and when compared to the doped structures 416 and 418 and the semiconductor layer 304 in a region spaced from the buried region 106. Can have The well region may comprise a combination of the doping structure 416 and the inner portion 426, and a combination of the doping structure 418 and the inner portion 428. Electronic components designed to operate at lower voltages than the low side and high side power transistors can be formed within the well region and can operate normally without significant interference or other adverse effects from the low side and high side power transistors. In the figures that follow, the doping structures 406 and 418 will be shown without their separate horizontal and vertical portions.

In FIG. 5, the pad layer 502 and the stop layer 504 (eg, a polish-stop layer or an etch-stop layer) are thermal growth techniques, deposition techniques, or their It is formed successively on the semiconductor layer 304 using a combination of. Each of the pad layer 502 and the stop layer 504 may include an oxide, nitride, oxynitride, or a combination thereof. In an embodiment, the pad layer 306 has a different composition than the stop layer 308. In a particular embodiment, the pad layer 306 comprises an oxide and the stop layer 308 comprises a nitride.

A patterned masking layer 522 is formed over the stop layer 504. Openings in the patterned mask layer 522 are formed where vertical doped regions are to be formed. Vertical doped regions are formed in sections 122, 124, 126, and 134. Thus, the patterned mask layer 522 substantially covers both the stop layer 504 of the sections 132 and 136. In certain embodiments, exposed portions of pad layer 502 and stop layer 504 are removed to expose portions of semiconductor layer 304. In another embodiment (not shown), the exposed portions of the pad layer 502 or both the pad layer 502 and the stop layer 504 are not etched. The presence of the pad layer 502, or both the pad layer 502 and the stop layer 504, may help to reduce the implant channeling phenomenon during subsequent implantation processes.

A portion of the semiconductor layer below the opening of the patterned mask layer 522 is implanted to form a vertical doped region 524 of the doped structure 526. Injection may be performed as a single injection process or as a plurality of injection processes. When a plurality of implantation processes are performed, they may be used for different energy, different species, or different energy and paper vertical doped regions 524. The conductivity type of the vertical doped region 524 is the same as the buried doped region 106 and may be the opposite of the conductivity type of the buried conductive region 102. In a particular embodiment, the vertical doped region 524 is p-type and approximately 10 ¹⁸ atoms / cm ³ It has the above dopant concentration. The combination of the vertical doped region 524 and the buried doped region 106 may help to isolate portions of the semiconductor layer 304 within the sections 122, 124, 126, and 134. Doped structure 526 includes a combination of buried doped region 106 and vertical doped region 524. In the figures that follow, the doped structure 526 may be shown without its separate buried doped region 106 and vertical doped region 524. After the implantation process, the patterned mask layer 522 is removed. In another embodiment described below, vertical doped regions can be formed using other techniques, and in another embodiment the vertical doped regions can be omitted.

Another patterned mask layer (not shown) is formed over the location where the pad layer 502 and the stop layer 504 are removed, followed by a trench. At this point in the process, the pad layer 502 and the stop layer 504 may be patterned in the sections 132 and 136. If the pad layer 502, or both the pad layer 502 and the stop layer 504, are not patterned within the sections 122, 124, 126, and 134, the sections 122, 124, 126, and 134. Pad layer 502, or pad layer 502 and stop layer 504, is patterned with corresponding portions within sections 132, 136. After the pad layer 502 and the stop layer 504 are patterned in suitable sections, other patterned mask layers are removed.

As shown in FIG. 6, sidewall spacers 622 are formed adjacent the openings in pad layer 502 and stop layer 504. The sidewall spacers 622 may be used to determine the width of subsequent trenches and the width of the remaining portion of the doped structure 526 lying along the sidewalls of the trenches. The sidewall spacers 622 may be formed by depositing a sacrificial layer and anisotropically etching the sacrificial layer. In certain embodiments, the sacrificial layer can include oxides, nitrides, oxynitrides, or any combination thereof. In certain embodiments, the sacrificial layer and the stop layer 504 have different compositions. The thickness of the sacrificial layer may be about 900 nm or about 700 nm or less, or about 50 nm or about 100 nm or more.

The exposed portions of the semiconductor layer 304 and the doping structure 526 are etched to form trenches 624 that extend from the major surface 305 toward the buried conductive region 102. The trench 624 extends partially or completely through the semiconductor layer 304, or the doped structure 526 and the buried doped region 106. Since the width of trench 624 is not so wide, subsequent conductive layers cannot fill trench 624. In certain embodiments, the width of each of trenches 624 is greater than about 0.3 microns or about 0.5 microns, and in another particular embodiment, the width of each of trenches 624 is less than about 4 microns or about 2 microns. After reading this specification, it will be understood by those skilled in the art that narrower or wider widths may be used in addition to the specific dimensions described. The trench 624 may extend into the buried conducting region 102, but may be shallower if necessary or desirable. Trench 624 may be formed using anisotropic etching. In embodiments, it may be performed with a predetermined timed etch, and in another embodiment end point detection (e.g., detection of dopant species such as arsenic or antimony from the buried conducting region 102) and a predetermined timed etch time. overetch) may be used.

Insulating sidewall spacers 626 may be formed along the exposed sidewalls of the trench 624. Insulating spacers may include oxides, nitrides, oxynitrides, or any combination thereof. The layer on which the insulating sidewall spacer 626 is formed is thermally grown or deposited and is anisotropically etched to remove the layer from the bottom of the trench 624. If necessary or desired, an etching process may be performed such that trench 624 extends close to the buried conductive region 102 or further into the buried conductive region 102. In another embodiment, insulating sidewall spacers 626 are not needed or formed at all in trench 624. In certain embodiments, insulating sidewall spacers 626 are used only within trenches 624 of sections 132, 134, and 136, not within trenches 624 of sections 122, 124, and 126. . In other embodiments, various other combinations of any section with or without insulating sidewall spacers 626 may be used.

A conductive layer is formed over the stop layer 504 and in the trench 624, and in certain embodiments, the conductive layer substantially fills the trench 624. The conductive layer can be polycrystalline and can include a metal containing material or a semiconductor containing material. In an embodiment, the conductive layer can include a heavily doped semiconductor material, such as amorphous silicon or polysilicon. In yet another embodiment, the conductive layer includes a plurality of films, such as an adhesive film, a barrier film, and a conductive film material. In certain embodiments, the adhesive film may comprise refractory metals such as titanium, tantalum, and the like. The barrier film may comprise refractory metal nitrides such as titanium nitride, tantalum nitride, or the like, or refractory metal-semiconductor-nitrides such as TaSiN. And the conductive film material may comprise tungsten or tungsten silicide. In certain embodiments, the conductive layer may comprise Ti / TiN / W. The choice of the number of films and the composition of these films depends on the electrical performance, the temperature of the subsequent heat cycle, another measure, or any combination thereof. Refractory metals and refractory metal-containing composites can withstand high temperatures (eg, the melting point of such materials can be 1400 ° C. or higher), can be deposited adaptively, and have a lower body resistance than highly doped n-type silicon. Has After reading this specification, those skilled in the art will be able to determine the composition of the conductive layer to suit their needs for a particular use.

As shown in FIG. 7, portions of the conductive layer overlying the stop layer 504 may be removed to form a conductive structure 724 in the trench 624. Removal may be performed using chemical-mechanical polishing or blanket etching techniques. The stop layer 504 may be used as a polish-stop layer or an etch-stop layer. The polishing or etching process may continue for a relatively short time after reaching the stopper layer 504 to account for the non-uniformity of the conductive layer thickness across the work piece and one or more of the nonuniformity of the polishing or etching operation. As shown in FIG. 7, if necessary or desired, an etching or other removal process can be used to cause the conductive structure 724 to become more concave towards the trench 624. The concave conductive structure 724 allows the vertically-oriented doping portion of the doping structure 526 and the conductive structure 724 to be electrically connected to each other more easily. Conductive structure 724 forms a vertical conducting region. In the form of a completed electronic device, the combination of the conductive structure 724 and the buried conductive region 102 electrically connects the source of the high side power transistor to the drain of the low side power transistor.

Sidewall spacers 622 and exposed portions of insulating sidewall spacers 626 in trench 624 are removed. Removal is performed by an isotropic etching technique using wet or dry etching agents. In certain embodiments, sidewall spacers 622 and insulated sidewall spacers 626 include oxide, and stop layer 504 includes nitride, such that sidewall spacers 622 and insulated sidewall spacers 626 are resistant It may optionally be removed without removing a significant amount of layer 504. At this point in the process, the semiconductor layer 340, the doped structure 526, and portions of the conductive structure 724 are exposed.

In another embodiment (not shown), within the low side power transistor of section 136, a portion of semiconductor layer 304 near trench 624 is doped to form a portion of the drain region of the low side power transistor. can do. Similarly, within the high side power transistor of section 126, a portion of semiconductor layer 304 spaced apart from trench 624 may be doped to form a portion of the drain region of the high side power transistor. The same implantation steps can be used to form all of these doped regions, and a mask can be formed over other sections of the integrated circuit. After the portion of the semiconductor layer 304 of the section 136 is doped, the mask is removed.

In FIG. 8, a conductive plug 824 may be formed to electrically connect the conductive structure 724 to the doping structure 526 (and potentially other regions within the semiconductor layer 304). Conductive plug 824 can be formed using any material and method for forming conductive structure 724, except that in this embodiment conductive plug 82 is recessed in trench 624. The conductive plug 824 and the conductive structure 724 may include the same material or different materials, and may be formed using the same technique or different techniques. Pad layer 502 and stop layer 504 may be removed at this point in the process. In another embodiment, when a relatively flat surface is desired (e.g., the top of the conductive plug 824 is at the same elevation as the major surface 305 of the semiconductor layer 304), the semiconductor The portion of the conductive plug 824 overlying the layer 304 can be removed.

At this point in the process, the formation of the electronic component adjacent to the major surface 305 may begin, or if the manufacture of the electronic component has already begun, the production may continue. 9 illustrates an partially formed integrated circuit after part of the fabrication process has been performed. An injection barrier layer (not shown) may be formed over the major surface 305. Doped regions may be selectively formed in semiconductor layer 304 and in interior regions 426 and 428, respectively. The doped region may include drain regions 902 and 904 for high side and low side power transistors, respectively. Each of the drain regions 902 and 904 includes a relatively high dopant concentration and a relatively deep portion, and a relatively low dopant concentration and a relatively shallow portion. The relatively deep portions are designed to be highly conductive and at high voltages, while the relatively shallow portions are somewhat more resistive, and subsequently reduce the voltages near the gate dielectric layer and the gate electrode. Under normal operating conditions where a high voltage is applied to the drain of a high side or low side power transistor, all or most of the relatively shallow portion of the drain region 902 or 904 will be in a carrier depletion state, and the drain region 902 or 904 All or most of the relatively deep portion will be in an undeleted of carrier. In certain non-limiting embodiments, the relatively shallower portions of the drain regions 902 and 904 are horizontally-oriented doped regions spaced from the buried conducting region 102. In normal operating conditions, the primary charge carriers (electrons) or current flow through the relatively shallower portions of the drain regions 902 and 904 will be in the horizontal direction.

The relatively deep portions of the drain regions 902 and 904 can be formed using the same mask layer and doping parameters. This relatively deep portion may comprise a dopant type that is opposite to the dopant type of the doping structure 526 and may be approximately 10 ¹⁹ atoms / cm ^3. May have a dopant concentration of greater than or equal to, and the relatively shallow portion may comprise a dopant type opposite to the dopant type of the doping structure 526, and approximately 10 ¹⁹ atoms / cm ³ And a dopant concentration of less than about 10 ¹⁶ atoms / cm ³ or greater. In certain embodiments, these relatively deep portions can be formed using the same mask layers, the same implant species, and other implant parameters, and the relatively shallow portions are the same mask layers, implant species, and other implants from each other. It can be formed using a parameter. However, the mask layer, implant species, and parameters may differ for relatively deep portions as compared to relatively shallow portions.

This relatively shallow portion has a thickness in the range of approximately 0.1 microns to approximately 0.5 microns and extends laterally from the relatively deep portion to the range of approximately 0.2 microns to approximately 2.0 microns. The lateral dimension (from the vertically oriented conductive structure, or the relatively deep portions of the drain regions 902 and 904) may be determined depending on the voltage difference between the source and the drain of the power transistor to be formed. As the voltage difference between the source and the drain of the transistor increases, the lateral dimension may also increase. In an embodiment, the voltage difference is about 30V or less, and in yet another embodiment, the voltage difference is 20V or less. The highest doping concentration in the relatively shallow portion may range from approximately 2 x 10 ¹⁷ atoms / cm ³ to approximately 2 x 10 ¹⁸ atoms / cm ³ , in certain embodiments approximately 4 x 10 ¹⁷ atoms / cm ³ at approximately 7 x 10 ^It may range from ¹⁷ atoms / cm ³ .

In alternative embodiments, the relatively shallow portions of the drain regions 902 and 904 may extend continuously across the length of the unit cells of the high side and low side power transistors (ie, regions where channel and source regions will be formed subsequently). Stretched out). Doping of the channel region to be described later is increased correspondingly to counter-dope a portion of the drain region in the channel region. An advantage of allowing the relatively shallow portions of the drain regions 902 and 904 to extend into the channel region is to reduce or eliminate the effects of misalignment of the drain mask layer. In a further embodiment, this mask layer is removed to allow an implantation process to form relatively shallow portions of the drain regions 902 and 904 continuously over the entire work piece.

An insulating layer 922 is formed over the conductive plug 824. The insulating layer 922 includes two or more different types of regions having different thicknesses. In fact, the insulating layer 922 has a terraced configuration. As shown in FIG. 9, in the high side and low side power transistors, the insulating layer 922 includes three regions each having a different thickness. The insulating layer 922 may or may not include an injection blocking layer. A relatively thin region of the insulating layer 922 lies on the relatively shallow portions of the drain regions 902 and 904, and above the portion of the semiconductor layer 304 close to the main surface 305 and outside the drain regions 902 and 904. Is placed. A relatively thick region of insulating layer 922 lies over the relatively deep portions of drains 902 and 904. The middle region of the insulating layer 922 may lie between a relatively thin region and a relatively thick region and is an optional feature.

In an embodiment, the relatively thin region has a thickness of at least about 0.02 microns or at least about 0.05 microns, and in yet another embodiment, the relatively thin region has a thickness of about 0.2 microns or less or about 0.1 microns or less. In an embodiment, the relatively thick areas have a thickness of at least about 0.15 microns or at least about 0.25 microns, and in yet another embodiment, the relatively thick areas have a thickness of about 0.8 microns or less or about 0.5 microns or less. The intermediate region (between relatively thin and relatively thick regions) may have a thickness that is substantially equal to a relatively thin region, or a relatively thick region, or a thickness between a relatively thin region and a relatively thick region. In an embodiment, the middle region has a thickness of at least about 0.05 microns or at least about 0.15 microns, and in yet another embodiment, the middle region has a thickness of about 0.5 microns or less or about 0.25 microns or less. In certain embodiments, the relatively thin region has a thickness in the range of approximately 0.03 microns to approximately 0.08 microns, the relatively thick region has a thickness in the range of approximately 0.3 microns to approximately 0.5 microns, and the middle region ranges from approximately 0.13 microns to approximately 0.2 microns. Has a thickness of.

The insulating layer 922 may be formed by various other techniques, and may be formed in various other shapes as shown in the cross-sectional view. The insulating layer 922 may be formed from a single insulating film or a plurality of insulating films deposited over the work piece. The master insulating film or the plurality of insulating films may comprise an oxide, nitride, oxynitride, or any combination thereof. In particular embodiments, the characteristics of the insulating layer 922 may differ for points near the injection blocking layer 1100 and points close to the corresponding injection blocking layer 1100. In an embodiment, the composition of the insulating layer 922 may vary during or between depositions. For example, the oxide film may be closer to the semiconductor layer 304 and the nitride film may be deposited over the oxide film. In another embodiment, dopants such as phosphorus may be included at increasing concentrations during the later part of the deposition. In yet another embodiment, the stress in the film can be altered by changing deposition parameters (eg, radio frequency power, pressure, etc.) even though the composition is substantially the same across the thickness of the insulating layer 922. . In further embodiments, the combinations described above may be used. Masks are formed over relatively thick and intermediate areas, and patterning techniques are used to obtain the required shape. Such techniques include isotropically etching portions of the insulating layer 922, etching sidewall etching of the mask instead of etching and placing the insulating material thereon, etching sidewalls of the mask etching and placing the insulating material thereon. Using the advantages of different compositions (the doped oxide is etched faster than the undoped oxide), forming a pattern and then forming sidewall spacers, another suitable technique, or any combination thereof. Include.

A conductive layer 944 is deposited over the insulating layer 922 and patterned to form an opening 946 where a drain contact structure is to be fabricated following the drain region 902. Conductive layer 944 may comprise a conductive material, or may be conductive, for example, by doping. More specifically, conductive layer 944 may be a doped semiconductor material (eg, heavily doped amorphous silicon, polysilicon, etc.), a metal containing material (refractory metal, refractory metal nitride, refractory metal silicide, etc.), or any thereof. It can include a combination of. Conductive layer 944 has a thickness ranging from approximately 0.05 microns to approximately 0.5 microns. In a particular embodiment, conductive layer 944 is a conductive electrode layer to be used to form the conductive electrode. The conductive layer 944 is patterned so that subsequent drain contact structures are not electrically shorted to the conductive layer 944. The portion of the conductive layer 944 overlying the conductive plug 824 in the sections 122, 124, 132, and 134 is an electric field or other from the conductive plug 824 that is electrically connected to the buried conductive region 102. From other electrical effects, it may be helpful to shield the interconnects formed over conductive layer 944 (overlying conductive layer 944).

10 shows a cross-sectional view of a substantially completed high side and low side power transistor. Many features of the transistor have been described above, and additional features have also been described. In FIG. 10, an insulating layer 1402 is formed over the conductive layer 944. The insulating layer 1402 may include a single film or a plurality of films. Each film in insulating layer 1402 may comprise an oxide, nitride, oxynitride, or any combination thereof. In another particular embodiment, the nitride film lies closest to the conductive layer 944 and has a thickness ranging from approximately 0.5 microns to approximately 0.2 microns. The oxide film overlies the nitride film and has a thickness ranging from approximately 0.2 microns to approximately 0.9 microns. An antireflective film may be placed over the oxide film, or may be included somewhere in the insulating layer 1402. For example, the nitride film may be selected to an appropriate thickness to serve as an etch-stop layer and antireflective film. In another embodiment, more or less films may be used, and the thicknesses described herein are exemplary only and are not intended to limit the scope of the invention.

The insulating layer 1402, the conductive layer 944, and the insulating layer 922 are patterned to form openings. Openings are formed over portions of the drain regions 902 and 904. This portion causes portions of the drain regions 902 and 904 to lie under portions of the subsequently formed gate electrode. An insulating layer 1404 is formed along the side of the opening. The insulating spacer 1404 electrically insulates the conductive layer 944 from the subsequently formed gate electrode. Insulating spacers 1404 may include oxides, nitrides, oxynitrides, or any combination thereof, and may have a width in the range of approximately 50 nm to approximately 200 nm at the bottom of the insulating spacer 1404.

Gate dielectric layer 1422, well regions 1426 and 1427, and gate electrodes 1424 and 1425 are formed. A portion of insulating layer 922 is removed by an etching process, and gate dielectric layer 1422 is formed over the exposed surface of the work piece. In a particular embodiment, gate dielectric layer 1422 comprises oxide, nitride, oxynitride, or any combination thereof, and has a thickness in the range of approximately 5 nm to approximately 100 nm, with a conductive layer over gate dielectric layer 1422. Is formed. The conductive layer may be part of the gate electrodes 1424 and 1425, but is not shown separately. The conductive layer may be conductive when deposited, or may be deposited into a high resistive layer (eg, undoped polysilicon) and subsequently conductive. The conductive layer may comprise a metal containing material or a semiconductor containing material. The thickness of the conductive layer is selected such that when viewed from above, the vertical edge of the conductive layer is substantially adjacent to the edges of the drain regions 902 and 904. In an embodiment, the conductive layer is deposited from about 0.1 micron to about 0.15 micron thick.

After the conductive layer is formed, the semiconductor layer 304 may be doped to form well regions 1426 and 1427. The conductivity type of the well regions 1426 and 1427 is opposite to the conductivity type of the drain regions 902 and 904. In an embodiment, boron dopants are implanted through the conductive and gate dielectric layers 1422 to the semiconductor layer 304 to provide p-type dopants for the well regions 1426 and 1427. In one embodiment, well regions 1426 and 1427 have a depth greater than the depth of the source region that is subsequently formed, and in yet another embodiment, well regions 1426 and 1427 have a depth of approximately 0.5 microns or more. In further embodiments, well regions 1426 and 1427 have a depth of about 2.0 microns or less, and in still other embodiments, have a depth of about 1.5 microns or less. As an example, well regions 1426 and 1427 may be formed using two or more ion implantations. In a particular example, each ion implantation is performed using a dose of approximately 1.0 x 10 ¹³ atoms / cm ² , with two ion implantations having an energy of 25 KeV and approximately 50 KeV. In another embodiment, more or less ion implantation may be performed in the well region forming step. Different doses may be used at different energies, and higher or lower doses, higher or lower energies, or any combination thereof may be used to meet the need for a particular use.

In an alternative embodiment (not shown), when a portion of the relatively shallow portion extends across the unit cell of the transistor, the well region 1426 and 1427 to compensate for the relatively shallow portion of the drain regions 902 and 904. The dose of ion implantation to form is increased. In another embodiment, prior to forming the conductive layers for the gate electrodes 1424 and 1425, an implantation process is performed to form the well regions 1426 and 1427, with portions of the conductive layers in the gate electrodes 1424 and 1425. Instead, sidewall spacers 1404 are used as hardmask edges. In further specific embodiments, these two embodiments may be combined.

Additional conductive material is deposited over the conductive layer and etched to form gate electrodes 1424 and 1425. Additional conductive materials may include any of the materials described above in connection with conductive layers deposited over gate dielectric layer 1422 prior to forming well regions 1426 and 1427. Similar to the conductive layer described above, the additional conductive material may be conductive when deposited, or may be deposited as a high resistive layer (eg, undoped polysilicon) and subsequently conductive. The conductive layer and the additional conductive material may have the same composition or different compositions. The thickness of the composite conductive layer comprising the conductive layer and the additional conductive material ranges from approximately 0.2 microns to approximately 0.5 microns. In certain embodiments, the additional conductive material includes polysilicon and may be doped with n-type dopants during deposition, or subsequently doped using ion implantation or another doping technique. The composite conductive layer may be anisotropically etched to form gate electrodes 1424 and 1425. In the illustrated embodiment, the gate electrodes 1424 and 1425 are formed without using a mask and take the form of sidewall spacers. An insulating layer (not shown) may be thermally grown from the gate electrodes 1424 and 1424, or may be deposited over the work piece. The thickness of the insulating layer may range from approximately 10 nm to approximately 30 nm.

Source regions 1432 and 1433 may be formed using ion implantation. Source regions 1432 and 1433 are heavily doped and have a conductivity type opposite that of well regions 1426 and 1427, and the same conductivity type as drain regions 902 and 904. The portion of the well region 1426 that lies between the source region 1432 and the drain region 902 and under the gate electrode 1424 is a channel region for the high side power transistor, and the source region 1433 and the drain region 904 The portion of the well region 1427 that lies between and under the gate electrode 1425 is the channel region for the lowside power transistor.

An insulating layer 1428 is formed along the gate electrodes 1424 and 1425 and covers portions of the source regions 1432 and 1433 adjacent the gate electrodes 1424 and 1425, where the source regions 1432 and 1433 are formed. The exposed portion lies close to the conductive plug 824. Insulating spacer 1428 may comprise oxides, nitrides, oxynitrides, or any combination thereof, and has a width in the range of approximately 50 nm to approximately 500 nm at its base.

Exposed portions of the source regions 1432 and 1433 are etched to expose portions underlying the well regions 1426 and 1427, respectively. When the source regions 1432 and 1433 are etched, portions of the conductive plug 824 may or may not be etched, depending on the composition of the conductive plug 824. When the conductive plug 824 and the semiconductor layer 304 (the well regions 1426 and 1427 and the source regions 1432 and 1433 are formed in the semiconductor layer 304) are mostly silicon, the source regions 1432 and 1433 When etched through, some or all of the exposed conductive plug 824 may be etched. If the conductive plug 824 and the source regions 1432 and 1433 contain dissimilar materials, the conductive plug 824 will not be substantially etched at all or nearly when etched through the source regions 1432 and 1433. Can be.

Well contact regions 1434 and 1435 are formed in the exposed portions of well regions 1426 and 1427, respectively. Well contact regions 1434 and 1435 have the same conductivity type as well regions 1426 and 1427 and opposite conductivity types as source regions 1432 and 1433. In certain embodiments, the well contact regions 1434 and 1435 are approximately 10 ¹⁹ atoms / cm ³ The above dopant concentrations allow the ohmic contacts to be subsequently formed.

In yet another embodiment (not shown), an additional implantation process having the same conductivity type as the well regions 1426 and 1427 and having a conductivity type opposite to the source regions 1432 and 1433 is performed by the source regions 1432 and 1433. It can be used to form a well contact region below. Additional implantation processes may be performed before or after forming source regions 1432 and 1433 and prior to forming insulating spacers 1428. In this embodiment, the well contact region lies substantially below all source regions 1432 and 1433. After the well contact regions are formed with the source regions 1432 and 1433, an insulating spacer 1428 is formed to cover only a portion of the source regions 1432 and 1433. The etching process described above is performed to remove portions of source regions 1704 and 1724 and to expose portions of underlying well contact regions.

Returning to the embodiment shown in FIG. 10, a portion of insulating spacer 1428 is etched to expose portions of source regions 1432 and 1433. A conductive strap 1462 is then formed to electrically connect the source region 1432, the well contact region 1434, and the corresponding conductive plug 824 together, and other conductive straps 1462. ) Is formed to electrically connect the source region 1433 and the well contact region 1435 with each other. In certain embodiments, refractory metals such as Ti, Ta, W, Co, Pt may be deposited on the work piece and selectively react with exposed silicon (eg, substantially monocrystalline or polycrystalline silicon) to form metal silicides. The unreacted portion of the refractory metal is placed over the insulating layer 1402 and the insulating spacer 1428 is removed, thereby leaving the conductive strap 1462. Although not shown, top portions of the gate electrodes 1424 and 1425 may be exposed and may react with the refractory metal. However, the metal silicide in such a location is spaced apart from the metal silicide in contact with the source regions 1432 and 1433 and the well contact regions 1434 and 1435, and thus the gate electrodes 1424 and 1425, the source regions 1432 and No electrical short is formed between any of 1433 and the well regions 1426 and 1427. As shown in FIG. 10, at this point in the process, high side and low side power transistors are formed. In order to suitably connect different portions of the integrated circuit with terminals or other portions of the integrated circuit, subsequent processes may be performed to form interconnects or other wiring.

Although not shown, additional or fewer layers or features may be used to form the electronic device as needed or required. Although not shown, a field isolation region may be used to help electrically isolate a portion of the high side power transistor from the low side power transistor. In yet other embodiments, more isolation levels and interconnect levels may be used. For example, specific interconnect levels may be used for the conductive layer 944, and different interconnect levels may be used for the gate electrodes 1424 and 1425. A passivation layer can be formed on the work member. After reading this specification, those skilled in the art will be able to determine the layers and features for their particular use.

As shown in FIG. 10, the electronic device may include many other power transistors that are substantially the same as the power transistor. The high side power transistors may be connected in parallel with each other, and the low side power transistors may be connected in parallel with each other. Such one or more parallel connections may provide a sufficiently effective channel width of the electronic device to support the relatively high current flow used during normal operation of the electronic device. In a particular embodiment, each power transistor can be designed to have a maximum source-drain voltage difference of approximately 30V, and a maximum source-gate voltage difference of approximately 20V. During normal operation, the source-drain voltage difference is approximately 20V or less and the source-gate voltage difference is approximately 9V or less. The conductive layer 944 can be maintained at a substantially constant voltage with respect to the source terminal of either the high side or the low side transistor during normal operation to reduce drain-gate capacitance. In certain embodiments, conductive layer 944 may be substantially 0V, in which case conductive layer 944 may act as a ground plane. In another embodiment, a portion of the conductive layer 944 adjacent to the high side power transistor may be connected to the source region 1432, and another portion of the conductive layer 944 adjacent to the low side power transistor may be connected to the source region 1433. ) Can be connected.

Further processing may be performed to form an electronic component that may be partially or fully placed within the interior portion 426 or 428 or other portion of the semiconductor layer 304. Electronic components may include transistors, resistors, capacitors, diodes, and the like. Transistors may include field effect transistors or bipolar transistors. Each transistor has a source-drain or emitter-collector voltage difference of less than approximately 10V, a source-drain or emitter-collector voltage difference between approximately 10V and approximately 50V, or a source-drain or emitter greater than approximately 50V. Can be designed to operate normally with collector voltage difference. 11-15 illustrate electronic components that may be formed within sections 122, 124, 132, and 134, as shown in FIG. 9.

11 shows a cross sectional view of a MOSFET structure. Semiconductor region 1002 may be located within semiconductor layer 304 or within inner portion 426 or 428. Gate dielectric layer 1022 and gate electrode 1024 may be formed over semiconductor region 1002. Source / drain regions 1004 may be formed in portions of the semiconductor region 1002. Formed after sidewall spacer 1026 forms an extended portion of the lightly doped drain or source / drain region 1004 and before forming the heavily doped relatively deep portion of source / drain region 1004. Can be. The transistor structure shown in FIG. 11 may be a p-channel transistor or an n-channel transistor. The transistor may be an enhancement mode transistor or a depletion mode transistor. In a particular embodiment, source / drain region 1004 has a conductivity type that is opposite to the conductivity type of semiconductor region 1002. In yet another embodiment, the source / drain regions 1004 may be electrically connected to each other, with the final structure acting as a capacitor.

Additional transistors may be formed to form inverters, latches, and the like. In a particular embodiment, a transistor having a transistor structure similar to that shown in FIG. 11 causes the n-channel transistor to be partially or wholly placed in the semiconductor layer 304 in section 122, and the p-channel transistor is in section ( Partially or wholly within the inner portion 426 of 124, another n-channel transistor partially or entirely within the inner portion 428 in section 132, and another p-channel transistor Partially or wholly within the inner portion 426 of the section 134. The electronic components in sections 122 and 124 may be at least a portion of the control circuit used to control the control electrodes (eg, gate electrode or base region) of the high side power transistor, and the electronic components in sections 132 and 134. The element may be at least part of a control circuit used to control a control electrode (eg, a gate electrode or a base region) of the low side power transistor.

12 shows a cross sectional view of a resistance. Semiconductor region 1102 may be located within semiconductor layer 304 or within inner portion 426 or 428. Terminal region 1104 may be formed in part of the semiconductor region 1102. A resistor body region 1126 may be formed between the terminals. The resistive body region 1126 is more lightly doped than the terminal region 1104 and has a substantially greater effect on the resistance of the resistance than the terminal region 1104. In a particular embodiment, the terminal region 1104 and the resistive body region 1126 have a conductivity type that is opposite to the conductivity type of the semiconductor region 1102 and completely lies within the semiconductor region 1102.

13 shows a cross sectional view of a bipolar transistor. Semiconductor region 1202 may be located within semiconductor layer 304 or within interior portion 426 or 428. The collector 1222 may be part of the doping structure 416 or 418, or may be separated and spaced apart from the doping structure 416 or 418. Doped region 1224 lies adjacent to collector 1222. In certain embodiments, doped region 1224 has the same conductivity type as collector 1222 and has a highest dopant concentration that is lower than that of collector. Doped region 1224 is optional and may be omitted in another embodiment. In the embodiment shown in FIG. 13, collector 1222 surrounds the bottom and side of base area 1242. Base region 1242 has a conductivity type opposite that of collector 1222 and has a higher dopant concentration, which is higher than collector 1222. Contact region 1244 has the same conductivity type as base region 1242 and has the highest dopant concentration, which is higher concentration than base region 1242. The contact region may cause an ohmic contact to be formed in the base region 1242. Emitter region 1262 lies adjacent to base region 1242. Emitter region 1262 has a conductivity type opposite that of base region 1242 and has a higher dopant concentration, which is higher concentration than base region 1242. The bipolar transistor as shown may be an npn or pnp bipolar transistor. As shown in FIG. 13, the bipolar transistor may be a vertical transistor (determined by the main current flow) or a lateral transistor (not shown).

14 shows a cross sectional view of another MOSFET structure. The particular transistor of FIG. 14 is a side diffusion MOSFET (LDMOS) transistor. Semiconductor region 1302 may be located within semiconductor layer 304 or within inner portion 426 or 428. Doped regions 1304 and 1306 may include well regions having different conductivity types. Dopant concentrations for the doped regions 1304 and 1306 may be the same or different from each other.

Gate dielectric layer 1322 and gate electrode 1324 may be formed over doped region 1304. Source region 1362 and body contact region 1164 may be formed in portion of doped region 1304, and drain region 1366 may be formed in portion of doped region 1306. Source region 1362 has a conductivity type opposite to doped region 1304 and has a higher dopant concentration, which is higher than doped region 1304. Body contact region 1164 has the same conductivity type as doped region 1304 and has the highest dopant concentration, which is higher than doped region 1304. In a particular embodiment, source region 1362 and body contact region 1164 are electrically connected to each other. Drain region 1366 has the same conductivity type as doped region 1306 and has a higher dopant concentration that is higher than doped region 1366. The portion of the doped region 1304 between the source region 1362 and the doped region 1306 and adjacent the gate dielectric layer 1322 is the channel region for the LDMOS transistor. The LDMOS transistor may be an n-channel transistor or a p-channel transistor.

FIG. 15 shows a cross-sectional view of a particular transistor having features from high and low power transistors as shown and described with respect to FIG. 10. Unlike the high side and low side power transistors, these particular transistors do not have electrodes electrically connected to the buried conducting region 102. Thus, the transistor structure is spaced apart from the conductive structure 724 and the conductive plug 824. The particular transistor may be an n-channel transistor or a p-channel transistor. The advantage of this structure over the LDMOS transistor of FIG. 14 is that no additional processing is required to form the high side power transistor, and inherent electrical characteristics such as threshold and breakdown voltage may be similar to the high side power transistor. .

Bipolar transistors, LDMOS transistors, and specific transistors (all shown in FIGS. 13, 14, and 15) are at higher source and drain voltages than digital logic transistors, such as the transistors shown in FIG. It may be a power transistor that operates normally with a lower source-drain voltage than the power transistor. In a non-limiting example, such transistors can operate normally with a source-drain voltage of approximately 10V to approximately 50V, and the high side and lowside power transistors normally operate at source-drain voltages of approximately 50V or more. In another embodiment, different ranges of source-drain voltages may be used for the power transistors. If necessary or required, any transistor as shown in FIG. 13, 14, or 15 may be used in place of, or in conjunction with, another transistor shown in FIG. 13, 14, or 15. Can be.

10-15 include some electronic components that may be formed as described herein. After reading this specification, those skilled in the art will understand that other electronic components may be formed in addition to or in place of the electronic components described above. In yet another embodiment, the sections 122, 124, 126, 132, 134, and 136 need not all be formed. For example, if only n-channel transistors are formed and no p-channel transistors are formed, sections 124 and 134 may not be needed and may be omitted, and only p-channel transistors are formed and the n-channel transistors may be If not formed, sections 122 and 132 are not needed and can be omitted. After reading this specification, one skilled in the art can tailor the design of an integrated circuit to a particular use.

In accordance with the concepts described herein, an integrated circuit can be formed such that the high side and low side power transistors are integrated using control logic and potentially other circuitry within different portions of the same die. The parasitic resistance and inductance can be lowered because wire bonds between the control circuitry for the power transistor, the high side power transistor, and the separate die for the low side power transistor are no longer needed. have. This lower parasitic resistance and inductance improves the performance of the electronic device and allows smaller electronic devices to be formed.

One unique advantage of parasitic inductance reduction between transistors in different regions is the delay time of receiving control signals at the control electrodes of the high side and low side transistors when switching between high side and low side power transistors. Can be reduced and the switching or output node's ringing can be reduced. During this transient, the parasitic inductance between the high side and low side power transistors reacts with the output capacitance of the low side transistor to form a resonant circuit. Such resonant circuits can cause undesirable high frequency voltage swings on the output nodes of the circuit. Such voltage swings can introduce undesirable voltage stress in the device, complicate circuit element control, and reduce the overall power conversion efficiency of the voltage regulator. Embodiments described herein allow for reduction of parasitic inductances between high side and low side power transistors, thereby minimizing output node ringing. Moreover, the remaining parasitics between the high side and low side power transistors are governed by the resistance of the buried conductive layer, allowing more effective control of the ring at the output node.

The parasitic resistance between the two transistor types can be further reduced by combining small high side power transistors and small low side power transistors in pairs, and then these multiple pairs of transistors can be connected in parallel to each other to form a more effective device. have. If the average lateral distance between these high side and low side power transistors is less than the thickness of the buried conductive layer, there is no need for current from the high side transistor to reach the low side transistor through the entire thickness of the buried conductive layer, Thus, total parasitic resistance is reduced.

Other embodiments may be used if desired or desired. Alternatives to variations in the well region and other doped regions in the semiconductor layer 304 and the vertical conductive structure will be discussed.

As described above in FIG. 4, the section 124 includes a buried doped region 206 and a vertical portion 406, wherein the doping structure 416 surrounds an inner portion 426 of the semiconductor layer 304. Includes a representation of a portion of an integrated circuit. As mentioned above, the doping structure may not be necessary. In FIG. 16, a doped region 1526 can be formed by doping the portion of the semiconductor layer on which the inner portion 426 would otherwise be placed. In a particular embodiment, an injection blocking layer (similar to the injection blocking layer 402 of FIG. 4) and a mask layer are formed over the semiconductor layer 304. In this embodiment, the opening of the mask layer corresponds to the position where the dopant is injected into the semiconductor layer 304. The dopant is implanted into the semiconductor layer 304 to form the doped region 1526. The conductivity type of the doped region 1526 may be the same as or different from the conductivity type of the semiconductor layer 304. Doped region 1526 may itself be a well region or may be part of a larger well region that includes a portion of semiconductor layer 304. In a particular embodiment, the dopant concentration of the doped region 1526 is closer to the dopant concentration of the semiconductor layer 304 than the buried doped region 106. Processing may continue as described above. Doped regions similar to the doped regions 1526 may be formed in place of the doped structures 416 and 418 and the inner portions 426 and 428 of the sections 134 and 132, respectively, or the semiconductor layer of the section 122. It may be formed in the portion of. After reading this specification, those skilled in the art will appreciate whether a particular section of an integrated circuit is formed with a doped region similar to the doped region 1526, or a combination of doped structures 416 and 418 and inner portions 426 and 428. And the position at which it is formed, or whether nothing is formed (e.g., no doped regions or combinations thereof are formed).

As described above, after forming the vertical doped region 524 of the doping structure 526 in FIG. 5, and the trench 624 in FIG. 6, an insulating sidewall spacer 626 is formed along the walls of the trench 624. do. In yet another embodiment, one or more of the vertical doped region 524 and the insulating sidewall spacer 626 are omitted. The vertical doped region 524 is a potential interfacial area between the vertically doped region 524 and the semiconductor layer 304 in the same section as the region (viewed from above) occupied by the buried doped region in a particular section. May be omitted when more substantial. Furthermore, those skilled in the art can consider the electric field in the section to determine if the vertical doped region 524 can be omitted without significant adverse effects. Typically, if any vertical doped region 524 is used, additional additional doped region 524 may be used without causing additional processing steps or complexity.

Referring to FIG. 17, in one particular embodiment, the process sequence used to form the vertical doped region 524 is not performed. Trench similar to trench 624 is formed that extends partially or completely through semiconductor layer 304. In this particular embodiment, the process sequence used to form the insulating sidewall spacer 626 is omitted. Subsequently, using any of the techniques described above, a conductive structure 724 is formed in the trench, and then a conductive plug 824 is formed. The buried conductive region 106 and the buried conductive structure 102 are electrically connected to each other by the conductive structure 724.

In another embodiment, vertical doped regions, such as vertical doped region 524, may be formed using different techniques, and conductive plugs 824 may not be formed in all sections or at all. In FIG. 18, the doping sequence used to form the vertical doped region 524 can be omitted. After forming the trench extending through the semiconductor layer 304, a doped semiconductor layer is formed on and within the trench including the pad layer 502 and the stop layer 504 (not shown in FIG. 18). Deposited conformally. The doped semiconductor layer is anisotropically etched to remove portions of the doped semiconductor layer over the stop layer 504 and under the trench, leaving the doped semiconductor spacer 1722. Doped semiconductor spacer 1722 has the same dopant type and dopant concentration as vertical doped region 524 described above. As described above, the insulating sidewall spacer 626 may be formed. The vertical conductive structure 1724 can be formed using any of the techniques described with respect to the vertical conductive structure 1724, except that the top thereof is concave in the trench. If the pad layer 502 and the stop layer 504 are not removed after the insulating sidewall spacer 626 is formed, the pad layer 502 and the stop layer 504 may be removed. In another embodiment, the vertical conductive structure 1724 and the combination of the vertical conductive structure 724 and the conductive plug 824 may be formed in different sections of the same integrated circuit.

In yet another embodiment, another type of vertical conductive structure can be formed. For example, although not shown in FIGS. 7-9, vertical conductive structures may be formed in section 132. Referring to FIG. 19, any of the techniques described with respect to trench 624 may be employed except that trench 1802 only partially passes through semiconductor layer 304 and extends into buried conductive region 102. The trench 1802 may be formed using the same. Insulating sidewall spacers 1804 may be formed using any of the techniques described with respect to insulated sidewall spacers 626. Another etching process may be performed such that the trench extends into the buried conducting region 102. In FIG. 20, the conductive structure 1924 and the conductive plug 1926 are formed using any of the techniques used to form the conductive structure 724 and the conductive plug 824 described above. In another embodiment, a combination of vertical conductive structure 1924 and conductive plug 1926, and a combination of vertical conductive structure 724 and conductive plug 824 may be formed in different sections of the same integrated circuit. In another embodiment (not shown), the trench may not extend fully into the buried conducting region 102. A trench can be formed having a lower portion adjacent to but not reaching the buried conductive layer. A doped semiconductor material may be formed in the trench, and a diffusion operation may be performed to diffuse the dopant into the buried conductive region 102.

After reading this specification, skilled artisans will appreciate that many other embodiments may be utilized without departing from the concepts described herein. Due to the flexibility in the use and formation of different structures and doped regions, those skilled in the art will be able to better enhance existing equipment and techniques or to adapt to different applications without developing process steps or process flows with complex processing sequences. To match the structure and process. If necessary or desired, the conductivity type can be reversed for part or all of the integrated circuit.

Embodiments described herein may include regions having a highest dopant concentration of less than approximately 10 ¹⁹ atoms / cm ³ . If ohmic contact with a metal containing material is required or desired, the portion of this doped region is approximately 10 ¹⁹ atoms / cm ^3. It may be locally doped to have the highest dopant concentration above. In the non-limiting example, the buried doped region 106 is approximately 10 ¹⁹ atoms / cm ³ It may have a highest dopant concentration of less than. If the conductive structure 724 includes W or WSi, the portion of the buried doped region 106 close to the conductive structure 724, such as the portion along the bottom of the trench 624, with a locally highest peak dopant concentration of approximately 10 ^19. Implantation may be made to increase to at least atoms / cm ³ to aid in the formation of ohmic contacts between the buried doped region 106 and the conductive structure 724.

Many different forms and embodiments are possible. Some of these forms and embodiments are described below. After reading this specification, skilled artisans will appreciate that such forms and embodiments are illustrative only and are not intended to limit the scope of the invention.

In a first aspect of the invention, an electronic device may include an integrated circuit including an buried conductive region and a semiconductor layer overlying the buried conductive region. The semiconductor layer has a major surface and an opposing surface, and the buried conductive region lies closer to the opposite surface than the major surface. The electronic device may also include a first vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The electronic device may further include a first doped structure and a first well region. The first doped structure, which is located closer to the opposite surface than the main surface, has a conductivity type opposite to the buried conductive region and is electrically connected to the buried conductive region. The first well region may comprise a first portion of the semiconductor layer, wherein the first portion has a first doped structure and has a lower dopant concentration as compared to the first doped structure.

In an embodiment of the first aspect, the first doped structure includes a horizontal portion lying adjacent to the buried conducting region, and a vertical portion lying adjacent to the first vertical conductive structure, and electrically connected to the first vertical conductive structure. do. In another embodiment, the first well region includes a second doped structure, wherein the second doped structure is spaced apart from the first doped structure (enclosing the second doped structure) and in the first doped structure. It has a higher dopant concentration. In another embodiment, the first well region and the buried conducting region have the same conductivity type or opposite conductivity types.

In a further embodiment of the first aspect, the electronic device further comprises a second well region comprising a second portion of the semiconductor layer, wherein the second well region comprises a first well region and a first doped structure; Are spaced apart. In a particular embodiment, the electronic device further comprises a second vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region, wherein the electronic device is spaced apart from the first doped structure and opposite the buried conductive region. And further comprising a second doped structure having a type. The second doped structure may include a vertical portion lying adjacent to the buried conductive region, and a vertical portion lying adjacent to the second vertical conductive structure, and may be electrically connected to the second vertical conductive structure, the second portion of the semiconductor layer I can surround two parts.

In another particular embodiment of the first aspect, the electronic device further comprises a second vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. In addition, the electronic device further comprises a second doped structure spaced apart from the first doped structure, the second doped structure having a conductivity type opposite to the buried conducting area and closer to the opposite surface than the main surface. And electrically connected to the buried conducting area. In another particular embodiment, the second well region further comprises a second doping structure, wherein the second doping structure abuts and abuts the second portion and has a higher dopant concentration compared to this second portion. .

In a further particular embodiment, the electronic device further comprises a third well region comprising a third portion of the semiconductor layer, wherein the third well region is spaced apart from the first and second well regions. In a particular embodiment, the third well region further comprises a second doping structure, wherein the second doping structure abuts and abuts a third portion, and has the same conductivity type as this third portion, It has a higher dopant concentration compared to the part. In another particular embodiment, the electronic device further comprises a fourth well region comprising a fourth portion of the semiconductor layer, wherein the fourth well region is spaced apart from the first, second, and third well regions. It is.

In yet another embodiment of the first aspect, the electronic device further comprises a second vertical conductive structure and a second doped structure. The vertical conductive structure extends through the semiconductor layer and is electrically connected to the buried conductive region. The second doped structure has a conductivity type opposite to the buried conductive region and includes a vertical portion lying adjacent to the buried conductive region and a vertical portion lying adjacent to the third vertical conductive structure. The second doped structure is electrically connected to the second vertical conductive structure. The first well region and the fourth well region have opposite conductivity types. In a particular embodiment, the first well is a p-well region, the second well region is an n-well region, the third well region is another p-well region, and the fourth well region is another n-well region to be.

In a particular embodiment of the first aspect, the integrated circuit further includes a first power transistor and a second power transistor. The first power transistor includes a first current-carrying electrode, a second current carrying electrode, and a first control electrode, wherein the first current carrying electrode is connected to a first terminal. . The second power transistor includes a third current carrying electrode, a fourth current carrying electrode, and a second control electrode. In an integrated circuit, the second current carrying electrode, the third current carrying electrode, and the buried conducting area are electrically connected to each other. The fourth current carrying electrode is connected to a second terminal designed to operate at a voltage different from that of the first terminal. The integrated circuit further includes a first electronic component in the first well region and a second electronic component in the second well region, wherein the first electronic component is connected to the first control electrode. And the second electronic component is part of the first control circuit connected to the first control electrode. Also, the integrated circuit further includes a third electronic component in the third well region and a fourth electronic component in the fourth well region, wherein the third electronic component is connected to the second control electrode. It is part of the circuit, and the fourth electronic component is part of the second control circuit connected to the second control electrode.

In a second aspect, the electronic device can include an integrated circuit including an embedded conductive region and a semiconductor layer overlying the embedded conductive region. The semiconductor layer may comprise a major surface, and the opposite surface, and the buried conducting region may lie closer to the opposite surface than the major surface. Also, the electronic device may include a first vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The electronic device can further include a first well region comprising a first doped structure, wherein the first doped structure is spaced apart from each of the buried conductive region and the first vertical conductive structure. The electronic device may further include a field-effect transistor that lies partially or entirely within the first well region.

In yet another embodiment of the second aspect, the electronic device further includes a second vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region. The electronic device can also include a second doped structure in the semiconductor layer, wherein the second doped structure lies adjacent to the buried conductive region and the first vertical conductive structure. The electronic device may further include a second well region that includes an inner portion of the semiconductor layer. The second doped structure surrounds an inner portion of the semiconductor layer, and the first well region and the second well region have opposite conductive structures.

In a third aspect, a process of forming an electronic device including an integrated circuit can include providing a substrate comprising a semiconductor layer overlying an buried conductive region, wherein the semiconductor layer has a major surface and an opposite surface. The buried conducting area lies closer to the opposite surface than the main surface. The process may also include forming a first doped structure in the semiconductor layer, wherein the first doped structure is placed closer to the opposite surface than the major surface and has a conductivity type opposite to the buried conductive region. Have The process may further comprise forming a first vertical conductive structure extending through the semiconductor layer. In the completed device, the first well region may comprise a first portion of the semiconductor layer overlying the first doping structure and the buried conducting region, the first doping structure and the first vertical conductive structure being electrically connected to each other.

In the third form of embodiment, providing the substrate and forming the first doped structure comprises providing a substrate comprising a first portion of the semiconductor layer over the buried conductive region, the first horizontal of the first doped structure. Selectively doping the first portion of the semiconductor layer to form a portion, and selectively doping the second portion of the semiconductor layer to form a first vertical portion of the first doped structure. In another embodiment, the process includes forming a second well region comprising a second portion of the semiconductor layer, wherein the second well region has a conductivity type opposite to the first well region. In a particular embodiment, the process further includes forming a second horizontal portion of the second doped structure in the semiconductor layer, wherein the second horizontal portion is spaced apart from the buried conductive region. The process may also include forming a second vertical portion of the second doped structure, wherein the second vertical portion lies between the second horizontal portion of the semiconductor layer and the major surface. In the completed device, the second well region further comprises a second doping structure, the second doping structure surrounding the second portion of the semiconductor layer and having a higher dopant concentration than the second portion.

In another particular embodiment of the third aspect, the process further includes forming a third well region comprising a third portion of the semiconductor layer, wherein the third well region is formed of the first and the first wells. 2 is spaced apart from the well area. In a particular embodiment, the process further comprises forming a second horizontal portion of the second doped structure in the semiconductor layer, forming a second vertical portion of the second doped structure, wherein the second The vertical portion lies between the second horizontal portion of the semiconductor layer and the major surface. In the finished device, the third well region comprises a second doping structure, the second doping structure surrounding the third portion of the semiconductor layer, having the same conductivity type as the third portion of the semiconductor layer, and the third It has a higher dopant concentration compared to the part.

In yet another embodiment of the third aspect, the process further includes forming a fourth well region comprising a fourth portion of the semiconductor layer, wherein the fourth well region is a first, second , And a third well region. In a particular embodiment, the process further includes forming a second horizontal portion of the second doped structure of the semiconductor layer, wherein the second horizontal portion is in contact with the buried conductive region. The process also includes forming a second vertical portion of the second doped structure, wherein the second vertical portion of the second doped structure lies between the second horizontal portion of the second doped structure, the semiconductor It extends along most of the layer thickness. The process further includes forming a second vertical conductive structure extending through the semiconductor layer. In the finished device, the second doped structure surrounds the fourth portion of the semiconductor layer, and the first well region and the fourth well region have opposite conductive structures, and the buried conductive region, the second vertical conductive structure, and the doped region are Are electrically connected to each other. In another particular embodiment, the first well region is a p-well region, the second well region is an n-well region, the third well region is another p-well region, and the fourth well region is another n Well area.

In a particular embodiment of the third form, the process includes forming a first electronic component in a first well region, forming a second electronic component in a second well region, a third electronic in a third well region Forming a component, and forming a fourth electronic component in the fourth well region, wherein the first electronic component is part of a first control circuit and wherein the second electronic component is formed. The element is part of the first control circuit, the third electronic component is part of the second control circuit and the fourth electronic component is part of the second control circuit. The process further includes the steps of forming a first current carrying electrode, a second current carrying electrode, and a first control electrode of the first power transistor, a third current carrying electrode, a fourth current carrying electrode of the second power transistor, And forming a second control electrode, and connecting the third current carrying electrode and the third current carrying electrode to the buried conducting region. The process includes connecting the first control circuit to the first control electrode, connecting the second control circuit to the second control electrode, connecting the first current carrying electrode to the first terminal, Connecting the four current carrying electrodes to a second terminal designed to operate at a different voltage than the first terminal.

Not all of the activities or examples described above in the general description are required, no specific activity portion may be required, and one or more additional activities may be performed in addition to the above description. In addition, the order of activities described is not necessarily the order necessary for the activities to be performed.

In addition, certain features described in the context of separate embodiments may be provided in combination in a single embodiment, for clarity. Conversely, various features that are described in the context of a single embodiment can be provided individually or in any subcombination for the sake of brevity. Moreover, reference to a value defined within a range includes each or all values within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, any benefit, advantage, solution to the problem, and any features that arise notably from occurring are not to be construed as critical, necessary, or essential for any or all claims. Does not.

The description and examples of the above-described embodiments are intended to provide a general understanding of the structure of the various embodiments. The descriptions and examples are not intended to be exhaustive or comprehensive of all elements and features of apparatus and systems using the structures or methods described herein. In addition, separate embodiments may be provided in combination in a single embodiment, and vice versa, various features described in the context of a single embodiment may, for brevity, be provided alone or in any sub-combination. Moreover, reference to a value defined within a range includes each or all values within that range. After reading the above description, various other embodiments will be apparent to those skilled in the art. Other embodiments are utilized and derived from the teachings herein, and structural, logical, or other changes will be made without departing from the scope of the present invention. Accordingly, the disclosure should be considered as illustrative and not restrictive.

100: working member 102: investment conductive area
104, 204, 302: semiconductor layers 106, 206, 208: buried doped region
122, 124, 126, 132, 134, 136: section 304: composite semiconductor layer
306, 502: pad layer 308, 504: stop layer
402: injection barrier layers 416, 418, 526: doped structures
522: patterned mask layer 524: vertical doped region
622, 1804: sidewall spacers 624, 1802: trenches
626: insulated sidewall spacers 724, 1924: conductive structure
824, 1926: conductive plugs 902, 904: drain region
922, 1402, 1404: insulating layer 944: conductive layer
1002, 1102, 1302: semiconductor region 1004: source / drain region
1022 and 1422 gate dielectric layers 1024 and 1424 and 1425 gate electrodes
1126: resistance body area 1222: collector
1242: base area 1262: emitter area
1304, 1306, 1526: doped region
1362, 1432, 1433, 1704, 1724: source area 1426, 1427: well area
1428: insulating spacer 1722: doped semiconductor spacer
1724: vertical conductive structure

Claims (5)

An electronic device comprising an integrated circuit,
Buried conductive region,
A semiconductor layer overlying said buried conductive region, said semiconductor layer having a major surface and an opposite surface, said buried conductive region lying closer to said opposite surface than said major surface;
A vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region;
A first doped structure having a conductivity type opposite to the buried conductive region, lying closer to the opposite surface than the major surface, and electrically connected to the buried conductive region; And
A well region comprising a first portion of the semiconductor layer;
The first portion overlies the first doped structure;
Wherein the first portion has a lower dopant concentration as compared to the first doped structure. The method of claim 1,
The first doped structure is:
A horizontal portion lying adjacent to the buried conducting area,
And a vertical portion lying adjacent to the vertical conductive structure and electrically connected to the vertical conductive structure. The method of claim 1,
The well region further comprises a second doped structure:
The second doped structure is spaced apart from the first doped structure;
The first doped structure surrounds the second doped structure;
And the second doped structure has a higher dopant concentration than the first portion of the well region. In an electronic device comprising an integrated circuit:
Investment zone,
A semiconductor layer overlying said buried conductive region, said semiconductor layer having a major surface and an opposite surface, said buried conductive region lying closer to said opposite surface than said major surface;
A vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region;
A well region comprising a doping structure, wherein the doping structure is spaced apart from each of the buried conductive region and the vertical conductive structure; And
An electronic device comprising an integrated circuit comprising a field-effect transistor at least partially lying within a first well region. A processing method for forming the electronic device according to any one of claims 1 to 4 so as to lie within a first well region.

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