KR20110001075A

KR20110001075A - Nonvolatile memory device and operating method thereof

Info

Publication number: KR20110001075A
Application number: KR1020090058466A
Authority: KR
Inventors: 윤미선
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-06-29
Filing date: 2009-06-29
Publication date: 2011-01-06

Abstract

PURPOSE: A nonvolatile memory device and a method for operating the same are provided to increase the convenience during test by selecting one from various reading modes and implementing a reading operation. CONSTITUTION: A memory cell array(110) includes a plurality of memory cells. A mode signal generator(170) generates a first signal for determining the sensing method of data stored in the memory cell. The mode signal generator generates a second signal for determining a bit-line selecting method in a data reading operation. A mode selector(161) receives the first signal and the second signal and selects the reading mode of data stored in the memory cells. A page buffer(120) implements the reading operation of data stored in the memory cells according to the reading mode selected by the mode selector.

Description

Nonvolatile memory device and its operation method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device and a method of operating the same, and more particularly, to a nonvolatile memory device capable of selecting a read / verify method of data stored in a memory cell and a method of operating the same.

The flash memory reads data stored in a memory cell by using a voltage sensing method. However, as the capacity of flash memory increases, the size of memory cells becomes smaller, and coupling between adjacent floating gates and short channel effects are applied while applying a multi-level cell (MLC) technique. Problems such as increased oxide thickness / coupling ratio. In order to solve this problem, various read / verify methods have been developed. Therefore, an apparatus including an algorithm capable of supporting all of these various read / verify methods is required.

An object of the present invention is to provide a nonvolatile memory device capable of performing a read operation by selecting one of various read modes according to a user's needs, and a method of operating the same.

In order to achieve the above technical problem the nonvolatile memory device according to the present invention,

A memory cell array including a plurality of memory cells from which data is read through a bit line;

A mode signal generator configured to generate a first signal for determining a sensing method of data stored in the memory cell and a second signal for determining a method for selecting a bit line during a read operation of the data;

A mode selector configured to receive the first signal and the second signal and select a read mode of data stored in the memory cell; And

And a page buffer configured to read data stored in the memory cell according to the read mode selected by the mode selector.

In this embodiment, the sensing method includes a voltage sensing method of reading data by a voltage difference and a current sensing method of reading data by a current difference, and one of them is the first sensing method. Can be determined by a signal.

In this embodiment, the method of selecting a bit line includes a method of selecting an even bit line or an odd bit line and a method of selecting all bit lines. It can be determined by the second signal.

In this embodiment, the mode selection unit,

Selecting the even bit line to read data using the voltage sensing method and outputting the data from the page buffer, and then selecting the odd bit line to read data using the voltage sensing method and outputting the data from the page buffer. mode;

A second mode of selecting even-numbered bit lines to read data using a voltage sensing method, selecting odd-numbered bit lines to read data using a voltage sensing method, and then outputting all the read data from the page buffer; And

The read mode may be selected as one of the third modes in which all the bit lines are selected to read the data by a current sensing method, and all the read data are output from the page buffer.

In this embodiment, the mode selection unit,

Select the first mode as the read mode when the first signal is '0' and the second signal is '0',

Select the second mode as the read mode when the first signal is '0' and the second signal is '1',

When the first signal is '0' and the second signal is '0', the third mode may be selected as the read mode.

In this embodiment, the mode selector is included in the controller, and the controller may control the read operation of the page buffer according to the read mode selected by the mode selector.

Method of operation of a nonvolatile memory device according to the present invention,

Generating a first signal for determining a sensing method of data stored in a memory cell and a second signal for determining a method for selecting a bit line in a read operation of the data;

Selecting a read mode of the data according to the first signal and the second signal; And

And performing a read operation of the data according to the selected read mode.

In this embodiment, the step of selecting the read mode,

Selecting a first mode as the read mode when the first signal is '0' and the second signal is '0';

Selecting the read mode when the first signal is '0' and the second signal is '1'; And

When the first signal is '0' and the second signal is '0', the method may include selecting a third mode as the read mode.

In this embodiment, the first mode may include selecting an even bit line to read data using a voltage sensing method;

Outputting the data in a page buffer;

Selecting odd-numbered bit lines to read data using a voltage sensing method; And

Outputting the data in a page buffer.

In this embodiment, the second mode may further include: reading data using a voltage sensing method by selecting even-numbered bit lines;

Confirming whether the second mode is selected as the read mode;

If the second mode is selected as the read mode, reading data by a voltage sensing method by selecting an odd bit line; And

Outputting all read data from the page buffer.

In this embodiment, the third mode may include selecting all bit lines and reading the data by a current sensing method; And

Outputting all read data from the page buffer.

According to the nonvolatile memory device according to the present invention, convenience can be increased during testing of the nonvolatile memory device by performing a read operation by selecting one of various read modes controlled by one controller according to a user's needs.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a nonvolatile memory device according to the present invention may include a memory cell array 110, a page buffer unit 120, a Y decoder 130, an X decoder 140, a high voltage generator 150, and a controller ( 160 and the mode signal generator 170.

The memory cell array 110 includes a plurality of memory cell blocks. Each memory cell block includes a plurality of strings, each string including a drain select transistor, a cell string, and a source select transistor. The string is connected between the bit line and the common source line, where the strings are each connected with different bit lines and connected in parallel to the common source line. The cell string includes a plurality of memory cells connected in series. Gates of the drain select transistors included in the different strings are connected to each other to form a drain select line, and gates of the source select transistors included in the different strings are connected to each other to form a source select line. Control gates of memory cells included in different strings are connected to each other to form word lines. A set of memory cells connected to one word line is called one page. Also, a set of even-numbered memory cells among one word line is called an even page, and a set of odd-numbered memory cells is called an odd page.

The drain select transistor electrically connects the cell string to the bit line according to the voltage applied to the drain select line. The source select transistor electrically connects the cell string with the common source line according to a voltage applied to the source select line.

In the nonvolatile memory device, an erase operation, a program operation, and a read operation are performed according to voltages applied to the drain select line, the word lines, and the source select line. The erase operation is performed in units of memory cell blocks, and the program operation or read operation is performed in units of pages.

The controller 160 outputs a program command signal, a read command signal, or an erase command signal according to a command signal CMD input from the outside. In addition, an internal address signal is generated in accordance with the address signal ADD. In addition, control signals for controlling the operation of the page buffer unit 120 during a read operation or a program operation are output. In particular, the controller 160 includes a mode selector 161.

The mode selector 161 selects a read / verify mode for reading data stored in the memory cell according to the signals transmitted from the mode signal generator 170.

The mode signal generator 170 generates a signal for determining a sensing method of data stored in a memory cell and a signal for selecting a bit line during a data read operation, and transmits a signal to the mode selector 161. . The mode signal generator 170 may be implemented as a fuse, a CAM cell, or an option block.

The high voltage generator 150 outputs operating voltages required for a program operation, a read operation, or an erase operation according to a program command signal, a read command signal, or an erase command signal generated from the controller 160.

The X decoder 140 is generated by the high voltage generator 150 as a word line of a selected memory cell block among a plurality of memory cell blocks included in the memory cell array 110 according to an internal address generated by the controller 160. Delivers operating voltages.

The page buffer unit 120 includes page buffers connected to bit lines. In general, page buffers can be connected per pair of bit lines, including even bit lines and odd bit lines (that is, two pages in one word line), but can be connected in one bit line (that is, one One page on a word line) is preferably connected to each bit line in an embodiment of the present invention. In order to reduce the layout area, the page buffer unit 120 may be positioned at both the top and the bottom of the memory cell array 110, and the page buffers may be connected to each bit line by half from the top and bottom of the memory cell array 110. Can be. The page buffer unit 120 outputs data read from the memory cell to the outside during a read operation according to a control signal generated from the controller 160, or transfers data input from the outside to the memory cell array 110 during a program operation. It plays a role.

The Y decoder 130 reads data from the memory cell array 110 and sequentially outputs data stored in the page buffer unit 120 to the outside, or transmits data input from the outside to the page buffer unit 120. do. The Y decoder 130 may operate according to the column address, and the column address may be generated by the controller 160.

2 is a diagram illustrating a read mode according to a method of sensing data and a method of selecting a bit line in a read operation.

Referring to FIG. 2, a voltage sensing method and a current sensing CS method are used to sense data stored in a memory cell. Voltage sensing VS is a method of sensing data stored in a memory cell by a voltage difference (eg, voltage change of a precharged bit line), and current sensing CS is a current difference (eg, bit line). The data stored in the memory cell is sensed by the difference in the amount of current flowing in the circuit. In the case of current sensing CS, a page buffer including an internal circuit different from the page buffer used in general voltage sensing VS may be used.

The read operation of data may be performed for memory cells connected to an even bit line or for memory cells connected to an odd bit line according to an input internal address. After each read operation, data may be output from the page buffer. That is, when an even address is input, data is output after a read operation is performed on a memory cell connected to an even bit line, and when an odd address is input, data is output after a read operation is performed on a memory cell connected to an odd bit line. Can be output.

The read operation of data may be performed for memory cells connected to all bit lines.

In the case of the voltage sensing (VS) method, when an address is input, a read operation may be performed on a memory cell connected to an even bit line, and then a read operation may be performed on a memory cell connected to an odd bit line. As such, after all read operations are performed on all the bit lines, all data read up to that time may be output from the page buffer. It is of course possible to perform the read operation on the even bit line after performing the read operation on the odd bit line. In addition, since a page buffer is connected to one bit line, the read operation may be sequentially performed on each bit line, and then the read data may be output from the page buffer.

In the current sensing (CS) method, after a read operation is simultaneously performed on memory cells connected to all bit lines, all read data may be output from the page buffer.

The read mode of the data stored in the memory cell may be determined by combining the data sensing method and the method of selecting a bit line in a data read operation. That is, the first mode (EOBL & VS, or EOBLVS), which selects an even bit line or an odd bit line and reads data by a voltage sensing method, selects all the bit lines and selects the data by a voltage sensing method. A second mode (ALLBL & VS or SEPVS) to read out and all bit lines may be selected to determine a third mode (ALLBL & CS or ALLBLCS) to read data by a current sensing (CS) method. Since the current sensing (CS) method is based on performing a read operation on all bit lines, there is no mode for selecting an even bit line or an odd bit line and reading data using the current sensing (CS) method, respectively. .

Therefore, in order to select the read mode, a signal for determining a sensing method of data stored in a memory cell and a signal for selecting a bit line during a read operation of data are required.

FIG. 3 is a diagram illustrating a read mode generated according to a signal for determining a data sensing method and a bit line selection method in a read operation of FIG. 2.

Referring to FIG. 3, a signal for determining a sensing method of data stored in a memory cell is defined as a first signal CNFCSS, and a signal for determining a method for selecting a bit line in a data read operation is set as a second signal CNFALLBL. The read mode can be determined. The first signal CNFCSS and the second signal CNFALLBL are generated by the mode signal generator 170 of FIG. 1.

For example, when the first signal CNFCSS is inputted as '0' and the second signal CNFALLBL is inputted as '0', the first mode EBOLVS is selected and the first signal CNFCSS is set to '0'. If the second signal CNFALLBL is input as '1', the second mode SEPVS is selected, and when the first signal CNFCSS is input as '1' and the second signal CNFALLBL is input as '1', the third mode ( ALLBLCS) may be selected.

4 is a block diagram illustrating an input / output relationship between a mode signal generator and a mode selector of FIG. 1.

Referring to FIG. 4, the mode signal generator 170 determines a first signal CNFCSS that determines a method of sensing data stored in a memory cell and a second signal that determines how to select a bit line in a data read operation. CNFALLBL) is generated to transmit signals to the mode selector 161. The mode selector 161 selects a read mode for reading data stored in the memory cell according to the first signal CNFCSS and the second signal CNFALLBL transmitted from the mode signal generator 170, and the controller 160. ) Generates a control signal for enabling the page buffer unit 120 to perform a read / verify operation, and the page buffer unit 120 receives the control signal and performs a read / verify operation according to the selected read mode. .

As described above, the read mode selects an even bit line to read data using a voltage sensing method and outputs the data from a page buffer, and then selects an odd bit line to select data using a voltage sensing method. In the first mode (EOBLVS) that reads and outputs data from the page buffer, an even bit line is selected to read data using a voltage sensing method, and an odd bit line is selected to read data using a voltage sensing method. Subsequently, a second mode (SEPVS) for outputting all read data from the page buffer, a third mode for selecting all bit lines to read data by the current sensing method and outputting all read data from the page buffer It can be (ALLBLCS).

FIG. 5 is a flowchart illustrating a process of performing a read / verify operation by selecting a read mode in the mode selector of FIG. 1.

First, a first signal CNFCSS, which determines a sensing method of data stored in a memory cell, and a second signal CNFALLBL, which determines a method of selecting a bit line during a data read operation, are received from the mode signal generator in operation S510. . The mode selector determines the first signal CNFCSS and the second signal CNFALLBL received from the mode signal generator. If the first signal CNFCSS is '0' and the second signal CNFALLBL is '0', the first mode EBOLVS is selected (S520), and the control unit performs a read / verify operation by the page buffer unit. When the control signal is generated and transmitted to the page buffer unit, the page buffer unit selects an even bit line or an odd bit line according to the first mode (EBOLVS) and performs a read / verify operation by a voltage sensing (VS) method. (S530). If the first signal CNFCSS is '0' and the second signal CNFALLBL is '1', the second mode SESPVS is selected (S540), and all the bit lines are selected in the page buffer unit to sense voltage (VS). A read / verify operation is performed by the method (S550). If the first signal CNFCSS is '1' and the second signal CNFALLBL is '1', the third mode ALLBLCS is selected (S560), and the page buffer unit selects all the bit lines to simultaneously sense current (CS). The read / verify operation is performed by the method (S560).

6 is a flowchart illustrating an operation according to a first mode EOBLVS of the read mode of FIG. 5. Here, the read operation of 2-bit data will be described as an example.

Referring to FIG. 6, the read operation of the upper bit data of the 2 bit data and the read operation of the lower bit data are distinguished and performed (S610). In a read operation of lower bit data, a second read voltage R2 is first applied to a word line connected to a memory cell in which data to be read is stored (S620). Thereafter, the data stored in the flag cell (hereinafter referred to as flag cell data) is checked (S630). If the flag cell data is '0', since the data to be read is 2-bit data, the lower bit data can be immediately read. If the threshold voltage is lower than the second read voltage R2, the stored lower bit data is '1', and if it is high, it is '0'. When the flag cell data is '1', the data to be read is 1 bit data, not 2 bit data. In this case, when the data stored in the memory cell is read using the second read voltage R2, the threshold voltage of the memory cell is increased. Since some are lower than the second read voltage R2 and some are high, incorrect data may be read. Therefore, the first read voltage R1 is applied to the word line again to read data (S640). If the threshold voltage of the memory cell is lower than the first read voltage R1, the stored 1-bit data is '1' and if it is high, it is '0'.

In the read operation of the upper bit data, the first read voltage R1 is applied to a word line connected to a memory cell in which data to be read is stored (S650). Thereafter, the flag cell data is checked (S660). If the flag cell data is '1', the data to be read is 1-bit data, not 2-bit data, and thus 1-bit data can be immediately read. If the threshold voltage of the memory cell is lower than the first read voltage R1, the stored 1-bit data is '1' and if it is high, it is '0'. If the flag cell data is '0', since the data to be read is two-bit data, the second read voltage R2 is applied (S670), and then the third read voltage R3 is applied to the upper level of the two-bit data. The bit data is read (S680). If the threshold voltage is lower than the third read voltage R3, the stored upper bit data is '0' and if it is high, it is '1'.

FIG. 7 is a flowchart illustrating an operation according to a second mode SEPVS in the read mode of FIG. 5.

Referring to FIG. 7, the operation of the second mode SEPVS is basically similar to that of the first mode EOBLVS. However, in the second mode SEPVS, all bit lines are selected and read / verified by the voltage sensing method, whereas in the first mode EOBLVS, an even bit line is selected when an even address is input. A read operation is performed, and the read data is output from the page buffer. In addition, when the odd address is input, a read operation is performed by selecting the odd bit line, and the read data is output from the page buffer.

In the second mode SEPVS, all bit lines are selected to perform a read operation. When an address is input, the even bit line is selected to perform a read operation, and the page buffer unit is not outputted. This means that the data is temporarily stored in a plurality of latches included, and then the odd bit line is selected to perform a read operation to store the read data in the latch of the page buffer unit, and output all the stored data up to that time. That is, the read operation is repeated twice for the even bit line and the odd bit line before the read data is output. Therefore, the read operation portion of the second mode SEPVS is the same as that of the first mode EOBLVS. However, in order to enable the repetitive operation, the second mode SEPVS uses a one time read (OTR) signal generated by the controller. By default, the One Time Read (OTR) signal is set to '0'.

Referring to the dotted line of FIG. 7, when the one-time read (OTR) signal first comes in after the read operation is performed on the even bit line in the first mode EOBLVS, the value is '0' according to an initial condition (S710). After that, the one-time read end signal (OTR End Signal) is set by setting the one-time read (OTR) signal to '1' (S720). After that, it is determined whether the read mode is the second mode (SEPVS) (S730). If the read mode is not the second mode (SEPVS), the data stored in the page buffer unit is output and the operation is terminated. That is, in this case, the operation is substantially the same as the first mode EOBLVS. When the read mode is the second mode (SEPVS), the read operation is not performed on all the bit lines. Therefore, the read operation on the odd bit line is performed again. After the read operation is performed on the odd bit line, the one-time read (OTR) signal is set to '1'. Therefore, the read operation is terminated accordingly, and all the data stored in the plurality of latches of the page buffer unit are output. . That is, the one time read (OTR) signal enables the second mode (SEPVS) to share the algorithm with the first mode (EOBLVS), and the one time read (OTR) signal to the dotted line block of the second mode (SEPVS). It is a signal to escape.

FIG. 8 is a flowchart illustrating an operation according to a third mode ALLBLCS among the read modes of FIG. 5.

Referring to FIG. 8, the operation of the third mode ALLBLCS is the same as the operation of the first mode EOBLVS. However, the third mode ALLBLCS selects all the bit lines and simultaneously performs read / verify operation by the current sensing (CS) method, and then outputs all the read data from the page buffer unit, whereas the first mode (EOBLVS) When the even address is input, the even bit line is selected and a read operation is performed by a voltage sensing (VS) method to read data and output the data from the page buffer unit. A read operation is performed by a sensing method to read data and output data from the page buffer unit.

By the nonvolatile memory device according to an exemplary embodiment of the present invention, a read operation may be performed by selecting one of various read modes controlled by one controller according to a user's need, thereby increasing convenience during testing of the nonvolatile memory device. Can be.

On the other hand, in the detailed description of the present invention has been described with respect to specific embodiments, various modifications are of course possible without departing from the scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

6 is a flowchart illustrating an operation according to a first mode EOBLVS of the read mode of FIG. 5.

100 ... Nonvolatile Memory Device

110 ... memory cell array

120 page buffer

130 ... Y decoder

140 ... X decoder

150.High voltage generator

160 control unit

161 ... Mode selector

170 ... mode signal generator

Claims

The method of claim 1,

The sensing method,

And a voltage sensing method for reading data by a voltage difference and a current sensing method for reading data by a current difference, wherein one of the sensing methods is determined by the first signal.

The method of claim 1,

The method for selecting the bit line,

And a method for selecting even or odd bit lines and all bit lines, wherein one of the bit line selection methods is determined by the second signal.

The method of claim 1,

The mode selector,

And selecting one of the third modes of selecting all bit lines to read the data by a current sensing method and outputting all the read data to the page buffer.

The method of claim 4, wherein

The mode selector,

When the first signal is '0' and the second signal is '0', the first mode is selected as the read mode,

And the third mode is selected as the read mode when the first signal is '0' and the second signal is '0'.

The method of claim 1,

And a mode selector included in the controller, wherein the controller controls a read operation of the page buffer according to a read mode selected by the mode selector.

The method of claim 7, wherein

The sensing method,

A voltage sensing method of reading data by a voltage difference and a current sensing method of reading data by a current difference, wherein one of the sensing methods is an operation of the nonvolatile memory device determined by the first signal. Way.

The method of claim 7, wherein

The method for selecting the bit line,

A method of selecting an even bit line or an odd bit line and a method of selecting all bit lines, wherein one of the bit line selection methods is determined by the second signal.

The method of claim 7, wherein

Selecting the read mode,

If the first signal is '0' and the second signal is '0', selecting a third mode as the read mode.

The method of claim 10,

The first mode is,

Selecting even-numbered bit lines to read data using a voltage sensing method;

Outputting the data in a page buffer;

And outputting the data from a page buffer.

The method of claim 10,

The second mode is,

Selecting even-numbered bit lines to read data using a voltage sensing method;

Confirming whether the second mode is selected as the read mode;

And outputting all read data from the page buffer.

The method of claim 10,

The third mode is,

Selecting all bit lines and reading the data by a current sensing method; And

And outputting all read data from the page buffer.