KR20100138544A - Method of operation a nonvolatile memory device - Google Patents

Method of operation a nonvolatile memory device Download PDF

Info

Publication number
KR20100138544A
KR20100138544A KR1020090057127A KR20090057127A KR20100138544A KR 20100138544 A KR20100138544 A KR 20100138544A KR 1020090057127 A KR1020090057127 A KR 1020090057127A KR 20090057127 A KR20090057127 A KR 20090057127A KR 20100138544 A KR20100138544 A KR 20100138544A
Authority
KR
South Korea
Prior art keywords
cell block
read
retention
block
normal
Prior art date
Application number
KR1020090057127A
Other languages
Korean (ko)
Inventor
김형석
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090057127A priority Critical patent/KR20100138544A/en
Publication of KR20100138544A publication Critical patent/KR20100138544A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits

Landscapes

  • Read Only Memory (AREA)

Abstract

The present invention relates to a method of operating a nonvolatile memory device, comprising: providing a programmed normal cell block and a retention cell block, and performing a read operation using a first read voltage to read the retention cell block. Checking a retention cell reading step, a pass / fail of a read operation of the retention cell reading step, and a read operation using a second read voltage when it is determined to be a pass when checking a pass / fail of the read operation; A normal cell readout step of reading and outputting the normal cell block and a read operation using a second read voltage when the read / write operation is determined to fail when the pass / fail check of the read operation is performed, thereby performing the normal cell block and the retention cell. The normal cell block and the retention cell block using the data read in the entire block reading step, and the data read in the whole block reading step. After re-program, it discloses a method of operating a nonvolatile memory device including the step of returning to the retention cell read step.

Description

Method of operation a nonvolatile memory device

The present invention relates to a method of operating a nonvolatile memory device, and more particularly, to a method of operating a nonvolatile memory device capable of improving retention characteristics.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

In a nonvolatile memory, a plurality of memory cells form one string, and the plurality of strings form one memory cell array. In a conventional driving method of a memory cell, the operation is performed according to threshold voltage levels of two states that define a program and an erase region based on a threshold voltage of a certain level.

For example, if 0V is used as a reference voltage, program and erase operations are performed by using threshold voltage levels of two states, one for each of 0V, which is called a single level cell (SLC). Since the single level cell SLC determines only two states based on the reference voltage, the data storage capability is excellent. However, single level cells (SLCs) have many limitations in processing large amounts of data.

To improve this, a multi-level cell (MLC) scheme has been introduced. Multi-level cells physically have the same structure as single-level cells (SLC). In terms of logic, however, there are at least four levels of threshold voltage levels. That is, although the program area and the erase area are divided based on the reference voltage, at least three different threshold voltage level ranges are defined in the program area. Therefore, since the data structure can be driven at least four data states having the same physical structure as that of the single level cell SLC, data throughput is increased. That is, the multi-level cell type nonvolatile memory device supports a method of storing two data in one memory cell, and accordingly, the driving method based on threshold voltage distribution and bias condition of the memory cell has a single level. Compared to a driving method of a cell type nonvolatile memory device, the method has a complicated method.

In the nonvolatile memory device described above, a threshold voltage distribution of a programmed memory cell may change over time. This is called retention characteristics of nonvolatile memory devices.

According to this retention characteristic, the programmed data is changed during the read operation, thereby causing a data error.

1 is a graph illustrating a threshold voltage distribution of a general nonvolatile memory device.

Referring to FIG. 1, the threshold voltage is programmed to be higher than the program verify voltages PV1, PV2, and PV3 during the program operation of the nonvolatile memory device, and the program verify voltages PV1, PV2, and PV3 are read during the read operation. The read operation is performed using the read voltages R1, R2, and R3 that are as low as a predetermined potential. At this time, the difference (A) between the verify voltage and the read voltage is set to a certain margin.

2 is a graph illustrating that a data error occurs because a threshold voltage distribution changes according to retention characteristics.

Referring to FIG. 2, a data error occurs when a threshold voltage distribution programmed using the program verify voltages PV1, PV2, and PV3 gradually decreases over time to generate a threshold voltage lower than a read voltage.

The technical problem to be solved by the present invention is to divide a memory cell block into a normal memory cell block and a retention block, and to program the retention block in the second state to the fourth state of the threshold voltage distribution, and then retain the read operation. The present invention provides a method of operating a nonvolatile memory device in which a block is read at a retention read voltage higher than a normal read voltage, and the entire memory block is reprogrammed to increase a threshold voltage distribution when failing a read operation.

A method of operating a nonvolatile memory device according to an embodiment of the present invention includes providing a programmed normal cell block and a retention cell block, and performing a read operation using a first read voltage to read the retention cell block. Checking a retention cell readout step, a pass / fail check of a read operation of the retention cell readout step, and a read operation using a second read voltage when it is determined to be a pass at a pass / fail check of the read operation. A normal cell read step of reading and outputting the normal cell block and performing a read operation using a second read voltage when it is determined to fail when a pass / fail check of the read operation is performed; An entire block reading step of reading a tension cell block, and the normal cell block and the retention cell by using the data read in the whole block reading step After the program re-Luck, and your clothing is a step in the retention cell read step.

The first read voltage is higher than the second read voltage.

In the step of providing the retention cell block, the retention cell block is programmed to the first to third program states.

Reprogramming the normal cell block and the retention cell block raises the threshold voltage distribution of the normal cell block and the retention cell block.

The read margin of the normal cell block is set to be larger than the read margin of the retention cell block.

According to an embodiment of the present invention, the memory cell block is divided into a normal memory cell block and a retention block, and the retention block is programmed in the second state to the fourth state of the threshold voltage distribution, respectively, The present invention provides a method of operating a nonvolatile memory device in which a tension block is read at a retention read voltage higher than a normal read voltage, and the entire memory block is reprogrammed to increase a threshold voltage distribution when failing a read operation.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those of ordinary skill in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

3 is a block diagram illustrating a memory block of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 3, a memory block of a nonvolatile memory device is generally divided into a normal cell block 100 for storing or reading program data and a retention cell block 200 for checking a margin according to retention characteristics. do.

The retention cell block 200 is programmed to the second to fourth states among the first to fourth states (the first state is the erase state) during the program operation. That is, the threshold voltage distribution is programmed to be higher than the first to third verification voltages PV1 to PV3. This is to have a threshold voltage distribution in the same state as the program state of the normal cell block 100. In addition, it is possible to program all of the fourth states with the largest change in the moon turn voltage distribution.

4 is a flowchart illustrating a read operation of a nonvolatile memory device according to an embodiment of the present invention.

An operation of a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4 as follows.

First, the read operation of the retention cell block 200 programmed in the second to fourth states is performed. In operation 410, the read operation of the retention cell block 200 is performed during the read operation of the normal cell block 100. First to third retention read voltages R1 ', R2', and R3 'that are higher than the first to third normal read voltages R1, R2, and R3 used are used.

As a result, the difference between the verification voltage used in the program verifying operation, that is, the margin is smaller than the margin during the read operation of the normal cell block 100.

Thereafter, the pass / fail state of the read operation 410 of the retention cell block 200 is checked (420). The pass / fail operation is determined as a pass when the read data of the retention cell blocks 200 programmed in the second to fourth states are the same as the programmed state, and as a fail when they are different.

If it is determined in the pass / fail check step 420 that the read margin of the normal cell block 100 is secured, the read operation of the normal cell block 100 is performed (430). The read operation of 100 may include first to third normal read voltages lower than the first to third retention read voltages R1 ′, R2 ′, and R3 ′ used in the read operation of the retention cell block 200, respectively. (R1, R2, and R3) are used.

If it is determined as a fail in the pass / fail check step 420, all data of the normal cell block 100 and the retention cell block 200 are read. At this time, the read operations of the normal cell block 100 and the retention cell block 200 are lower than the first to third normal read voltages R1 ′, R2 ′, and R3 ′, respectively. (R1, R2, and R3) are used.

Thereafter, the normal cell block 100 and the retention cell block 200 are reprogrammed using the read data to increase the threshold voltage distribution. (450) After the reprogram operation 450, the retention block The read operation of step 410 is returned.

After the read operation step 430 of the normal cell block, the read normal cell data is output to the outside (460).

As described above, a read operation of the retention cell block 200 using a read voltage higher than that of the normal cell block 100 is performed to check that the margin due to retention characteristics is reduced, thereby thresholding the entire cell block. By performing the reprogram operation to increase the voltage, data errors due to retention characteristics can be prevented.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1 is a graph illustrating a threshold voltage distribution of a general nonvolatile memory device.

2 is a graph illustrating that a data error occurs because a threshold voltage distribution changes according to retention characteristics.

3 is a block diagram illustrating a memory block of a nonvolatile memory device according to an embodiment of the present invention.

4 is a flowchart illustrating a read operation of a nonvolatile memory device according to an embodiment of the present invention.

Claims (12)

Providing a programmed normal cell block and a retention cell block; A retention cell reading step of reading out the retention cell block by performing a read operation using a first read voltage; And reading the normal cell block using a second read voltage when the read operation of the retention cell read step is determined to be a pass. The method of claim 1, When the read operation of the retention cell read step is determined to fail. Reading a whole block to read the normal cell block and the retention cell block by performing a read operation using the second read voltage; And And programming the normal cell block and the retention cell block by using the data read in the entire block reading step. The method of claim 1, And the first read voltage is higher than the second read voltage. The method of claim 1, The providing of the retention cell block may include operating the retention cell block programmed in the same state as the program state of the normal cell block. The method of claim 2, The reprogramming of the normal cell block and the retention cell block may increase a threshold voltage distribution state of the normal cell block and the retention cell block. The method of claim 1, The read margin of the normal cell block is set to be larger than the read margin of the retention cell block. Providing a programmed normal cell block and a retention cell block; Reading and outputting the normal cell block if it is determined that the path is read and the retention cell block; And rereading the normal cell block and the retention cell block after reading the retention cell block, and returning to reading the retention cell block. Method of operation. The method of claim 7, wherein Reprogramming the retention cell block and the normal cell block Reading an entire block from the normal cell block and the retention cell block; And And programming the normal cell block and the retention cell block using the data read in the entire block reading step. The method of claim 7, wherein The read operation of the retention cell block is performed using a read voltage higher than that of the normal cell block. The method of claim 7, wherein The providing of the retention cell block may include operating the retention cell block in a first to third program state. The method of claim 7, wherein The reprogramming of the normal cell block and the retention cell block may increase a threshold voltage distribution state of the normal cell block and the retention cell block. The method of claim 7, wherein The read margin of the normal cell block is set to be larger than the read margin of the retention cell block.
KR1020090057127A 2009-06-25 2009-06-25 Method of operation a nonvolatile memory device KR20100138544A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090057127A KR20100138544A (en) 2009-06-25 2009-06-25 Method of operation a nonvolatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090057127A KR20100138544A (en) 2009-06-25 2009-06-25 Method of operation a nonvolatile memory device

Publications (1)

Publication Number Publication Date
KR20100138544A true KR20100138544A (en) 2010-12-31

Family

ID=43512012

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090057127A KR20100138544A (en) 2009-06-25 2009-06-25 Method of operation a nonvolatile memory device

Country Status (1)

Country Link
KR (1) KR20100138544A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11093325B2 (en) 2019-03-26 2021-08-17 SK Hynix Inc. Controller, memory system including the same, and method of operating memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11093325B2 (en) 2019-03-26 2021-08-17 SK Hynix Inc. Controller, memory system including the same, and method of operating memory system

Similar Documents

Publication Publication Date Title
US10353598B2 (en) System and method for refreshing data in a memory device
US9899092B2 (en) Nonvolatile memory system with program step manager and method for program step management
KR100865830B1 (en) Method of reading a memory device
US9036412B2 (en) Memory device and method of determining read voltage of memory device
US9064580B2 (en) Nonvolatile semiconductor memory device and write-in method thereof
KR101014926B1 (en) Programming and verifying method for non volatile memory device
KR102192910B1 (en) Semiconductor device and memory system and operating method thereof
US11404125B2 (en) Memory cell programming applying a programming pulse having different voltage levels
US9484098B1 (en) Smart reread in nonvolatile memory
US8995184B2 (en) Adaptive operation of multi level cell memory
US7885107B2 (en) Methods of programming non-volatile memory cells
US20140321206A1 (en) Reading memory cell history during program operation for adaptive programming
US9058881B1 (en) Systems and methods for partial page programming of multi level cells
TW201413723A (en) Apparatus and methods for carrying out operations in a non-volatile memory cell having multiple memory states
US9342401B2 (en) Selective in-situ retouching of data in nonvolatile memory
US20150228332A1 (en) Method for writing data into flash memory and associated memory device and flash memory
KR20100013957A (en) Method for programming a flash memory device
US9490024B1 (en) Solid state storage device and reading control method thereof
KR20120028035A (en) Non-volatile memory apparatus and method for operating thereof
US20160098197A1 (en) Nonvolatile memory and method with state encoding and page-by-page programming yielding invariant read points
US9047974B2 (en) Erased state reading
KR20100086193A (en) Method of reading a semiconductor memory device
KR20100138544A (en) Method of operation a nonvolatile memory device
KR101303177B1 (en) Non-volatile memory device and operating method of the same
KR20100138545A (en) Method of operation a nonvolatile memory device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination