KR20100133217A - 3d-nonvolatile memory device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A 3D structure nonvolatile memory device and a manufacturing method thereof are provided to improve the degree of integration by three-dimensionally arranging a gate line along a plurality of channel structures. CONSTITUTION: A plurality of gate structures includes a plurality of interlayer insulating layers and gate electrode layers. The plurality of gate structures are extended to a first direction in parallel. A plurality of memory cells are laminated along to the sidewall of the gate structure. The plurality of memory cells are arranged in a first direction and a second direction crossing the first direction.

Description

Non-volatile memory device having a three-dimensional structure and a method of manufacturing the same {3D-NONVOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having a three-dimensional structure and a method of manufacturing the same.

A non-volatile memory device is a memory device in which stored data is retained even if power supply is interrupted. Recently, as the degree of integration of a memory device having a two-dimensional structure that manufactures a memory device in a single layer on a silicon substrate has reached its limit, a non-volatile memory device having a three-dimensional structure in which memory cells are stacked vertically from a silicon substrate has been proposed. .

Hereinafter, a structure and a problem of a nonvolatile memory device having a three-dimensional structure according to the prior art will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a nonvolatile memory device having a three-dimensional structure according to the prior art, and in particular, shows a cross section of a nonvolatile memory device having a bit cost scalable (BICS) structure. However, in this drawing, the bottom selection transistor, the top selection transistor, and the like are omitted for convenience of description and are shown mainly in the memory cell. In addition, the charge blocking film, the charge trap film, and the tunnel insulating film are shown as one film, and the reference numeral 13 is used.

As shown, a conventional three-dimensional nonvolatile memory device includes a channel 14 protruding vertically from the substrate 10 and a plurality of memory cells stacked along the channel. The manufacturing process will be briefly described as follows.

First, a plurality of interlayer insulating films 11 and conductive films 12 for gate electrodes are alternately stacked on the substrate 10, and then etched to form channel trenches. Subsequently, the charge blocking film, the charge trap film and the tunnel insulating film 13 are formed on the entire surface of the resultant in which the channel trench is formed, and then the back of the substrate on the bottom surface of the channel trench is etched by etching back the charge blocking film, the charge trap film and the tunnel insulating film 13. Expose (10). Subsequently, the channel 14 is formed by embedding the channel film in the channel trench in which the charge blocking film, the charge trap film, and the tunnel insulating film 13 are formed.

However, according to the prior art as described above, since the manufacturing process proceeds in the reverse order to the method for manufacturing a flat panel nonvolatile memory device, the film quality of the tunnel insulating film may be reduced. In particular, in the process of etching back the charge blocking film, the charge trap film, and the tunnel insulating film 13 to expose the substrate 10 on the bottom surface of the channel trench, the previously formed tunnel insulating film is damaged, thereby degrading data retention characteristics and reliability. Triggered.

In addition, since the channel trench has a shape having a large aspect ratio with a deep depth D1 compared to the opening width, voids may occur in the process of embedding the channel film. In particular, the threshold voltage of the memory cell is controlled by doping ions when the channel film is buried. Since the depth D1 of the channel trench is deep, it is not easy to adjust the ion doping concentration of the channel 14. Thus, the threshold voltages of the plurality of memory cells become nonuniform.

In addition, since the plurality of gate electrode conductive films 12 are stacked, an etching process, that is, a slimming process, is required to expose the conductive film 12 for each gate electrode when forming the gate contact. The process is very complicated.

In addition, since the charge blocking film, the charge trap film, the tunnel insulating film 13, and the channel 14 are formed after forming the plurality of gate electrode conductive films 12 first, in order to prevent contamination by metal in subsequent steps. The material of the conductive film 12 for the gate electrode is limited to the polysilicon film. That is, it is impossible to form a metal electrode.

The present invention has been proposed to solve the above problems, and by stacking memory cells on sidewalls of a gate structure in which a plurality of gate electrode films are stacked, a three-dimensional nonvolatile memory having strings arranged three-dimensionally along a plurality of gate structures. It is a first object to provide an element and a method of manufacturing the same.

In addition, the present invention provides a non-volatile memory device having a three-dimensional structure in which a gate line is three-dimensionally arranged along a plurality of gate structures by stacking memory cells on sidewalls of a channel structure in which a plurality of channel films are stacked. Let it be a 1st objective.

In addition, the present invention is a non-volatile memory device having a three-dimensional structure that can easily form a contact pad at one end of the structure by etching the string predetermined region of the substrate, and then forming a gate structure or a channel structure in the etched region And a manufacturing method thereof.

In order to achieve the above object, the present invention provides a method of manufacturing a nonvolatile memory device having a three-dimensional structure, comprising: alternately stacking a plurality of interlayer insulating films and conductive films for a gate electrode; Etching the plurality of interlayer insulating films and the conductive films for the gate electrodes to form a plurality of gate structures extending in parallel in a first direction; Sequentially forming a charge blocking film, a charge trapping film, and a tunnel insulating film along the entire surface of the resultant product in which the gate structure is formed; Forming a channel film along the entire surface of the resultant product in which the charge blocking film, the charge trapping film, and the tunnel insulating film are formed; And etching the channel film, the tunnel insulating film, the charge trapping film, and the charge blocking film to form a plurality of channel lines extending in parallel in a second direction crossing the first direction along a profile of the plurality of gate structures. It is characterized by including a step.

In addition, the present invention provides a method of manufacturing a nonvolatile memory device having a three-dimensional structure, comprising: alternately stacking a plurality of interlayer insulating films and channel films; Etching the plurality of interlayer insulating films and the channel films to form a plurality of channel structures extending in parallel in a first direction; Sequentially forming a tunnel insulating film, a charge trapping film, and a charge blocking film along the entire surface of the resultant product in which the channel structure is formed; Forming a conductive film for a gate electrode along an entire surface of the resultant product in which the tunnel insulating film, the charge trapping film, and the charge blocking film are formed; And etching the gate electrode conductive film, the tunnel insulating film, the charge trapping film, and the charge blocking film to form a plurality of gate lines extending in parallel in a second direction crossing the first direction along a profile of the plurality of channel structures. It is another feature that comprises the step of forming.

In addition, the present invention provides a non-volatile memory device having a three-dimensional structure, comprising: a plurality of gate structures comprising a plurality of interlayer insulating films and gate electrode films alternately stacked and extending in parallel in a first direction; A plurality of memory cells stacked along sidewalls of the gate structure and arranged in a first direction and a second direction crossing the first direction; And a plurality of channel lines extending in parallel in a second direction along profiles of the plurality of gate structures while connecting the plurality of memory cells arranged in the second direction.

In addition, the present invention provides a non-volatile memory device having a three-dimensional structure, comprising: a plurality of channel structures formed of a plurality of interlayer insulating films and channel films stacked alternately and extending in parallel in a first direction; A plurality of memory cells stacked along sidewalls of the channel structure and arranged in a first direction and a second direction crossing the first direction; And a plurality of gate lines extending in parallel in the second direction along profiles of the plurality of channel structures while connecting the plurality of memory cells arranged in the second direction.

According to the present invention, the degree of integration of the memory device may be further improved by three-dimensionally arranging strings along a plurality of gate structures or three-dimensionally arranging gate lines along a plurality of channel structures.

In addition, no void is formed when the channel film is formed, and the ion doping concentration is easily controlled, thereby improving the threshold voltage uniformity of the memory cell.

In addition, since the gate structure or the channel structure is formed in the etched region after the string predetermined region of the substrate is etched, a contact pad may be easily formed at one end of the structure to reduce the difficulty of the memory cell manufacturing process.

In addition, when the memory cell is formed using the channel structure, since the memory cells are formed in the same manufacturing order as in the conventional flat plate type memory device, the film quality of the tunnel insulating layer may be improved, thereby improving data retention characteristics and reliability. In addition, formation of a metal electrode becomes possible.

In the following, the most preferred embodiment of the present invention is described. In the drawings, thicknesses and intervals are expressed for convenience of description and may be shown to be processed compared to actual physical thicknesses. In describing the present invention, well-known structures irrelevant to the gist of the present invention may be omitted. In adding reference numerals to the components of each drawing, it should be noted that the same components as much as possible, even if displayed on different drawings.

Hereinafter, a method of forming a memory cell of a nonvolatile memory device will be described.

2A to 2D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention, and specifically, a method of forming a memory cell using a gate structure.

As shown in FIG. 2A, a plurality of interlayer insulating films 21 and conductive films 22 for gate electrodes are alternately stacked.

Here, the interlayer insulating film 21 is provided as a separation film for separating the conductive films 22 for gate electrodes to be stacked. The gate electrode conductive film 22 is for forming a gate electrode of a memory cell, and the gate electrode conductive films 22 are stacked as many as the number of memory cells to be stacked. In the drawing, as an example, a case of stacking four memory cells is illustrated.

Of course, it is also possible to divide and stack memory cells in multiple times. For example, if 20 memory cells are to be stacked, 20 memory cells may be stacked by stacking four memory cells at a time, but repeating this process five times in total.

As shown in FIG. 2B, the plurality of interlayer insulating layers 21 and the conductive layers 22 for the gate electrodes are etched to form a plurality of gate structures A extending in parallel in the first direction I-I '. do. In the drawing, as an example, a case of forming four gate structures is illustrated.

As a result, a gate structure A including a plurality of interlayer insulating films and gate electrode films is formed. In this drawing, the interlayer insulating film constituting the gate structure A is shown by reference numeral 21A, and the gate electrode film is shown in the drawings. It is shown by the symbol "22A".

Here, the plurality of gate structures A are formed at predetermined intervals, and the gate structure A is preferably patterned in consideration of the thicknesses in which the charge blocking film, the charge trapping film, the tunnel insulating film, and the channel film are to be formed.

Next, it is preferable to form the insulating film 23 so as to alternately fill the gap regions between the gate structures A. FIG. Here, the insulating film 23 is preferably made of an oxide film, and a specific method of alternately filling the insulating film 23 will be described in detail with reference to FIGS. 5A to 6C.

As shown in FIG. 2C, a charge blocking film, a charge trapping film, and a tunnel insulating film are sequentially formed along the entire surface of the resultant product in which the gate structure A is formed. In the figure, for convenience of description, the charge blocking film, the charge trapping film, and the tunnel insulating film are shown as one film, and are denoted by reference numeral 24.

Here, the charge blocking film is to prevent the charge stored in the charge trapping film from moving in the direction of the gate electrode, and is preferably made of a material film or an oxide film having a high-k constant. In addition, the charge trapping film may be formed of a charge trapping film for trapping charges or a charge storing film for storing charges. In the case of the charge trapping film, it is preferable that the charge trapping film is made of a nitride film, and in the case of the charge storage film, it is preferably made of a polycrystalline silicon film. . Further, the tunnel insulating film is provided as an energy barrier film due to tunneling of the charge, and is preferably made of an oxide film.

Subsequently, a channel film 25 is formed along the entire surface of the resultant product in which the charge blocking film, the charge trapping film, and the tunnel insulating film 24 are formed.

As shown in FIG. 2D, the channel layer 25, the charge blocking layer, the charge trapping layer, and the tunnel insulating layer 24 are etched to extend in parallel in the second direction along the profiles of the plurality of gate structures A. FIG. A plurality of channel lines 25A are formed. Here, the charge blocking film, the charge trapping film, and the tunnel insulating film 24 patterned together when the channel line 25A is formed are shown by reference numeral 24A. In this figure, as an embodiment, the case in which two channel lines 25A are formed is illustrated.

Thus, a plurality of layers stacked along the sidewalls of the gate structure A and arranged in a first direction I-I 'and in a second direction II-II' intersecting the first direction I-I '. Memory cells are formed. That is, while the memory cells are stacked along the sidewall of the gate structure A, the memory cells stacked like pillars are arranged in the first direction and the second direction.

In particular, when the insulating layers 23 are alternately filled in the gap regions between the gate structures A, the memory cells may be stacked along one sidewall of the gate structure A in which the insulating layers 23 are not buried.

FIG. 2E is a diagram for explaining the structure of a non-volatile memory device having a three-dimensional structure formed by the first embodiment of the present invention.

As shown, the non-volatile memory device having a three-dimensional structure according to the first embodiment of the present invention includes a plurality of gate structures A and gate structures A extending in parallel in a first direction I-I '. And a plurality of channel lines 25A connecting the plurality of memory cells MC stacked along the sidewalls of the plurality of memory cells MC and the plurality of memory cells MC arranged in the second direction.

Here, the plurality of channel lines 25A extend parallel to the second direction along the profile while crossing the gate structure A. As shown in FIG. That is, the channel lines 25A are three-dimensionally arranged along the sidewalls of the plurality of gate structures A while up and down the sidewalls of the plurality of gate structures A. FIG.

According to this structure, the plurality of memory cells MC arranged in the second direction, that is, the plurality of memory cells MC sharing the same channel line 25A, may be disposed between the source select transistor and the drain select transistor. It is connected to form a string ST. That is, strings are three-dimensionally arranged along the channel structure A, thereby increasing the number of memory cells belonging to one string ST.

In addition, the plurality of memory cells MC arranged in the first direction and sharing the gate electrode layer 22A are connected to the same word line and form one page PAGE to perform a read / write operation. . That is, the memory cells MC formed on the same layer of each gate structure A constitute one page PAGE, and a plurality of pages are formed according to the number of gate electrode layers 22A included in the gate structure A. FIG. (PAGE) are stacked.

Of course, even the memory cell MC formed on the same layer, it may be divided into an even page (odd page) and an odd page (odd PAGE) according to the connected bit line, but for convenience of description in the present specification the even page (even PAGE) ) And odd page are not shown separately.

As described above, by forming the memory cells MC using the gate structure A, a plurality of pages PAGE may be stacked and the strings ST may be three-dimensionally arranged.

According to the first embodiment of the present invention as described above, the degree of integration of the memory device can be further improved by stacking the plurality of pages PAGE and arranging the strings ST in three dimensions.

In addition, since the channel film 25 is formed on the entire surface of the resultant product in which the charge blocking film, the charge trapping film, and the tunnel insulating film 24 are formed (see FIG. 2C), the channel film is embedded in the channel trench having a high aspect ratio. In contrast, ion doping may be performed easily, and thus, threshold voltage uniformity of the memory cells MC may be improved. In addition, it is possible to prevent the generation of voids when forming the channel film.

3A to 3D are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention. In particular, FIGS. 3A to 3D illustrate a method of forming a memory cell using a channel structure.

As shown in Fig. 3A, a plurality of interlayer insulating films 31 and channel films 32 are alternately stacked.

Here, the interlayer insulating film 31 is provided as a separation film for separating the channel films 32 to be stacked. In addition, the channel film 32 is used to form channels of memory cells, and the channel films 32 are stacked as many as the number of memory cells to be stacked. In the drawing, as an example, a case of stacking four memory cells is illustrated.

Of course, it is also possible to divide and stack memory cells in multiple times. For example, if 20 memory cells are to be stacked, 20 memory cells may be stacked by stacking four memory cells at a time, but repeating this process five times in total.

As shown in FIG. 3B, the plurality of interlayer insulating layers 31 and the channel layers 32 are etched to form a plurality of channel structures B extending in parallel in the first direction I-I '. In the drawing, as an embodiment, a case of forming four channel structures B is illustrated.

As a result, a channel structure B including a plurality of interlayer insulating films and a channel film is formed. In this figure, the interlayer insulating film constituting the channel structure B is shown by reference numeral 31A, and the channel film is denoted by " 32A ".

Here, the plurality of channel structures B are formed at predetermined intervals. In the subsequent process, the channel structures B are preferably patterned in consideration of the thicknesses of the charge blocking film, the charge trapping film, the tunnel insulating film, and the gate electrode.

Subsequently, the insulating film 33 is preferably formed so as to alternately fill gap regions between the channel structures B. Here, the insulating film 33 is preferably made of an oxide film, and a specific method of alternately filling the insulating film 33 will be described in detail with reference to FIGS. 5A to 6C.

As shown in FIG. 3C, a tunnel insulating film, a charge trapping film, and a charge blocking film are sequentially formed along the entire surface of the resultant product in which the channel structure B is formed. In this figure, the tunnel insulating film, the charge trapping film, and the charge blocking film are shown as one film for convenience of description, and are denoted by reference numeral 34.

Here, the tunnel insulating film is provided as an energy barrier film due to tunneling of the charge, and is preferably made of an oxide film. In addition, the charge trapping film may be formed of a charge trapping film for trapping charges or a charge storing film for storing charges. In the case of the charge trapping film, it is preferable that the charge trapping film is made of a nitride film, and in the case of the charge storage film, it is preferably made of a polycrystalline silicon film. . In addition, the charge blocking film is intended to prevent the charge stored in the charge trapping film from moving in the direction of the gate electrode, and is preferably made of a material film or an oxide film having a high dielectric constant (high-k).

Subsequently, a conductive film 35 for the gate electrode is formed along the entire surface of the resultant product in which the tunnel insulating film, the charge trapping film, and the charge blocking film 34 are formed. Here, it is preferable that the conductive film 35 for gate electrodes consists of a metal film.

As shown in FIG. 3D, the conductive film 35 for the gate electrode, the tunnel insulating film, the charge trapping film, and the charge blocking film 34 are etched so as to be parallel to the second direction along the profiles of the plurality of channel structures B. FIG. A plurality of gate lines 35A extending are formed. Here, the tunnel insulating film, the charge trapping film, and the charge blocking film 34 patterned together at the time of forming the gate line 35A are shown by reference numeral 34A. In the drawing, as an example, the case where two gate lines 35A are formed is illustrated.

Thus, a plurality of layers stacked along the sidewall of the channel structure B and arranged in a first direction I-I 'and in a second direction II-II' intersecting the first direction I-I '. Memory cells are formed. That is, while the memory cells are stacked along the sidewall of the channel structure B, the memory cells stacked like columns are arranged in the first direction and the second direction.

In particular, when the insulating layers 33 are alternately filled in the gap regions between the channel structures B, the memory cells may be stacked along one sidewall of the channel structure B in which the insulating layers 33 are not buried.

FIG. 3E is a diagram for explaining the structure of a nonvolatile memory device having a three-dimensional structure formed by a second embodiment of the present invention.

As shown, the non-volatile memory device having a three-dimensional structure according to the second embodiment of the present invention includes a plurality of channel structures B and channel structures B extending in parallel in a first direction I-I '. And a plurality of gate lines 35A connecting the plurality of memory cells MC stacked along sidewalls of the plurality of memory cells MC and the plurality of memory cells MC arranged in a second direction.

Here, the plurality of gate lines 35A extend in parallel in the second direction along the profile while crossing the channel structure B. As shown in FIG. That is, the gate lines 35A are three-dimensionally arranged along the sidewalls of the plurality of channel structures B, while the sidewalls of the plurality of channel structures B move up and down.

According to such a structure, the plurality of memory cells MC arranged in the second direction, that is, the plurality of memory cells MC sharing the same gate line 15A, are connected to the same word line to form one page ( PAGE) to perform read / write operations. That is, pages PAGE are arranged three-dimensionally along the channel structure B, thereby increasing the number of memory cells belonging to one page PAGE.

Of course, even in the memory cell MC connected to the same gate line 35A, the page PAGE may be divided according to the connected bit line, and the page PAGE connected to the even bit line even BL may be even page. PAGE), and a page PAGE connected to the odd bit line odd BL may operate as an odd page. However, in the present specification, an even page and an odd page are not illustrated separately for convenience of description.

In addition, the plurality of memory cells MC arranged in the first direction and sharing the channel film 12A are connected between the source select transistor and the drain select transistor to form one string ST. That is, the memory cells MC formed on the same layer of each channel structure B constitute one string ST, and a plurality of strings may be formed according to the number of channel layers 32A included in the channel structure B. ST) is laminated.

As such, by forming the memory cells MC using the channel structure B, the pages PAGE may be three-dimensionally arranged and a plurality of strings ST may be stacked.

According to the second exemplary embodiment of the present invention as described above, by stacking a plurality of strings PAGE and arranging the gate lines 35A in three dimensions, the degree of integration of the memory device may be further improved.

In addition, since the channel film 32A, the tunnel insulating film, the charge trapping film, and the charge blocking film 34 are formed first, then the conductive film 35 for the gate electrode is formed. Is formed. Therefore, it becomes possible to form the gate electrode conductive film 35 which consists of a metal film.

In addition, since the channel film 32 is alternately stacked with the interlayer insulating film 31 (see FIG. 3A), ion doping can be performed more easily than in the prior art in which the channel film is embedded in the channel trench having a high aspect ratio. As a result, the threshold voltage uniformity of the memory cells MC may be improved. In addition, it is possible to prevent the generation of voids when forming the channel film.

4A to 4C are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a third embodiment of the present invention. In particular, a method of forming a contact pad at one end of the structure will be described. Do it. Here, the structure may be the gate structure described in the first embodiment or the channel structure described in the second embodiment. In the present embodiment, for convenience of description, the gate structure is described as an example, but the same applies to the formation of the channel structure.

As shown in FIG. 4A, the string predetermined region (see reference numeral “1”) of the substrate 40 is etched to a predetermined depth. Here, the string planning region refers to a region where a plurality of strings are to be formed by a subsequent process, and it is preferable to perform an etching process in consideration of the width, length and height of the gate structure formed by the subsequent process.

As shown in FIG. 4B, after a plurality of interlayer insulating films 41 and conductive films 42 for gate electrodes are alternately stacked along the entire surface of the resultant portion where the string predetermined region is etched, the surface of the substrate 40 is exposed. The planarization process is performed until

Here, the left figure shows the structure of the intermediate product in which the plurality of interlayer insulating films 41 and the conductive film 42 for the gate electrode are embedded in the string predetermined region of the substrate 40, and the right figure shows the embedded structure in the string predetermined region. Only the plurality of interlayer insulating films 41 and the conductive films 42 for gate electrodes are shown enlarged.

As shown in the drawing on the right, the position where the stack of the interlayer insulating film 41 and the conductive film 42 for the gate electrode and the etch side of the substrate 40 abut (see reference numeral “2”) is examined. It can be seen that the interlayer insulating film 41 and the conductive film 42 for the gate electrode are vertically stacked along the etching side of the substrate. Therefore, the plurality of interlayer insulating films 41 and the gate electrode conductive films 42 stacked along the etch side of the substrate 40 are planarized to form the plurality of gate electrode conductive films 42 at the ends of the stack. Exposed.

As shown in FIG. 4C, a plurality of gate structures which extend in parallel in a first direction by etching the plurality of interlayer insulating layers 41 and the gate electrode conductive layers 42 embedded in the string predetermined regions of the substrate 40. (A) is formed. Subsequently, a charge blocking film, a charge trapping film, a tunnel insulating film 43A, and a channel line 44A are formed.

However, since the process of forming the gate structure A and the like is the same as described above in the first embodiment, a detailed process will be omitted. In addition, in this drawing, only the gate structure A and the channel line 44A formed in the string region of the substrate 40 are enlarged for convenience of description.

As described above, the plurality of gate electrode layers 42A constituting the gate structure A are exposed at one end of the gate structure by the planarization process. That is, through the planarization process, the gate structure A includes a plurality of contact pads (see reference numeral “③”) that expose the plurality of gate electrode films 42A, respectively, at one end thereof.

Next, although not shown in the drawing, after forming contact plugs respectively connected to the plurality of contact pads, a plurality of word lines connected to each contact plug are formed. First, an insulating film is formed on the entire structure of the resultant product in which the channel line 45A is formed, and then the insulating film is etched to form contact holes for exposing a plurality of contact pads, respectively. Subsequently, a contact plug is formed by filling a conductive layer in the contact hole, and then a plurality of word lines connected to the contact plug are formed.

As in the above-described second embodiment, when the channel structure B is formed in the string predetermined region of the substrate, after forming contact plugs connected to the plurality of contact pads, a plurality of bits connected to the contact plugs, respectively. Form a line. First, an insulating film is formed on the entire structure of the resultant product in which the gate lines 45A are formed, and then the insulating film is etched to form contact holes for exposing a plurality of contact pads, respectively. Subsequently, a contact plug is formed by filling a conductive layer in the contact hole, and then a plurality of bit lines connected to the contact plug are formed.

According to the third embodiment of the present invention as described above, a contact pad (reference numeral “③” at one end of the gate structure A) is formed by planarizing the plurality of interlayer insulating films 41 and the gate electrode films 42A. ") Is formed. Thus, there is no need to perform a slimming process that requires a complicated process, thereby simplifying the manufacturing process and reducing the manufacturing cost.

5A to 5C are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a fourth embodiment of the present invention. In particular, FIGS. 5A to 5C illustrate a method of alternately filling an insulating film in a gap region between structures. do. In the present embodiment, for convenience of description, the gate structure is described as an example, but the same applies to the formation of the channel structure.

As shown in FIG. 5A, after a plurality of interlayer insulating films 51 and conductive films 52 for gate electrodes are alternately stacked, a first mask pattern 53 for primary etching is formed on the stack. .

Here, the primary etching is to form a trench to alternately fill the insulating layer in the gap region between the gate structures A, and has a larger primary than the gate structure A to be finally formed by the primary etching. A pattern is formed.

The first mask pattern 53 is formed of a plurality of line patterns extending in parallel in the first direction. In particular, the first mask pattern 53 is formed to cover the adjacent gate structures A and the gap region therebetween, and to expose the gap region where the insulating film is to be filled. For example, the line width W1 of the first mask pattern 53 corresponds to the width of two gate structures A and one gap region, and the space width W2 corresponds to the width of one gap region. It is preferable to apply.

Subsequently, the first mask pattern 53 is used as an etching barrier to form a primary pattern by etching the plurality of interlayer insulating films 51 and the conductive films 52 for gate electrodes.

As shown in FIG. 5B, after forming the insulating film 54 in the gap region between the primary patterns, a second mask pattern 55 for secondary etching is formed on the resultant material in which the insulating film 54 is embedded.

Here, the secondary etching is to form a secondary pattern, that is, the gate structure A, and is formed in a plurality of line patterns extending in parallel in the first direction. In particular, the second mask pattern 55 is formed to cover the insulating film 54 and the two gate structures A in contact with the insulating film. For example, the line width W3 of the second mask pattern corresponds to the width of the insulating film and the two gate structures A contacting the insulating film, and the space width W4 corresponds to the width of one gap region. It is preferable.

As shown in FIG. 5C, the second mask pattern 55 is used as an etch barrier, and the interlayer insulating layer 51 and the conductive layer 52 for the gate electrode are etched to form a secondary pattern, that is, a gate structure A. FIG. do.

As a result, the insulating layer 54 alternately buried in the gap region between the plurality of gate structures A and the plurality of gate structures A is formed.

6A to 6C are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a fifth embodiment of the present invention. In particular, a method of alternately filling an insulating film in a gap region between structures will be described. do. In the present embodiment, for convenience of description, the gate structure is described as an example, but the same applies to the formation of the channel structure.

As shown in FIG. 6A, after a plurality of interlayer insulating films and conductive films for gate electrodes are alternately stacked, a plurality of mask patterns extending in parallel in a first direction while covering a predetermined area of the gate structure on the stack (not shown) Form).

Subsequently, the plurality of gate structures A that extend in parallel in the first direction are formed by etching the plurality of interlayer insulating films and the gate electrode conductive films using the mask pattern as an etching barrier.

As shown in FIG. 6B, an insulating film is formed on the entire structure of the resultant product in which the plurality of gate structures A are formed, and then the planarization process is performed until the surface of the gate structure A is exposed, thereby providing a plurality of gates. An insulating film 63 is buried in the gap region between the structures A. Subsequently, a mask pattern 64 that alternately covers the insulating film 63 is formed on the resultant on which the insulating film is formed. In particular, the mask pattern 64 is formed so as to cover the insulating film and the gate structure A on both sides in contact with the insulating film. That is, the insulating layers 63 buried in the gap regions between the gate structures A are alternately exposed by the mask pattern 64.

As illustrated in FIG. 6C, the insulating layer 63 is etched using the mask pattern 64 as an etch barrier. As a result, an insulating layer 63 that is alternately buried in a gap region between the plurality of gate structures A is formed.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view of a nonvolatile memory device having a three-dimensional structure according to the prior art.

2A to 2D are perspective views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a first embodiment of the present invention.

2E is a perspective view illustrating a structure of a nonvolatile memory device having a three-dimensional structure formed in accordance with a first embodiment of the present invention.

3A to 3D are perspective views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure according to a second embodiment of the present invention.

3E is a perspective view illustrating a structure of a nonvolatile memory device having a three-dimensional structure formed according to the second embodiment of the present invention.

4A to 4C are perspective views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure, according to a third embodiment of the present invention.

5A through 5C are perspective views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure, according to a fourth embodiment of the present invention.

6A through 6C are perspective views illustrating a method of manufacturing a nonvolatile memory device having a three-dimensional structure, according to a fifth embodiment of the present invention.

[Description of Symbols for Main Parts of Drawing]

21: interlayer insulating film 22: conductive film for gate electrode

22A: gate electrode film 23: insulating film

24: charge blocking film, charge trapping film and tunnel insulating film 25: channel film

25A: channel film A: gate structure

Claims (24)

Alternately stacking a plurality of interlayer insulating films and conductive films for gate electrodes; Etching the plurality of interlayer insulating films and the conductive films for the gate electrodes to form a plurality of gate structures extending in parallel in a first direction; Sequentially forming a charge blocking film, a charge trapping film, and a tunnel insulating film along the entire surface of the resultant product in which the gate structure is formed; Forming a channel film along the entire surface of the resultant product in which the charge blocking film, the charge trapping film, and the tunnel insulating film are formed; And Etching the channel layer, the tunnel insulating layer, the charge trapping layer, and the charge blocking layer to form a plurality of channel lines extending in parallel in a second direction crossing the first direction along a profile of the plurality of gate structures; Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 1, In the stacking of the plurality of interlayer insulating films and the conductive films for the gate electrodes, Etching the string predetermined area of the substrate; Alternately stacking the plurality of interlayer insulating films and the conductive films for gate electrodes along the entire surface of the resultant portion of which the string predetermined region is etched; And Performing a planarization process until the surface of the substrate is exposed Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 2, After the channel line forming step, Forming an insulating film on the entire structure of the resultant product in which the channel lines are formed; Etching the insulating layer to form a contact hole for exposing a plurality of contact pads of the plurality of gate structures, respectively; Embedding a conductive film in the contact hole to form a contact plug; And Forming a plurality of word lines connected to the contact plugs Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 3, wherein The contact pad, A plurality of gate electrode conductive layers constituting the gate structure are positioned at ends of the gate structure to be exposed, and are formed in the process of planarizing a plurality of interlayer insulating layers and gate electrode conductive layers stacked along the etching side of the substrate. A method of manufacturing a nonvolatile memory device having a three-dimensional structure. The method of claim 1, Forming an insulating layer to alternately fill gap regions between the plurality of gate structures; Non-volatile memory device manufacturing method of the three-dimensional structure further comprising. The method of claim 5, The gate structure, Memory cells are stacked along one sidewall of the gate structure in which the insulating layer is not buried. A method of manufacturing a nonvolatile memory device having a three-dimensional structure. Alternately stacking a plurality of interlayer insulating films and channel films; Etching the plurality of interlayer insulating films and the channel films to form a plurality of channel structures extending in parallel in a first direction; Sequentially forming a tunnel insulating film, a charge trapping film, and a charge blocking film along the entire surface of the resultant product in which the channel structure is formed; Forming a conductive film for a gate electrode along an entire surface of the resultant product in which the tunnel insulating film, the charge trapping film, and the charge blocking film are formed; And Etching the gate electrode conductive film, the tunnel insulating film, the charge trapping film, and the charge blocking film to form a plurality of gate lines extending in parallel in a second direction crossing the first direction along a profile of the channel structure; Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 7, wherein In the stacking of the plurality of interlayer insulating films and channels, Etching the string predetermined area of the substrate; Stacking a plurality of interlayer insulating films and channel films along the entire surface of the resultant portion of which the string predetermined region is etched; And Performing a planarization process until the surface of the substrate is exposed Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 8, After the gate line forming step, Forming an insulating film on the entire structure of the resultant product in which the gate line is formed; Etching the insulating layer to form a contact hole for exposing a plurality of contact pads of the plurality of channel structures, respectively; Embedding a conductive film in the contact hole to form a contact plug; And Forming a plurality of bit lines connected to the contact plugs Method of manufacturing a non-volatile memory device having a three-dimensional structure comprising a. The method of claim 9, The contact pad, A plurality of channel layers constituting the channel structure are positioned at ends of the channel structure to which the channel structure is exposed. A method of manufacturing a nonvolatile memory device having a three-dimensional structure. The method of claim 7, wherein Forming an insulating layer so as to alternately fill gap regions between the plurality of channel structures. Non-volatile memory device manufacturing method of the three-dimensional structure further comprising. The method of claim 11, wherein The channel structure, Memory cells are stacked along one sidewall of the channel structure in which the insulating layer is not embedded. A method of manufacturing a nonvolatile memory device having a three-dimensional structure. A plurality of gate structures including a plurality of interlayer insulating films and gate electrode films stacked alternately and extending in parallel in a first direction; A plurality of memory cells stacked along sidewalls of the gate structure and arranged in a first direction and a second direction crossing the first direction; And A plurality of channel lines extending in parallel in a second direction along profiles of the plurality of gate structures while connecting the plurality of memory cells arranged in the second direction Non-volatile memory device having a three-dimensional structure comprising a. The method of claim 13, A plurality of memory cells arranged in the second direction to share the channel line, Make up a string Non-volatile memory device having a three-dimensional structure. The method of claim 13, A plurality of memory cells arranged in the first direction and sharing the gate electrode film, One page (PAGE) that performs read / write operations. Non-volatile memory device having a three-dimensional structure. The method of claim 13, The plurality of gate structures, After etching the predetermined region of the string of the substrate to a predetermined depth, formed in the etched region Non-volatile memory device having a three-dimensional structure. The method of claim 16, The gate structure, A plurality of contact pads positioned at one end of the gate structure in contact with an etched side of the substrate and exposing a plurality of gate electrode layers constituting the gate structure, respectively; Non-volatile memory device having a three-dimensional structure. The method of claim 13, The gate structure, The gap region between adjacent gate structures is filled with an insulating film, and memory cells are stacked only on one sidewall of the gate structure in which the insulating film is not buried. Non-volatile memory device having a three-dimensional structure. A plurality of channel structures formed of a plurality of interlayer insulating films and channel films stacked alternately and extending in parallel in a first direction; A plurality of memory cells stacked along sidewalls of the channel structure and arranged in a first direction and a second direction crossing the first direction; And A plurality of gate lines extending in parallel in the second direction along profiles of the plurality of channel structures while connecting the plurality of memory cells arranged in the second direction Non-volatile memory device having a three-dimensional structure comprising a. The method of claim 19, A plurality of memory cells arranged in the first direction to share the channel film, Make up a string Non-volatile memory device having a three-dimensional structure. The method of claim 19, The plurality of memory cells sharing the gate line, One page (PAGE) that performs read / write operations. Non-volatile memory device having a three-dimensional structure. The method of claim 18, The plurality of channel structures, After etching the predetermined region of the string of the substrate to a predetermined depth, formed in the etched region Non-volatile memory device having a three-dimensional structure. The method of claim 22, The channel structure, A plurality of contact pads positioned at one end of the channel structure in contact with an etched side of the substrate and exposing a plurality of channel films constituting the channel structure, respectively; Non-volatile memory device having a three-dimensional structure. The method of claim 19, The channel structure, The gap region between adjacent channel structures is filled with an insulating film, and memory cells are stacked only on one sidewall of the channel structure in which the insulating film is not buried. Non-volatile memory device having a three-dimensional structure.

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