KR20100133037A - Apparatus and method for performing add-compare-select processing in turbo decoder - Google Patents

Abstract

PURPOSE: An add calculation comparison process executing device and a method thereof are provided to improve a decoding speed by improving the data path delay of an add comparison selecting part which determines the operation speed of a turbo decoder. CONSTITUTION: A first addition comparative selection part(300) outputs a first stage path metric by receiving a path metric in the previous step of a first step and the branch metric of the first step. A second addition comparative selection part(350) outputs a second stage path metric by receiving the metric that is outputted from the addition result from the branch metric of a second step and the first addition comparative selection part. The second addition comparative selection part comprises four addition units(351-354), two first selection unit(355,356), a comparison unit(357), and a second selection unit(358).

Description

Apparatus and Method for performing add-compare-select processing in turbo decoder

The present invention relates to a turbo decoder, and more particularly, to an apparatus and method for performing an addition comparison selection process in a turbo decoder for improving high-speed data processing in a wireless communication system.

With the development of wireless communication system, the demand for high speed data communication is increasing, and the demand for technology development to support this is urgently required. Meanwhile, in a wireless communication system receiver, a channel decoder plays an important role in determining a data rate. Therefore, there is an urgent need to develop a turbo decoder device and method for processing a large amount of data at a high speed to be suitable for high-speed data transmission in a wireless communication system.

However, the conventional turbo decoder has a limitation in increasing the operation speed in order to increase the data processing speed. In particular, a parallel turbo decoder for improving data processing power can simultaneously drive several turbo decoders to improve data processing power, but it causes an increase in complexity and cost due to an area increase, and data addressing for parallel processing ( Data complexity also increases.

Apparatus and method for performing addition comparison selection process in turbo decoder according to the present invention are to implement a turbo decoder that can process high-speed data without increasing the area and cost.

In the turbo decoder of the present invention for solving the above problems, the addition comparison selecting unit includes a first addition comparison selecting unit which receives the branch metric of the first step and the path metric of the previous step and outputs the path metric of the first step; And a second add comparison selector configured to receive the branch metric of the second step and the metric outputted as a result of the addition of the first add comparison selector, and output the path metric of the second step. The apparatus may further include a third addition comparison selector configured to receive the branch metric of the third step and the result of the first selection unit and output the path metric of the third step.

In addition, the method of performing the addition comparison selection process in the turbo decoder of the present invention for solving the above problems is the step of performing the addition process of the first step by receiving the branch metric of the first step and the path metric of the previous step, At the same time as performing the comparison process of the steps, receiving the branch metric of the second step, performing the second step of the addition process using the result of the first step, and performing the selection process of the first step. Performing a first selection process of the second step by using the result of the addition process of the second step and the comparison process result of the first step, while outputting the path metric of the first step Performing a comparison process of the second step using the result of the first selection process, and the ratio of the first selection process result of the second step to the second step; Process using the result performing a second selection process of the second stage and is characterized in that it comprises a step of outputting a path metric of the second step.

According to the addition comparison selection apparatus in the turbo decoder of the present invention, the decoding speed is weak compared to the conventional turbo decoder by improving the data path delay of the Add-Compare-Select unit which determines the operation speed of the turbo decoder. You can implement a turbo decoder that can increase nearly double. This increase in decoding speed enables a turbo decoder of a receiver of a wireless communication system to process data at high speed, and can be applied to a turbo decoder of an existing parallel structure type, thereby improving data processing performance and transmission rate. In addition, when applied to a receiver of a wireless communication system requiring a high data rate such as 3G or 4G, it is possible to implement an efficient receiver without increasing the cost.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this case, it should be noted that like elements are denoted by like reference numerals as much as possible. In addition, detailed descriptions of well-known functions and configurations that may blur the gist of the present invention will be omitted.

Also, the terms and words used in the present specification and claims should not be construed to be limited to ordinary or dictionary meanings, and the inventor is not limited to the concept of terms in order to describe his invention in the best way. It should be construed in accordance with the meaning and concept consistent with the technical idea of the present invention based on the principle that it can be properly defined.

1A and 1B are block diagrams of a general turbo decoder device of a reception device of a wireless communication system.

First, referring to FIG. 1A, the turbo decoder device 100 may include a first seesaw decoder 110, a first interleaver 120, a second interleaver 130, a second seesaw decoder 140, and a deinterleaver 150. ). In particular, the turbo decoder device 100 performs an iterative decoding operation to cause a data rate drop. In order to solve this problem, a parallel turbo decoder 150 shown in FIG. 1B has been conventionally proposed.

Referring to FIG. 1B, the parallel turbo decoder 150 includes a first interleaver 120, a second interleaver 130, and a deinterleaver 150. The turbo decoder 100 shown in FIG. Although the same, the first seesaw decoder 110 and the second seesaw decoder 140 respectively include the first sub-seesaw decoders 111 and 112 and the second sub-seesaw decoders 141 and 142, respectively. The parallel turbo decoder 150 may drive a plurality of sub-seesaw decoders simultaneously to substantially improve data processing capability. However, as described above, the need to integrate several sub-seeder decoders together causes problems such as area increase, complexity, and cost, and also increases the complexity of data addressing for parallel processing. do.

2A and 2B are diagrams showing the configuration of a general seesaw decoder included in the decoder device.

First, referring to FIG. 2A, the seesaw decoder 200 includes a branch metric generator BMU 201, an add comparison selector 202, and a log-likelihood-ratio (LLR) calculator 203. The branch metric generator 201 is a unit that calculates a distance along a path that can be transitioned by a received signal and a given trellis diagram. The addition comparison selecting unit 202 generates a new path metric by adding the previous path metric and the branch metric of the currently received signal, and compares a path overlapping the trellis node to select a path having a smaller path metric. to be. The LLR calculator 203 is a unit that generates the LLR that is the final determination output value using the path selected by the addition comparison selection unit 202. FIG. 2B also shows the general configuration of the addition comparison selection unit 202 among the components of the seesaw decoder 200. The general addition comparison selecting unit 202 includes addition units 251 and 252, a comparison unit 253, and a selection unit 254.

FIG. 2B shows a block diagram of the addition comparison selector 202 among the components of the seesaw decoder 200 shown in FIG. 2A. Particularly, d _A of FIG. 2B is a portion for performing an addition process, and d _CS represents a portion for performing a comparison process and a selection process. A _{n, s`} and a _{n, s``} of the input signals represent the path metrics of the previous step, and g _{00, n + 1} and g _{11, n + 1} represent the input branch metrics. Also, a _{n + 1, s ′} indicates a path metric output from the addition comparison selecting unit 202.

As shown in FIG. 2B, a delay occurs during decoding by the addition comparison selector 202 having the longest data path in the structure of the seesaw decoder 200. In order to reduce the delay, a pipeline technique may be applied to increase the driving speed of the turbo decoder among the widely used methods. However, in the addition comparison selector 202, the same operation must be performed simultaneously. Therefore, there is a limit to increasing the data processing speed by applying the pipeline technique.

3A and 3B are block diagrams of an addition comparison selection unit according to an exemplary embodiment of the present invention.

First, referring to FIG. 3A, the addition comparison selecting unit according to the embodiment of the present invention may calculate the first addition comparison selection unit 300 and the second step path metric for calculating the path metric of the first step. It includes a second addition comparison selector 350 for.

The first addition comparison selector 300 has the same configuration as the addition comparison selection unit of FIG. 2B, and the branch metrics g _{00, n + 1} and g _{11, n + 1 of the first} stage and the path metric a of the previous stage. _{n, s '} and a _{n, s''} ) are input to calculate the path metric a _{n + 1, s'} of the first step.

In addition, the second addition comparison selector 350 adds branch metrics g _{00, n + 2} and g _{11, n + 2} of the second step as logic added to continuously calculate the path metric of the next step. Calculate the path metric (a _{n + 2, s '} ) of the second step by using the result of the first step addition process (ta _{n + 1, s'} and ta _{n + 1, s ''} ) and the comparison process result. do. More specifically, the second addition comparison selector 350 may differ from the general addition comparison selection unit described above by using four addition units 351 to 354, two first selection units 355 and 356, and a comparison unit 357. And a second selection unit 358. In the first addition comparison selection unit 300, ta _{n + 1, s'} and ta _{n + 1, s " ,} which are outputs of the addition units 301 and 302, are added units in the second addition comparison selection unit 350. (351 to 354). In addition, the output of the selection unit 303 in the first addition comparison selection unit 300 is input to the first selection units 355 and 356 in the second addition comparison selection unit 350.

In addition, the outputs of the first selection units 355 and 356 are input to the comparison unit 357 and the second selection unit 358 in the second addition comparison selection unit 350. This process is performed in the same manner as the comparison and selection process of the first addition comparison selection unit 300. Therefore, the addition comparison selection unit according to the embodiment of the present invention compares and selects the first addition comparison selection unit 300 (d _CS ) and the addition process (d _A ) of the second addition comparison selection unit 350 simultaneously. Will be.

In addition, if the number of steps to be processed in parallel as shown in FIG. 3B is added, a third addition comparison selection unit 380 having the same configuration as that of the second addition comparison selection unit 350 may be further added. The third addition comparison selector 380 of FIG. 3B is configured to calculate the route metric a _{n + 3, s'} of the third stage, and the branch metrics g _{00, n + 3} and g of the third stage. _{11, n + 3} ) and the path metric (a _n) of the third step using the result of the second step addition process (ta _{n + 2, s'} and ta _{n + 2, s''} ) and the comparison process result. _{+ 3, s'} ).

4 is a flowchart illustrating a calculation process of an add comparison selector according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the branch metric of the first step and the path metric of the previous step are input in step 401, and the addition process of the first step is performed in step 402. Meanwhile, in step 403, the result of the addition process of the first step and the branch metric of the second step are input, and the path metric calculation of the second step is started.

In step 404, the comparison process of the first step is performed, and at the same time, the addition process of the second step is performed in step 405. In operation 406, the first selection process of the second step is performed by using the addition process result of the second step and the comparison process result of the first step.

In step 407, the selection process of the first step is performed, and in step 408, the path metric of the first step is output. In operation 409, a comparison process of the second step is performed using the result of the first selection process of the second step performed in step 406.

Finally, in step 410, the second selection process of the second step is performed using the result of the first selection process of the second step and the comparison process result of the second step, and the path metric of the second step is output in step 411.

5 is a diagram comparing a delay time of an add comparison selector according to an embodiment of the present invention with a delay time of a conventional add comparison selector. In particular, the addition comparison selection unit of the present invention illustrated in FIG. 5 is characterized in that the addition comparison selection step of five steps is performed stepwise in a configuration including the first to fifth addition comparison selection units.

Referring to reference numeral 501 of FIG. 5, when the conventional add comparison selector performs the five-step addition comparison selection process, the delay time is about 50 ns since the five steps are performed serially. Meanwhile, referring to the reference numeral 502, the addition comparison selecting unit according to the embodiment of the present invention takes about 25 ns since the addition process of the next step is performed when the addition process of the first step is completed.

On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to easily explain the technical contents of the present invention and help the understanding of the present invention, and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention can be carried out in addition to the embodiments disclosed herein.

1A and 1B are block diagrams of a general turbo decoder device of a receiving device of a wireless communication system.

2A and 2B show the configuration of a typical seesaw decoder included in the decoder device.

3A and 3B are block diagrams of an addition comparison selection unit according to an embodiment of the present invention.

4 is a flowchart illustrating a calculation process of an add comparison selector according to an exemplary embodiment of the present invention.

5 is a diagram comparing a delay time of an add comparison selector with a delay time of a conventional add comparison selector according to an exemplary embodiment of the present invention.

Claims (4)

A first addition comparison selector which receives the branch metric of the first step and the path metric of the previous step of the first step and outputs the path metric of the first step; and A second comparison comparison selector configured to receive a branch metric of a second stage and a metric outputted as a result of the addition of the first addition comparison selector and to output a path metric of the second stage; Optional device. The method of claim 1, wherein the second addition comparison selection unit An addition unit for performing an addition process using the metric outputted as a result of the addition of the first addition comparison selector and the branch metric of the second step; A first selection unit which receives a result of the addition unit and performs a selection process using the comparison output of the first addition comparison selection unit; A comparison unit which performs a comparison process using the selection result of the first selection unit; and And a second selection unit which receives a result of the first selection unit and performs a selection process by using the result of the comparison unit. The method of claim 2, And a third addition comparison selector configured to receive a branch metric of a third step and a result of the first selection unit and output a path metric of a third step. Performing a first step of adding the branch metric of the first step and the path metric of the previous step of the first step; At the same time as performing the comparison process of the first step, receiving the branch metric of the second step and performing the addition process of the second step by using the result of the addition process of the first step; By performing the selection process of the first stage and outputting the path metric of the first stage, the first selection process of the second stage is performed using the result of the addition process of the second stage and the comparison process result of the first stage. Performing; Performing a comparison process of the second step by using the result of the first selection process of the second step; And And performing a second selection process of the second stage by using the result of the first selection process of the second stage and the comparison process result of the second stage, and outputting a path metric of the second stage. A method of performing an addition comparison selection process in a turbo decoder.

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