KR20100131714A

KR20100131714A - Temperature compensation oscillator of semiconductor device

Info

Publication number: KR20100131714A
Application number: KR1020090050443A
Authority: KR
Inventors: 조현철
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-06-08
Filing date: 2009-06-08
Publication date: 2010-12-16

Abstract

PURPOSE: A temperature compensation oscillator is provided to generate an internal clock which is outputted in a clock generator as a plurality of delay clocks by using a delay circuit. CONSTITUTION: A clock generator(110) generates an internal clock which has a period of a clock which is changed according to internal temperature. A delay clock generator(120) generates a plurality of delay clocks which have different periods by using the internal clock. A clock output part(140) generates a control signal by detecting internal temperature. The clock output part outputs a one among the plurality of delay clocks to an output clock in response to the control signal.

Description

Temperature compensation oscillator circuit of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a temperature compensated oscillation circuit of a semiconductor device, and more particularly, to a temperature compensated oscillation circuit of a semiconductor device for generating a clock having a constant period by suppressing a change in clock period caused by temperature change.

In general, there are circuits that need to use an internal clock as well as an external clock in memory devices and IC chips. In flash memory, an internal clock is used without input of an external clock to a microcontroller or a pump circuit. An oscillating circuit generates this clock.

The oscillation circuit is a ring oscillator that connects an odd number of inverters in series so that the output of the final stage is fed back to the input of the first inverter. However, the ring oscillator has a disadvantage in that the period is greatly changed by being influenced by the process, power supply voltage, and temperature fluctuation (PVT fluctuation). To improve this, circuits are used to connect a constant current source to the inverter, to include resistors, capacitance and Schmitt triggers, or comparators to allow the RC delay effect to determine the period. In addition, a problem arises in that the clock cycle of the oscillation circuit changes when the cycle resistance to external changes and the area resistance value due to the process change.

An object of the present invention is to generate an internal clock output from a clock generator as a plurality of delay clocks using a delay circuit, and outputs any one of a plurality of delay clocks using a detection signal output from a temperature detection signal generator. The present invention provides a temperature compensated oscillation circuit of a semiconductor device capable of generating an output clock having a certain period even when the temperature changes.

In an embodiment, a temperature compensation oscillation circuit of a semiconductor device may include a clock generator for generating an internal clock, a delay clock generator for generating a plurality of delay clocks having different periods using the internal clock, and the plurality of clock generators. It includes a clock output unit for outputting any one of the delay clock of the output clock.

The clock output unit outputs any one of the plurality of delayed clocks as an output clock in response to a plurality of temperature detection signals.

The apparatus further includes a temperature detection signal generator for detecting a temperature of the device and outputting the plurality of temperature detection signals.

In the plurality of temperature detection signals, only one temperature detection signal has a high level.

The delay clock generator includes a plurality of delay units, the plurality of delay units are connected in series, and each delay unit outputs one of the plurality of delay clocks. Each of the plurality of delay units has an even number of inverters connected in series.

The clock output unit includes a plurality of switches, each of which outputs one of the plurality of delayed clocks to the output clock in response to one of the corresponding plurality of temperature detection signals.

According to an embodiment of the present invention, the internal clock output from the clock generator is generated as a plurality of delay clocks using a delay circuit, and any one of the plurality of delay clocks is generated using a detection signal output from the temperature detection signal generator. By outputting the output clock, it is possible to generate an output clock having a certain period even if the temperature changes.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

1 is a block diagram of a temperature compensation oscillation circuit 100 of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, the temperature compensation oscillator circuit 100 of the semiconductor device includes a clock generator 110, a delayed clock generator 120, a temperature detection signal generator 130, and a clock output unit 140.

The clock generator 110 generates an internal clock CLK1 having a predetermined period in response to the clock enable signal CLK_EN. In this case, the resistance inside the device may change according to the temperature change, and the period of the internal clock CLK1 may change.

The delay clock generator 120 includes a plurality of delay units, for example, the first delay unit 121 to the nth delay unit 12n.

The first delay unit 121 to the n-th delay unit 12n are connected to each other in series. The first delay unit 121 receives the internal clock CLK1 output from the clock generator 110 and outputs the first delay clock DC1. The second delay unit 122 receives the first delay clock DC1 output from the first delay unit 121 and outputs a second delay clock DC2. The n-th delay unit 12n receives the n-th delay clock DCn-1 output from the n-th delay unit 12n-1 to output the n-th delay clock DCn.

The temperature detection signal generator 130 detects an internal temperature of the device and outputs a plurality of detection signals T1 to Tn according to the detected internal temperature. The temperature detection signal generator 130 compares a plurality of set temperatures and outputs a plurality of detection signals T1 to Tn.

Table 1 is a table showing, for example, the logic levels of the plurality of detection signals T1 to Tn according to the detected temperature.

T1 T2 ... Tn-1 Tn Temp 1 L L ... L H Temp 2 L L ... H L ... ... ... ... ... ... Temp n-1 L H ... L L Temp n H L ... L L

For example, when the detected temperature is Temp 1, Temp 2, Temp n-1, Temp n (Temp 1> Temp 2> Temp n-1> Temp n), a plurality of detection signals T1 to Outputs Tn). That is, only one detection signal of the plurality of detection signals T1 to Tn is output at a logic high level, and the remaining detection signals are output at a logic low level.

The clock output unit 140 includes a plurality of NMOS transistors NM1 to NMn. Each of the plurality of NMOS transistors NM1 to NMn may output any one of the plurality of delay clocks DC1 to DCn output from the delay clock generator 120 in response to the plurality of detection signals T1 to Tn. Output to CLK2).

FIG. 2 is a detailed circuit diagram of the first delay unit 121 of FIG. 1.

Since the detailed circuits are similar to each other in the first delay unit 121 to the nth delay unit 12n, only the detailed circuit of the first delay unit 121 will be described.

2, the first delay unit 121 includes a plurality of inverters IV1 to IV4. In FIG. 2, four inverters IV1 to IV4 are illustrated for ease of description, but an even number of inverters may be configured in series and may be configured by adjusting the number of inverters according to a set time. The first delay unit 121 delays the internal clock CLK1, in which even-numbered inverters IV1 to IV4 are connected in series and outputs the first delay clock DC1 by a predetermined time.

Referring to FIGS. 1 and 2, a temperature compensation oscillation circuit of a semiconductor device according to example embodiments will be described below.

The clock generator 110 generates an internal clock CLK1 having a predetermined period in response to the clock enable signal CLK_EN. The period of the clock of the generated internal clock CLK1 may change according to temperature.

The delay clock generator 120 generates a plurality of delay clocks DC1 to DCn using the internal clock CLK1 generated by the clock generator 110. The periods of the plurality of delay clocks DC1 to DCn are different from each other, and the period of the second delay clock DC2 is longer than that of the first delay clock DC1.

The temperature detection signal generator 130 outputs a plurality of detection signals T1 to Tn according to the detected temperature. At this time, only one detection signal among the plurality of detection signals T1 to Tn has a high level logic value.

The clock output unit 140 outputs any one of the plurality of delayed clocks DC1 to DCn to the output clock CLK2 in response to the plurality of detection signals T1 to Tn.

As described above, the temperature compensation oscillation circuit of the semiconductor device according to an embodiment of the present invention outputs any one of a plurality of delayed clocks generated by using an internal clock as an output clock in response to a detection signal according to a detected temperature. In addition, even when the temperature changes, it is possible to generate an output clock having a certain period.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

FIG. 2 is a detailed circuit diagram of the first delay unit 121 of FIG. 1.

100: oscillation circuit 110: clock generator

120: delay clock generator 130: temperature detection signal generator

140: clock output unit

Claims

A clock generator for generating an internal clock in which a cycle of the clock changes according to an internal temperature;

A delay clock generator for generating a plurality of delay clocks having different periods using the internal clock; And

And a clock output unit which detects the internal temperature to generate a control signal, and outputs any one of the plurality of delayed clocks as an output clock in response to the control signal.

The method of claim 1,

And the clock output unit outputs any one of the plurality of delayed clocks as an output clock in response to the plurality of temperature detection signals generated by detecting the internal temperature.

The method of claim 2,

The clock output unit includes a temperature detection signal generator for detecting the internal temperature and outputs the plurality of temperature detection signals.

The method of claim 3, wherein

And the temperature detection oscillation circuit of the semiconductor device has only one temperature detection signal having a high level.

The method of claim 1,

The delay clock generator includes a plurality of delay units,

And the plurality of delay units are connected in series, and each of the delay units outputs one of the plurality of delay clocks.

The method of claim 2,

The clock output unit includes a plurality of switches,

Each of the plurality of switches outputs one of the plurality of delayed clocks to the output clock in response to one of the corresponding plurality of temperature detection signals.

The method of claim 5,

Each of the plurality of delay units is a temperature compensation oscillation circuit of a semiconductor device in which an even number of inverters are connected in series.

A clock generator for generating an internal clock;

A delay clock generator for generating a plurality of delay clocks having different periods using the internal clock;

A temperature detection signal generator for detecting a temperature of the device to generate a plurality of temperature detection signals; And

And a clock output unit configured to output one of the plurality of delayed clocks as an output clock in response to the plurality of temperature detection signals.

The method of claim 8,

And the temperature detection signal generator outputs only one of the plurality of temperature detection signals to a logic high level according to the detected temperature.

The method of claim 8,

The delay clock generator includes a plurality of delay units,

The method of claim 8,

The clock output unit includes a plurality of switches,

The method of claim 10,