KR20100128861A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device is provided to easily implement an integrated circuit integrated with components having various threshold voltages by controlling the threshold voltage of a transistor by controlling the operating voltage applied to the semiconductor pattern. CONSTITUTION: A first separation oxide(125) is formed on a semiconductor substrate(111). An active pattern(131) is formed on a first separation insulation pattern. A semiconductor pattern(127) is formed between the semiconductor substrate and the first separation insulation pattern. A second separation insulation pattern(124) is formed between the semiconductor substrate and the semiconductor pattern.

Description

Semiconductor device {SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including an SOI substrate having a thin buried oxide (BOX).

With the trend toward higher integration of semiconductor devices, each component in the device is required to be disposed on a substrate at a higher density. As each component is placed at narrow intervals, unwanted interaction between the components may occur. This interaction can reduce the reliability of the device. To prevent this, various methods for separating each component have been attempted.

A method of arranging components on a silicon on insulator (SOI) substrate has been proposed as a means to electrically and / or spatially separate each component. However, when the components of the device are disposed on the SOI substrate, there is a problem that does not occur in the existing bulk substrate.

One object of the present invention is to provide a semiconductor device capable of easily adjusting the threshold voltage.

A semiconductor device for solving the above technical problem is provided.

The semiconductor device includes a semiconductor substrate, a first isolation insulating pattern on the semiconductor substrate, an active pattern on the first isolation insulation pattern, a semiconductor pattern between the semiconductor substrate and the first isolation insulation pattern, the semiconductor substrate and the semiconductor. And a second separation insulating pattern between the patterns, and a connection pattern connecting the semiconductor substrate and the semiconductor pattern.

In an embodiment, the semiconductor device may further include a gate insulating layer and a gate electrode sequentially stacked on the active pattern. In this case, during operation of the semiconductor device, a depletion layer may be formed in the active pattern and the semiconductor pattern.

In an embodiment, the depletion layer may extend into the semiconductor substrate.

In an embodiment, the connection pattern may be in contact with a semiconductor substrate on one side of the semiconductor pattern and one side of the semiconductor pattern.

In example embodiments, the second separation insulating pattern may include the same insulating material as the first separation insulating pattern.

In an embodiment, the semiconductor substrate and the semiconductor pattern may be electrically connected by the connection pattern.

In an embodiment, the gate electrode may extend onto sidewalls of the active pattern. In this case, the first isolation insulating pattern may extend between the gate electrode and sidewalls of the active pattern.

In an embodiment, the channel region in the active pattern may include an undoped semiconductor material, and the semiconductor pattern may include a doped semiconductor material.

In an embodiment, the connection pattern may include a semiconductor material or a conductive material.

In example embodiments, the connection pattern and the semiconductor pattern may include the same material.

According to embodiments of the present invention, an SOI device having a connection pattern electrically connecting a semiconductor substrate and an active pattern and an electrically thin investment insulating film is provided. When a back bias is applied to the semiconductor substrate, this voltage may affect the active pattern through the thin buried insulating layer. That is, the threshold voltage value of the transistor including the active pattern may be easily adjusted by the back bias.

Hereinafter, a semiconductor device and a method of forming the same according to embodiments of the present invention will be described with reference to the accompanying drawings. The described embodiments are provided so that those skilled in the art can easily understand the spirit of the present invention, and the present invention is not limited thereto. Embodiments of the invention may be modified in other forms within the spirit and scope of the invention. In this specification, 'and / or' is used to include at least one of the components listed before and after. In this specification, the fact that one component is 'on' another component means that another component is directly positioned on one component, and that a third component may be further positioned on the one component. It also includes meaning. Each component or part of the present specification is referred to using the first, second, and the like, but the present disclosure is not limited thereto. The thickness and relative thickness of the components represented in the drawings may be exaggerated to clearly express embodiments of the present invention.

10A to 10C, a semiconductor device according to an embodiment of the present invention is described. 10A is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIGS. 10B and 10C are cross-sectional views of semiconductor devices taken along lines II ′ and II-II ′, respectively, shown in FIG. 10A.

A semiconductor substrate 111 is provided. The semiconductor substrate 111 may include a bottom portion 112 and a protrusion 113 protruding from the bottom portion 112. The semiconductor substrate 111 may include a single crystal semiconductor material. The semiconductor substrate 111 may include a well region doped with dopants. At least a portion of the well region may be disposed in the protrusion 113.

Sidewalls and upper surfaces of the protrusions 113 of the semiconductor substrate may be surrounded by the second isolation insulating pattern 124. A portion of the upper surface of the bottom portion 112 adjacent to the protrusion 113 may also be covered by the second isolation insulating pattern 124. At least a portion of the bottom portion 112 of the semiconductor substrate may not be covered by the second isolation insulating pattern 124. When the semiconductor substrate 111 is in the form of a flat plate without a protrusion, the second isolation insulating pattern 124 may be disposed only on a portion of the upper surface of the semiconductor substrate 111.

The second separation insulating pattern 124 may include an insulating material. The second isolation insulating pattern 124 may include at least one selected from insulating layers including an oxide layer, a nitride layer, and an oxynitride layer. For example, the second isolation insulating pattern 124 may be an oxide-nitride-oxide (ONO) layer.

The semiconductor pattern 127 may be disposed on the second isolation insulating pattern 124. The semiconductor pattern 127 may cover an upper surface of the second isolation insulating pattern 124. When the semiconductor substrate 111 includes the protrusion 113, the semiconductor pattern 127 may cover the top surface and sidewalls of the protrusion 113 of the semiconductor substrate. Sidewalls of the semiconductor pattern 127 may be coplanar with sidewalls constituting one end of the second isolation insulating pattern 124. The semiconductor pattern 127 may be spaced apart from the semiconductor substrate 111 by the second isolation insulating pattern 124.

The semiconductor pattern 127 may include a semiconductor material. In an embodiment, the semiconductor pattern 127 may include a polycrystalline semiconductor material. The semiconductor pattern 127 may be doped with dopants or not.

A connection pattern 129 connecting the semiconductor substrate 111 and the semiconductor pattern 127 is disposed. The connection pattern 129 may have a lower surface in contact with the semiconductor substrate 111 and a sidewall in contact with the semiconductor pattern 127.

The connection pattern 129 may include a semiconductor material or a conductive material. For example, the connection pattern 129 may include a doped semiconductor, an undoped semiconductor, a metal, or a metal compound. In some embodiments, the connection pattern 129 may be formed of the same material as the semiconductor pattern 127. Unlike shown, the connection pattern 129 and the semiconductor pattern 127 may not have an interface.

The semiconductor substrate 111 and the semiconductor pattern 127 may be electrically connected by the connection pattern 129. In other words, the semiconductor substrate 111 and the semiconductor pattern 127 may be spaced apart from each other by the second isolation insulating pattern 124, but may be electrically connected to each other via the connection pattern 129.

An active pattern 131 is disposed on the semiconductor pattern 127. A first isolation insulating layer 125 may be interposed between the semiconductor pattern 127 and the active pattern 131. In an embodiment, the active pattern 131 may be disposed in a predetermined area surrounded by the first isolation insulating pattern 125. The active pattern 131 may be separated from other components on the semiconductor substrate 111 by the first isolation insulating pattern 125.

The active pattern 131 may include a semiconductor material. For example, the active pattern 131 may include a semiconductor material in a single crystal state. A source / drain region 135 may be disposed in the active pattern 131. In an embodiment, the bottom surface of the source / drain region 135 may extend to the bottom surface of the active pattern 131. That is, the bottom surface of the source / drain region 135 and the bottom surface of the active pattern 131 may be defined as the same surface.

In example embodiments, the semiconductor device may include an active pattern 131 including a doped semiconductor pattern 127 and an undoped channel region. In this case, the active pattern 131 may be formed to a thinner thickness than when the active pattern 131 is doped.

A gate insulating pattern 153 and a gate electrode 155 may be stacked on the active pattern 131. Spacers 156 may be disposed on sidewalls of the gate electrode 155.

When disposing the components of the device on the SOI substrate, other problems that may not occur in the bulk substrate, for example, difficulty in adjusting the threshold voltage may occur. Therefore, the application of SOI devices to integrated circuits that require devices with various threshold voltages is limited.

However, according to embodiments of the present invention, the threshold voltage of the SOI device can be easily adjusted.

Specifically, according to the embodiments of the present invention, the first isolation insulating film 125 serving as the buried insulating film of the SOI device may be formed to have a very thin thickness. In an embodiment, the first isolation insulating layer 125 may be formed to 10 nm or less. In addition, according to example embodiments, the semiconductor pattern 127 is connected to the semiconductor substrate 111 by the connection pattern 129. Accordingly, an operating voltage may be applied to the semiconductor pattern 127 through the semiconductor substrate 111. The back bias is induced in the active pattern 131 by the operating voltage applied to the semiconductor pattern 127.

In addition, the semiconductor pattern 127 may be disposed under the lower surface of the active pattern 131 to perform a lower gate function for controlling the active pattern 131. In this case, the first isolation insulating layer 125 may function as a gate insulating layer of the lower gate.

That is, the semiconductor substrate 111 and the semiconductor pattern 127 may be electrically connected to each other. In addition, since the first isolation insulating layer 125 is formed to have a very thin thickness, even when the first isolation insulating layer 125 is interposed, a voltage applied to the semiconductor substrate 111 is applied to the active pattern 131. Can affect Therefore, the threshold voltage of the transistor may be controlled by adjusting the operating voltage applied to the semiconductor substrate 111 and / or the semiconductor pattern 127. Accordingly, an integrated circuit in which devices having various threshold voltages are integrated may be more easily implemented.

In the operation of the semiconductor device according to the embodiment of the present invention, a depletion layer may be formed in the active pattern 131. The depletion layer may be formed in the entire area of the active pattern 131. As described above, since the first isolation insulating layer 125 surrounding the lower surface and the sidewall of the active pattern 131 is formed very thin, the depletion layer may extend into the semiconductor pattern 127. In addition, the depletion layer may extend into the semiconductor substrate 111 according to the intensity of the applied voltage.

1A to 1C, 2A to 2C, 3A to 3C, 4A to 4C, 5A to 5C, 6A to 6C, 7A to 7C, 8A to 8C, and 9A. 9C and 10A to 10C, a method of forming a semiconductor device according to an embodiment of the present invention will be described. 1A to 10A are perspective views illustrating a method of forming a semiconductor device in accordance with an embodiment of the present invention. 1B to 10B and 1C to 10C are cross-sectional views taken along lines II ′ and II-II ′ illustrated in FIGS. 1A to 10A, respectively.

In the method of forming a semiconductor device according to an embodiment of the present invention, forming a stacked structure in which a sacrificial layer and an active layer are sequentially stacked on a semiconductor substrate, and removing the sacrificial layer to empty space between the active layer and the semiconductor substrate. Forming a second isolation insulating pattern on the semiconductor substrate in the empty space, filling the empty space, but forming a semiconductor pattern spaced apart from the semiconductor substrate, and forming the semiconductor pattern; It may include forming a connection pattern for connecting the semiconductor substrate.

1A to 1C, the sacrificial layer 120 and the active layer 130 are sequentially stacked on the semiconductor substrate 110. The semiconductor substrate 110 may be a bulk substrate composed of semiconductor elements. The semiconductor substrate 110 may include a well region.

In example embodiments, the sacrificial layer 120 and the active layer 130 may be formed on a portion of the semiconductor substrate 110. For example, the semiconductor substrate 110 may include an SOI region and a bulk region, and the sacrificial layer 120 and the active layer 130 may be formed on the semiconductor substrate 110 of the SOI region. The semiconductor substrate 110 including the SOI region and the bulk region may be prepared, and a mask film may be formed on the semiconductor substrate 110 of the bulk region. In this case, the semiconductor substrate 110 in the SOI region may be exposed. Subsequently, the semiconductor substrate 110 in the SOI region may be anisotropically etched using the mask layer as an etching mask. The sacrificial layer 120 and the active layer 130 may be sequentially stacked on the etched semiconductor substrate 110 in the SOI region. As described above, according to the exemplary embodiment of the present invention, both the SOI region and the bulk region may be formed on one bulk substrate.

Alternatively, after the sacrificial layer 120 and the active layer 130 are formed on the entire surface of the semiconductor substrate 110, the sacrificial layer 120 and the active layer 130 in the bulk region are removed to remove the sacrificial layer ( The semiconductor substrate 110 including the 120 and the active layer 130 may be prepared.

The sacrificial layer 120 may include a material having an etch selectivity with respect to the semiconductor substrate 110 and the active layer 130. For example, the sacrificial layer 120 may include single crystal silicon germanium (Si-Ge). The sacrificial layer 120 may be formed by an epitaxial growth method using the semiconductor substrate 110 as a seed layer.

The active layer 130 may include a semiconductor material. In one embodiment, the active layer 130 may be a layer composed of single crystal silicon. The active layer 130 may be formed by an epitaxial growth method using the sacrificial layer 120 as a seed layer.

2A through 2C, the sacrificial layer 120 and the active layer 130 are patterned to form the sacrificial pattern 121 and the active pattern 131. The patterning is performed by forming a first mask 141 on the sacrificial layer 120 and the active layer 130 and using the first mask 141 as an etching mask. May include anisotropic etching.

In the anisotropic etching, the semiconductor substrate 110 may act as an etch stop layer. In this case, a portion of the semiconductor substrate 110 may be etched. The etched semiconductor substrate 111 may include a bottom portion 112 and a protrusion 113 protruding from the bottom portion 112.

A support insulating layer 142 is formed on the semiconductor substrate 111. The device isolation layer may include an upper surface of the bottom portion 112 of the semiconductor substrate and sidewalls of the protrusion 113, the sacrificial pattern 121, the active pattern 131, and the first mask 141 of the semiconductor substrate 111. Can be covered An upper surface of the support insulating layer 142 may be planarized to expose the upper surface of the first mask 141.

3A to 3C, a second mask 151 is formed on the upper surface of the structure formed in FIGS. 2A to 2C. The second mask 151 may cover only a portion of the upper surface of the support insulating layer 142 and the first mask 141.

The support insulating layer 142 is anisotropically etched using the second mask 151 as an etching mask. By the anisotropic etching process, sidewalls of the stacked structure including the sacrificial pattern 121, the active pattern 131, and the first mask 141 may be exposed. In addition, an upper surface of the bottom portion 112 of the semiconductor substrate and a sidewall of the protrusion 113 may be exposed.

Thereafter, the sacrificial pattern 121 may be removed. As described above, since the sacrificial pattern 121 is formed of a material having an etch selectivity with respect to the active pattern 131 and the etched semiconductor substrate 111, the sacrificial pattern 121 may be selectively removed. have. The support insulating layer 142 may support the stack structure such that the stack structure is not collapsed by removing the sacrificial pattern 121.

An empty space 122 is formed in the space where the sacrificial pattern 121 was. The empty space 122 may be surrounded by an upper surface of the protrusion 113 of the semiconductor substrate, a lower surface of the active pattern 131, and a support insulating layer 142. By forming the empty space 122, an upper surface of the protrusion 113 of the semiconductor substrate and a lower surface of the active pattern 131 may be exposed.

4A through 4C, insulating layers 123 and 125 are formed on surfaces exposed by the semiconductor substrate 111 and the empty space 122 and side surfaces of the stacked structure. The insulating layers 123 and 125 may include an upper surface of the bottom portion 112 of the semiconductor substrate, a second isolation insulating layer 123 formed on the sidewalls and the upper surface of the protrusion 113 of the semiconductor substrate, and the active layer. The first isolation insulating layer 125 may be formed on the bottom surface and the sidewall of the pattern 131. The first isolation insulating layer 125 and the second isolation insulating layer 123 may be formed to have a very thin thickness. In an embodiment, the first isolation insulating layer 125 and the second isolation insulating layer 123 may be formed to be less than 10 nm.

The insulating layers 123 and 125 may be at least one insulating layer selected from various insulating layers including an oxide layer, a nitride layer, and an oxynitride layer. In example embodiments, the insulating layers 123 and 125 may be an oxide-nitride-oxide (ONO) layer. Forming the ONO film may include oxidizing exposed surfaces of the semiconductor substrate 111 and the active pattern 131 to form a first oxide film, depositing a nitride film covering the first oxide film, and on the nitride film. It may include forming a second oxide film.

5A through 5C, a semiconductor film 126 is formed between the active pattern 131 and the semiconductor substrate 111. The semiconductor film 126 may fill the empty space 122. The semiconductor film 126 may extend onto sidewalls of the stacked structure. The semiconductor film 126 may cover the entirety of the protrusion 113 of the semiconductor substrate and a portion of the bottom 112 of the semiconductor substrate. The semiconductor film 126 may be formed by depositing a film and performing a chemical mechanical polishing process or an etch back process. When performing the chemical mechanical polishing process, the second mask 151 may also be removed.

The semiconductor film 126 may include a semiconductor material. For example, the semiconductor film 126 may include a semiconductor material in an amorphous state. The semiconductor film 126 may include a semiconductor material doped with dopants. Alternatively, the semiconductor film 126 may include an undoped semiconductor material. When the semiconductor film 126 is doped with dopants, the dopants may be implanted into the film through an in-situ process during the film formation process, or into the film through an ion implantation process after the film formation. The semiconductor film 126 may be converted into a semiconductor material in a polycrystalline state in a subsequent process.

In example embodiments, the semiconductor layer 126 may be doped, and the channel region in the active pattern 131 may not be doped. In this case, a threshold voltage variation of the semiconductor device formed by using the semiconductor film 126 and the active pattern 131 may be reduced.

In detail, when the channel region of the active pattern 131 is doped with dopants, the dopant concentration profile in the active pattern 131 may not appear in a desired shape. That is, dopant fluctuations in the active pattern 131 may appear. The threshold voltage of the transistor including the active pattern 131 may not represent a desired value. In particular, when the dopants are implanted by an ion implantation process, such a dopant variation may be further intensified.

However, according to one embodiment of the present invention, when the semiconductor film 126 is doped, the doping concentration profile of the semiconductor film 126 may appear close to the desired shape. That is, when dopants are implanted toward the active pattern 131, the dopant concentration profile in the semiconductor layer 126 may be uniform compared to the dopant concentration profile in the active pattern 131. Accordingly, when the semiconductor layer 126 is doped and the semiconductor device is formed using the semiconductor layer 126, the dopant variation may be improved. Accordingly, the threshold voltage deviation of the device can be greatly reduced.

After the formation of the semiconductor layer 126, a portion of the isolation insulating layer 123 may be etched to form a second isolation insulating pattern 124. A portion of the upper surface of the semiconductor substrate 111 is exposed by the etching of the isolation insulating layer 123. When the semiconductor substrate 111 includes the protrusion 113 and the bottom 112, a portion of the bottom 112 may be exposed.

6A through 6C, a connection layer 128 is formed on the exposed semiconductor substrate 111. The connection layer 128 may be formed by performing a deposition and chemical mechanical polishing process or an etch back process. The connection layer 128 may be formed on an upper surface of the bottom portion 112 of the semiconductor substrate. The connection layer 128 may be formed to cover sidewalls of the semiconductor layer 126. The connection layer 128 may be formed of a material capable of electrically connecting the semiconductor substrate 111 and the semiconductor layer 126. For example, the connection layer 128 may include a semiconductor material or a conductive material. The connection layer 128 may include a doped semiconductor material, an undoped semiconductor material, or a metal compound.

In one embodiment, the semiconductor film 126 and the connection film 128 may be formed at the same time. For example, the semiconductor film 126 and the connection may be formed by forming a semiconductor material film on sidewalls of the void 122, the active pattern 131, and the protrusion 113 of the semiconductor substrate, and omitting an etching process. The film 128 may be formed at the same time. In this case, an etching process may be performed on the second isolation insulating layer 123 before the semiconductor layer 126 and the connection layer 128 are formed. Specifically, at least a portion of the second isolation insulating layer 123 on the bottom portion 112 of the semiconductor substrate may be removed. A portion of the bottom 112 of the semiconductor substrate may be exposed by the etching process of the second isolation insulating layer 123.

7A to 7C, upper portions of the semiconductor layer 126 and the connection layer 128 may be etched. The semiconductor layer 126 and the connection layer 128 may be simultaneously etched. As a result, the semiconductor pattern 127 and the connection pattern 129 may be formed. Unlike illustrated, upper surfaces of the semiconductor pattern 127 and the connection pattern 129 may be lower than a lower surface of the first isolation insulating pattern 125. In addition, upper surfaces of the semiconductor pattern 127 and the connection pattern 129 may be higher than an upper surface of the second isolation insulating pattern 124.

An interlayer insulating layer 144 may be formed on the semiconductor pattern 127 and the connection pattern 129. An upper surface of the interlayer insulating layer 144 may be planarized to form a coplanar surface with the supporting insulating layer 142. The interlayer insulating layer 144 may cover sidewalls of the exposed first isolation insulating pattern 125. Sidewalls of the active pattern 131 may be surrounded by the support insulating layer 142 and the interlayer insulating layer 144.

8A to 8C, the first mask 141 is removed. When the first mask 141 is removed, a portion of the first isolation insulating layer 125 and the interlayer insulating layer 144 may be etched together. By removing the first mask 141, an upper surface of the active pattern 131 may be exposed.

9A through 9C, a gate insulating layer 153 may be formed on an upper surface of the active pattern 131. The gate insulating layer 153 may be at least one selected from various insulating layers including an oxide layer, a nitride layer, and an oxynitride layer. In an embodiment, the gate insulating layer 153 may be formed by thermally oxidizing an upper surface of the active pattern 131.

A gate film 154 is formed on the gate insulating film 153. The gate layer 154 may include a doped semiconductor material, a metal, or a metal compound.

10A to 10C, the gate electrode 155 may be formed by anisotropically etching the gate layer 154. The gate electrode 155 may extend in a direction perpendicular to the length direction of the active pattern 131. Spacers 156 may be formed on both sidewalls of the gate electrode 155.

Before and / or after forming the spacer 156, a source / drain region 135 may be formed in the active pattern 131 on both sides of the gate electrode 155. The source / drain region 135 may be formed by implanting dopants into the active pattern 131 by an ion implantation process using the gate electrode 155 and / or the spacer 156 as a mask.

18A to 18C, a semiconductor device according to another embodiment of the present invention is described. 18A is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIGS. 18B and 18C are cross-sectional views of semiconductor devices taken along lines II ′ and II-II ′, respectively, shown in FIG. 10A. 18A to 18C illustrate a semiconductor device having an active pattern in the form of a fin.

The semiconductor substrate 211 is prepared. The semiconductor substrate 211 includes a bottom portion 212 and a protrusion 213 protruding from the bottom portion 212. The second isolation insulating pattern 213 is disposed on the upper surface and the side surface of the protrusion 213 of the semiconductor substrate. A portion of the second isolation insulating pattern 213 may extend to an upper surface of the bottom portion of the semiconductor substrate 211.

The semiconductor pattern 227 is disposed on the protrusion 213 of the semiconductor substrate. The semiconductor pattern 227 may be spaced apart from the semiconductor substrate 211 by the second isolation insulating pattern 224. The semiconductor pattern 227 may include a semiconductor material. For example, the semiconductor pattern 227 may include a semiconductor material in a polycrystalline state.

A connection pattern 229 connecting the semiconductor substrate 211 and the semiconductor pattern 227 is disposed. The connection pattern 229 may electrically connect the semiconductor substrate 211 and the semiconductor pattern 227 that are spaced apart from each other. That is, the semiconductor pattern 227 is electrically connected to the semiconductor substrate 211 via the connection pattern 229.

An active pattern 231 may be disposed on the semiconductor pattern 227. The active pattern 231 may include a semiconductor material. For example, the active pattern 231 may include a semiconductor material in a single crystal state. Unlike shown, the active pattern 231 may include a rounded edge. For example, the active pattern 231 may be formed in a nanowire shape.

The first isolation insulating layer 225 may be disposed to surround the active pattern 231. The first isolation insulating layer 225 may be disposed on the bottom surface and some sidewalls of the active pattern 231. The first isolation insulating layer 225 may extend onto the top surface of the active pattern 231. Alternatively, a separate gate insulating layer 252 may be disposed on the active pattern 231. The first isolation insulating layer 225 may spatially separate the active pattern 231 from other components. That is, the first isolation insulating film 225 may be a buried insulating film of the SOI region in the semiconductor substrate.

The first isolation insulating film 225 may be at least one selected from various insulating films including an oxide film, a nitride film, and an oxynitride film. For example, the first isolation insulating layer 225 may be an ONO layer.

The gate electrode 255 may be disposed on the top surface and sidewalls of the active pattern 231. The gate electrode 255 may cover a portion of the active pattern 231. Unlike the illustrated figure, the gate electrode 255 may extend on some lower surfaces of the active pattern 231. In detail, the gate electrode 255 may extend to an edge portion of the lower surface. The transistor formed thereby may be an omega transistor.

11A to 18C, a method of forming a semiconductor device according to another embodiment of the present invention will be described. 11A through 18A are perspective views of the semiconductor device, and FIGS. 11B through 18B and 11C through 18C are cross-sectional views of the semiconductor device taken along lines II ′ and II-II ′ shown in FIGS. 11A through 18A.

11A through 11C, the sacrificial layer 220 and the active layer 230 are sequentially stacked on the semiconductor substrate 210. The description of the semiconductor substrate, the sacrificial layer, and the active layer described above with reference to FIGS. 1A to 1C may be equally applicable to the following description.

12A through 12C, the active layer 230 and the sacrificial layer 220 may be etched to form an active pattern 231 and a sacrificial pattern 221. The active pattern 231 and the sacrificial pattern 221 may be formed by forming an first mask 241 on the active layer 230 of FIG. 11A and then performing an etching process using the same as an etching mask. During the etching process, the semiconductor substrate 210 may serve as an etch stop layer. In this case, a portion of the semiconductor substrate 210 may be etched. The etched semiconductor substrate 211 may have a protrusion 213 and a bottom 212.

13A through 13C, a support insulating layer 242 may be formed to surround both ends of the stacked structure of the active pattern 231 and the sacrificial pattern 221. The supporting insulating layer 242 may be formed by forming an insulating layer to cover all of the sidewalls of the stacked structure, and then etching the insulating layer to expose a portion of the sidewalls of the laminated structure. Etching of the insulating layer may be performed by anisotropic etching using the second mask 251.

14A to 14C, the sacrificial pattern 221 may be removed to form an empty space 222. The empty space 222 may expose a lower surface of the active pattern 231 and an upper surface of the protrusion 213 of the semiconductor substrate.

15A through 15C, a first isolation insulating layer 225 may be formed on the bottom surface and sidewalls of the active pattern 231. An isolation insulating layer 223 may be formed on the top surface and the sidewall of the protrusion 213 of the semiconductor substrate. The isolation insulating layer 223 may also be formed on an upper surface of the bottom portion 212 of the semiconductor substrate. The first isolation insulating layer 225 and the isolation insulating layer 223 may be formed at the same time.

The first isolation insulating film 225 and the isolation insulating film 223 may be at least one selected from various insulating films including an oxide film, a nitride film, and an oxynitride film. In some embodiments, the first isolation insulating layer 225 and the isolation insulating layer 223 may be ONO layers.

16A through 16C, a semiconductor film 226 filling the empty space 222 is formed. Forming the semiconductor film 226 may include forming a semiconductor film on the semiconductor substrate 211 and anisotropically etching the semiconductor film. The etching of the semiconductor film may be performed until the top surface of the isolation insulating layer 223 on the bottom portion 212 of the semiconductor substrate is exposed. Thereafter, the exposed isolation insulating layer 223 is etched to form a second isolation insulating pattern 224. The upper surface of the bottom portion 212 of the semiconductor substrate is exposed by etching the separation insulating layer 223. An etching process for the isolation insulating layer 223 may be a wet etching process.

The semiconductor layer 226 is interposed between the active pattern 231 and the protrusion 213 of the semiconductor substrate, and extends on the sidewall of the active pattern 231 and the sidewall of the protrusion 213 of the semiconductor substrate. Can be.

A connection film 228 is formed between the semiconductor film 226 and the semiconductor substrate 211. The connection layer 228 may include the same material as the semiconductor layer 226. For example, the connection layer 228 and the semiconductor layer 226 may include a semiconductor material in a polycrystalline state. In an embodiment, the semiconductor film 226 may be formed in an amorphous state and then converted into a polycrystalline state by factors such as heat generated in a subsequent process.

In one embodiment, the connection film 228 and the semiconductor film 226 may be formed at the same time. In this case, an etching process for the second isolation insulating layer 223 may be performed first. That is, at least a portion of the second isolation insulating layer 223 on the bottom portion 212 of the semiconductor substrate may be removed to expose at least a portion of the top surface of the bottom portion 212 of the semiconductor substrate.

17A to 17C, the semiconductor layer 226 and the connection layer 228 are etched to form a semiconductor pattern 227 and a connection pattern 229. Top surfaces of the semiconductor pattern 227 and the connection pattern 229 are positioned higher than the top surface of the isolation insulating layer 223. Upper surfaces of the semiconductor pattern 227 and the connection pattern 229 may be lower than a lower surface of the active pattern 231. The etching of the semiconductor layer 226 and the connection layer 228 may be performed until the isolation insulating layer 223 is not exposed.

Unlike shown, isotropic etching may be additionally performed on the semiconductor film 226 and the connection film 228. As a result, a part of the lower surface of the first isolation insulating layer 225 may be exposed.

The upper surface of the active pattern 231 is exposed by removing the first mask 241. The first isolation insulating layer 225 and the support insulating layer 242 on the sidewalls of the first mask 241 may be etched together. The support insulating layer 242 may be removed until at least a portion of the sidewall of the active pattern 231 is exposed. Alternatively, all of the supporting insulating layer 242 may be removed.

A gate insulating layer 252 is formed on the upper surface of the active pattern 231. The gate insulating layer 252 may be formed by oxidizing an upper surface of the active pattern 231. Alternatively, the gate insulating film 252 may be formed by any one selected from various insulating film forming methods.

An isolation layer 253 may be formed on the connection pattern 229 and the semiconductor pattern 227. The device isolation layer 253 may have an upper surface lower than an upper surface of the active pattern 231.

18A to 18C, a gate electrode 255 may be formed to cover the top surface and sidewalls of the active pattern 231. The gate electrode 255 may be formed on an upper surface of the active pattern 231 and may extend on sidewalls of the active pattern 231. The gate electrode 255 may include a doped semiconductor, a metal, or a metal compound. The gate electrode 255 may be spaced apart from the active pattern 231 by the gate insulating layer 252 and the first isolation insulating layer 225.

An application of embodiments of the present invention is described with reference to FIG. 19. Referring to FIG. 19, SOI structures having different thicknesses of insulating layers may be formed in one semiconductor substrate. In the drawing, region A may be an SOI device region including a thin buried oxide (BOX), and region B may be an SOI device region including a thick buried insulating film.

The region A may be formed by the method described above with reference to FIGS. 1A to 8C. Specifically, the semiconductor substrate 2100 including the A region and the B region is prepared. A sacrificial layer, an active layer, and a first mask 2230 are stacked on the semiconductor substrate 2100 as shown in FIGS. 1A to 1C. The sacrificial layer and the active layer are anisotropically etched using the first mask 2230 as an etching mask. That is, the sacrificial layer and the active layer of the A region and the sacrificial layer and the active layer of the B region are separated. As a result, stacked structures in which sacrificial patterns and active patterns are stacked in the A and B regions are formed.

A support insulating film is formed in contact with both ends of the stacked structures. The supporting insulating film may be similar to the supporting insulating film 142 described above with reference to FIGS. 2A to 2C. Thereafter, after forming a mask on the supporting insulating layer, the mask is anisotropically etched using a mask pattern. Thereby, sidewalls of the laminate structures are exposed.

The sacrificial patterns of the stacked structures are removed. The sacrificial patterns may be removed by wet etching. An empty space 2122 is formed between the active pattern 2131 and the semiconductor substrate 2100 by removing the sacrificial patterns. The lower surface of the active pattern 2131 and the upper surface of the semiconductor substrate 2100 may be exposed by removing the sacrificial patterns.

A buried insulating film 2225 and a separation insulating film 2223 are formed on the exposed lower surface of the active pattern 2131 and the upper surface of the semiconductor substrate 2100. The investment insulating film 2225 and the isolation insulating film 2223 may be formed at the same time.

A box insulating film 2200 is formed to fill the empty space 2122. The box insulating layer 2200 may surround the patterns of the region A and the region B and fill the empty space 2122. The box insulating layer 2200 of the A region is removed. At this time, the buried insulation film 2225 and the isolation insulation film 2223 in the region A may be removed at the same time. Subsequently, a buried insulating film, a separation insulating pattern, a semiconductor pattern, and a connection pattern may be formed in the region A as described above with reference to FIGS. 1A through 10C.

The above-described buried insulating film may be a thin box surrounding the active region of the A region. In addition, the box insulating layer 2200 may be a thick box in the active region of the B region. Since the active regions of the A region and the B region are electrically and / or spatially spaced apart from the substrate, each device including the active regions may exhibit different characteristics. As shown, embodiments of the present invention can be applied to implement structures suitable for the characteristics of each device in one substrate.

Another application according to embodiments of the present invention is described with reference to FIG. 20. There is provided a semiconductor substrate 1110 including region A and region B.

Well regions 1111a and 1111b may be provided in the semiconductor substrates 1110 in regions A and B, respectively. In an embodiment, the well regions 1111a and 1111b of the A region and the B region may be doped with dopants of different conductivity types. In another embodiment, the well regions 1111a and 1111b of the A region and the B region may be doped with dopants of the same conductivity type.

Semiconductor patterns 1127a and 1127b may be disposed on the well regions 1111a and 1111b. The semiconductor patterns 1127a and 1127b may include a semiconductor material in a polycrystalline state. The semiconductor patterns 1127a and 1127b may be electrically connected to the well regions 1111a and 1111b by the connection patterns 1129a and 1129b.

The well regions 111a and 111b of the two regions may be electrically connected to the semiconductor patterns 1127a and 1127b by the connection patterns 1129a and 1129b. In addition, the semiconductor substrate 1110 and the active patterns 1131a and 1131b may be electrically connected to each other via the semiconductor patterns 1127a and 1127b and the connection patterns 1129a and 1129b.

In one embodiment, region A and region B may include transistors of the same mode. For example, transistors in an inversion mode may be disposed in the A and B regions. In detail, the well region 1111a of the A region may be doped with a p-type dopant, and the source / drain region 1135a may be doped with an n-type dopant. The gate electrode 1156a of the A region may be doped with an n-type dopant. The well region 1111b of the B region may be doped with an n-type dopant, and the source / drain region 1135b may be doped with a p-type dopant. The gate electrode 1156b of the B region may be doped with a p-type dopant.

Alternatively, the transistors in region A and region B may be transistors in an accumulation mode. In this case, the well 1111a of the A region may be doped with p-type dopants, the source / drain region 1135a may be n-type, and the gate electrode 1156a may be doped with p-type dopants. The well 1111b of the region B may be doped with n-type dopants, the source / drain region 1135a may be p-type, and the gate electrode 1156b may be n-type dopants.

In another embodiment, the transistor in region A and the transistor in region B may include transistors of different modes. For example, an inversion mode transistor may be disposed in one of the regions A and B, and a storage mode transistor may be disposed in another region. Specifically, the wells 1111a and 1111b of the A region and the B region may be doped with dopants of the same conductivity type. The source / drain region 1135a of the A region includes the same conductivity type dopants as the well 1111a of the A region, and the source / drain region 1135b of the B region is opposite to the well region 1111b. It may include conductive dopants. The gate electrode 1156a in the A region includes dopants of a conductivity type opposite to that of the source / drain region 1135a, and the gate electrode 1156b of the B region is the same conductivity type as the source / drain region 1135b. May include dopants. In example embodiments, the semiconductor patterns 1127a and 1127b may also include dopants. In this case, concentrations of the dopants in the semiconductor patterns 1127a and 1127b may be higher than concentrations of the dopants in the well regions 1111a and 1111b.

1A through 10A are perspective views illustrating a semiconductor device in accordance with an embodiment of the present invention.

1B to 10B are cross-sectional views taken along the line II ′ of FIG. 1A to FIG. 10A, and FIGS. 1C to 10C are cross-sectional views taken along the line II-II ′, respectively.

11A to 18A are perspective views illustrating a semiconductor device according to another exemplary embodiment of the present invention.

11B to 18B are cross-sectional views taken along the line II ′ of FIG. 11A to 18A, and FIGS. 11C to 18C are cross-sectional views taken along the line II-II ′ of FIG. 11A to 18A, respectively.

19 is a view for explaining an application example of the embodiments of the present invention.

20 is a view for explaining another application example of the embodiments of the present invention.

Claims (10)

Semiconductor substrates; A first isolation insulating pattern on the semiconductor substrate; An active pattern on the first isolation insulating pattern; A semiconductor pattern between the semiconductor substrate and the first isolation insulating pattern; A second isolation insulating pattern between the semiconductor substrate and the semiconductor pattern; And And a connection pattern connecting the semiconductor substrate and the semiconductor pattern. The method according to claim 1, Further comprising a gate insulating film and a gate electrode sequentially stacked on the active pattern, And a depletion layer is formed in the active pattern and the semiconductor pattern during operation of the semiconductor device. The method according to claim 2, And the depletion layer extends into the semiconductor substrate. The method according to claim 1, The connection pattern is in contact with a semiconductor substrate on one side of the semiconductor pattern and one side of the semiconductor pattern. The method according to claim 1, The second isolation insulating pattern may include the same insulating material as the first isolation insulation pattern. The method according to claim 1, And the semiconductor substrate and the semiconductor pattern are electrically connected by the connection pattern. The method according to claim 1, The gate electrode extends over sidewalls of the active pattern, and the first isolation insulating pattern extends between the gate electrode and sidewalls of the active pattern. The method according to claim 1, The channel region in the active pattern includes an undoped semiconductor material, The semiconductor pattern includes a semiconductor material doped. The method according to claim 1, The connection pattern includes a semiconductor material or a conductive material. The method according to claim 9, The semiconductor device may include the connection pattern and the semiconductor pattern.

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