KR20100128703A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to increase the data speed without lowering the threshold voltage of a transistor by driving first with the voltage having lower level than the level of the target source voltage. CONSTITUTION: A sense amplifier and input-output circuit(160) comprises a precharge circuit(161), a first sense amplifier(162), and a second sense amplifier(163). The precharge circuit precharges a bit line(BL) and a complementary bit line(BLB) by using the precharge voltage(VBL). The first sense amplifier comprises a pair of N type MOS transistors(MN1, MN2) cross-coupled between the bit line and the complementary bit line.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a technique for improving dynamic performance of a sense amplifier for sensing data stored in a memory cell array.

In general, a semiconductor memory device receives a bit line and a complementary bit line for charge stored in a memory cell, and amplifies a voltage difference between the bit line and the complementary bit line based on the received charge to sense data stored in the memory cell. And a bit line sense amplifier (hereinafter referred to as a 'sense amplifier'). In accordance with the miniaturization of semiconductor process technology, securing a sensing margin of a sense amplifier is a problem in order to lower an operating voltage and reduce an operating current of a semiconductor memory device.

The sense amplifier includes a plurality of transistors. In order to secure a sensing margin of the sense amplifier, there is a method of lowering the threshold voltage of the transistor included in the sense amplifier. However, when the threshold voltages of the transistors included in the sense amplifier are lowered, problems such as sensing errors and increased current consumption due to leakage currents of the transistors may occur.

Accordingly, a technical problem of the present invention is to provide a semiconductor memory device capable of securing a sensing margin of a sense amplifier and improving an operation speed without lowering a threshold voltage of a transistor included in the sense amplifier by improving the sensing operation of the sense amplifier. To provide.

The semiconductor memory device for achieving the above technical problem may include a sense amplifier and a voltage supply circuit. The sense amplifier may include an N-type metal oxide semiconductor (MOS) transistor pair that is cross-coupled between the bit line and the complementary bit line. The voltage supply circuit may supply at least one source voltage having a voltage level lower than that of a target source voltage to a common source of the N-type MOS transistor pair in a data sensing operation, and then supply the target source voltage.

The voltage supply circuit may include a voltage generator circuit and a switch circuit. The voltage generation circuit may generate the target source voltage and the at least one source voltage. The switch circuit may supply the at least one source voltage and the target source voltage to a common source of the N-type MOS transistor.

The semiconductor memory device may have a sense amplifier including a P-type MOS transistor pair cross-coupled between the bit line and the complementary bit line. And a voltage supply circuit for supplying at least one source voltage having a voltage level and then supplying the target source voltage. Here, the voltage supply circuit is a voltage generation circuit for generating the target source voltage and the at least one source voltage and a switch circuit for supplying the at least one source voltage and the target source voltage to a common source of the P-type MOS transistor. It may include.

The semiconductor memory device for solving the above technical problem may include a first sense amplifier, a second sense amplifier, and a voltage supply circuit. The first sense amplifier may include an N-type MOS transistor pair cross-coupled between the bit line and the complementary bit line. The second sense amplifier may include a P-type MOS transistor pair cross-coupled between the bit line and the complementary bit line.

The voltage supply circuit sequentially supplies at least one first source voltage having a voltage level lower than a level of a first target source voltage to a common source of the N-type MOS transistor pair in a data sensing operation, and then supplies the first target voltage. Supplying a source voltage, and supplying at least one second source voltage having a voltage level higher than that of a second target source voltage to a common source of the P-type MOS transistor pair in reverse order, and then supplying the second target source voltage. Can supply

The voltage supply circuit may include a voltage generator circuit and a switch circuit. The voltage generation circuit may generate the first target source voltage, the second target source voltage, the at least one first source voltage, and the at least one second source voltage. The switch circuit sequentially supplies the at least one first source voltage and the first target source voltage to a common source of the N-type MOS transistor pair, and the at least one second source voltage and the second target source. The voltage may be supplied in reverse order to a common source on the P-type MOS transistor.

The semiconductor memory device for solving the above technical problem may include a main sense amplifier, an auxiliary sense amplifier, and a voltage supply device. The main sense amplifier may include an N-type MOS transistor pair that is cross-coupled between the bit line and the complementary bit line and performs a data sensing operation based on a target source voltage supplied to a common source.

The auxiliary sense amplifier is connected between the bit line and the complementary bit line and is smaller in size than the N-type MOS transistor pair and has a data sensing operation based on a source voltage having a voltage level lower than that of the target source voltage. It may include an N-type MOS transistor pair to perform. The voltage supply circuit may supply the source voltage to the auxiliary sense amplifier during a data sensing operation, and then supply the target source voltage to a common source of the N-type MOS transistor of the main sense amplifier.

The voltage supply circuit supplies the source voltage to one of the common sources of the target source voltage, the voltage generation circuit for generating the source voltage, and the N-type MOS transistor pair of the auxiliary sense amplifier, and then supplies the source voltage to the main sense amplifier. It may include a switch circuit for supplying the target source voltage to a common source of the N-type MOS transistor.

The semiconductor memory device for solving the above technical problem is cross-coupled between the bit line and the complementary bit line, the main sense includes a P-type MOS transistor pair for performing a data sensing operation based on a target source voltage supplied to a common source An amplifier, which is connected between the bit line and the complementary bit line, is smaller in size than the P-type MOS transistor pair, and performs a data sensing operation based on a source voltage having a voltage level higher than that of the target source voltage An auxiliary sense amplifier including a P-type MOS transistor pair and a voltage supplying the source voltage to the auxiliary sense amplifier in a data sensing operation and then supplying the target source voltage to a common source of the P-type MOS transistor of the main sense amplifier It may also include a supply circuit.

Here, the voltage supply circuit supplies the source voltage to one of the common sources of the target source voltage, the voltage generation circuit for generating the source voltage, and the P-type MOS transistor pair of the auxiliary sense amplifier, and then the main sense. It may include a switch circuit for supplying the target source voltage to a common source of the P-type MOS transistor of the amplifier.

As described above, the semiconductor memory device according to the embodiment of the present invention first drives the N-type sense amplifier to a voltage having a voltage level lower than that of the target voltage during data sensing, or the P-type sense amplifier is a level of the target source voltage. By first driving to a voltage having a lower voltage level, the data sensing margin and data sensing speed can be increased without lowering the threshold voltage of the transistor.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

In the present specification, when one component 'transmits' data or a signal to another component, the component may directly transmit the data or signal to the other component, and at least one other component. Through this means that the data or signal can be transmitted to the other component.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a block diagram of a semiconductor memory device 100 according to an embodiment of the present invention. Referring to FIG. 1, the semiconductor memory device 100 may include a memory cell array 110, an address buffer 120, a controller 130, a row decoder 140, a column decoder 150, a sense amplifier, and an input / output circuit 160. ), An input / output buffer 170, and a voltage supply circuit 180.

The memory cell array 110 includes a plurality of memory cells (not shown), each of which may store data, and includes a plurality of word lines (not shown) and a plurality of bit lines (not shown) connected to the plurality of memory cells. C) and complementary bit lines (not shown). The address buffer 120 buffers the input address signal to the controller 130, the row decoder 140, and the column decoder 150. The controller 130 receives the address signal and controls the row decoder 140, the column decoder 150, and the sense amplifier and input / output circuit 160 based on the write, read, and erase commands.

The row decoder 140 selects a word line connected to memory cells for inputting / outputting data in response to the address signal and a command received from the controller 130, and the column decoder 150 selects the address signal and the controller 130. Select a bit line and a complementary bit line coupled to memory cells for inputting / outputting data in response to a command received from the device.

The sense amplifier and input / output circuit 160 inputs data to or outputs data from memory cells that are data input targets through bit lines and complementary bit lines. The input / output buffer 170 buffers data input / output through the sense amplifier and the input / output circuit 160.

The voltage supply circuit 180 generates a plurality of voltages to supply a voltage corresponding to each component of the semiconductor memory device 100. For example, the voltage supply circuit 180 may include a plate voltage, an internal boosted voltage, an internal low voltage, and a precharge voltage based on an operating voltage supplied from a power supply terminal. ) And various internal voltages such as substrate back-bias voltage.

The present invention aims at improving the operating characteristics of the sense amplifier and the input / output circuit 160. Hereinafter, the operation of the sense amplifier, the input / output circuit and the voltage supply circuit of the DRAM, which is a representative nonvolatile memory device, will be described. However, the scope of the present invention is not limited thereto, and the present invention can be applied to all semiconductor memory devices including a sense amplifier using a transistor.

2 is a circuit diagram of an embodiment of a sense amplifier and input / output circuit 160 and a voltage supply circuit 180 of the semiconductor memory device 100 according to an embodiment of the present invention. Referring to FIG. 2, the sense amplifier and the input / output circuit 160 include a precharge circuit 161, a first sense amplifier 162, and a second sense amplifier 163, and the voltage supply circuit 180. Includes switch circuits MN3, MN4, and MP3.

The precharge circuit 161 uses the plurality of transistors 161a, 161b, and 161c that are switched in response to the precharge signal PEQ to convert the precharge voltage VBL into the bit line BL and the complementary bit line BLB. Precharge using). The first sense amplifier 162 and the second sense amplifier 163 sense the data stored in the memory cell by amplifying a voltage difference between the bit line BL and the complementary bit line BLB.

The first sense amplifier 162 includes N-type MOS transistor pairs MN1 and MN2 cross-coupled between the bit line BL and the complementary bit line BLB. The second sense amplifier 163 includes P-type MOS transistor pairs MP1 and MP2 cross coupled between the bit line BL and the complementary bit line BLB.

As shown in FIG. 2, the gates of a pair of transistors connected between the bit line BL and the complementary bit line BLB cross the bit line BL and the complementary bit line BLB, as shown in FIG. 2. And a structure in which the same voltage is applied to the common source of the pair of transistors.

In the data sensing operation, the first sense amplifier 162 performs data sensing based on the source voltage VBB lower than the target source voltage VSSA, and then performs data operation sensing based on the target source voltage VSSA. . By the operation of the first sense amplifier 162, the sensing margin of the first sense amplifier 162 increases.

At the start of the data sensing operation, a source voltage VBB lower than the target source voltage VSSA is applied to the common source of the N-type MOS transistor pairs MN1 and MN2 so that the gate source voltage of the N-type MOS transistor pairs MN1 and MN2 is It is relatively higher than when the target source voltage VSSA is supplied. The sensing margin of the first sense amplifier 162 is increased by the gate source voltage of the relatively high N-type MOS transistor pairs MN1 and MN2. Furthermore, the relatively high gate source voltage of the N-type MOS transistor pairs MN1 and MN2 also increases the operating speed of the first sense amplifier 162.

The voltage supply circuit 180 has a source voltage VBB having a voltage level lower than that of the target source voltage VSSA at the common source S1 of the N-type MOS transistor pairs MN1 and MN2 of the first sense amplifier 162. ) And then the target source voltage (VBB). Although not shown in FIG. 1, the voltage supply circuit 180 may further include a capacitor for stably supplying the source voltage VBB to the common source S1 of the N-type MOS transistor pairs MN1 and MN2. .

Referring to FIG. 1, one source voltage VBB is supplied to a common source S1 of the first sense amplifier 162, and then a target source voltage VSSA is provided, but the scope of the present invention is limited thereto. no. For example, the common source S1 of the first sense amplifier 162 is sequentially provided with at least one source voltage having a voltage level lower than that of the target source voltage VSSA, that is, from a source voltage having a low voltage level to a high source. In order of voltage, the next target source voltage VSSA may be supplied.

The voltage supply circuit 180 may supply the target source voltage VDDA to the common source S2 of the P-type MOS transistors MP1 and MP2 of the second sense amplifier 163. The voltage supply circuit 180 includes a power generation circuit (not shown) and switch circuits 182 and 184.

The voltage generation circuit 180 generates target source voltages VSSA and VDDA and a source voltage VBB supplied to the first sense amplifier 162 and the second sense amplifier 163, and the switch circuits 182 and 184. ) Sequentially supplies the source voltage VBB and the target source voltage VSSA to the common source S1 of the N-type MOS transistor pairs MN1 and MN2 of the first sense amplifier 162 or the target source voltage VDDA. May be supplied to the common source S2 of the second sense amplifier 163.

The switch circuits 182 and 184 include a first switch circuit 182 and a second switch circuit 184. The first switch circuits 182 and 184 may include a switch MN3 and a second voltage supply signal LANG2 for supplying the source voltage VBB to the first sense amplifier 162 in response to the first voltage supply signal LANG1. And a switch MN4 for supplying the target source voltage VSSA to the first sense amplifier 162 in response to. The second switch circuits 182 and 184 include a switch MP3 for supplying the target source voltage VDDA to the second sense amplifier 163 in response to the fourth voltage supply signal LAPG.

3 is a timing diagram for describing an operation of the sense amplifier, the input / output circuit 160, and the voltage supply circuit 180 shown in FIG. 2. 2 and 3, the operation of the sense amplifier, the input / output circuit 160, and the voltage supply circuit 180 will be described based on the voltage supplied to the first sense amplifier 162.

The precharged state of the bit line BL and the complementary bit line BLB is maintained until the time t0. From the time t1 at which the word line select signal WL is enabled, the time stored at a time t1 after the predetermined time has elapsed, the charge stored in the pair of memory cells is output, thereby causing a voltage difference between the bit line BL and the complementary bit line BLB. do.

From the time t2, the switch MN3 for supplying the source voltage VBB to the first sense amplifier 162 is short-circuited in response to the first voltage supply signal LANG1 so that the bit line BL and the complementary bit line BLB are shorted. This begins to develop. After a predetermined time elapses after the switch MN3 for supplying the source voltage VBB to the first sense amplifier 162 is shorted, the target source voltage VSSA is supplied to the first sense amplifier 162. The switch MN4 is shorted in response to the second voltage supply signal LANG2 so that the bit line BL and the complementary bit line BLB are fully developed.

According to the above-described process, the sensing operation is performed based on the source voltage VBB lower than the target source voltage VSSA, and then the sensing operation is performed based on the target source voltage VSSA, thereby sensing the first sense amplifier 162. Margin and sensing speed can be increased.

In the above, the semiconductor memory device 100 drives the first sense amplifier 162 to one source voltage VBB that is lower than the target source voltage VSSA and then to the target source voltage VSSA, thereby sensing and sensing data. We have seen that speed can be increased. In another embodiment, the first sense amplifier 162 may be driven by sequentially applying at least two source voltages lower than the target source voltage VSSA in the order of voltage level, and then driving the first sense amplifier 162 by applying the target source voltage VSSA. .

 However, the semiconductor memory device 100 drives the second sense amplifier 163 to a source voltage VDDA 'higher than the target source voltage VDDA and then to a source voltage VDDA' to secure a data sensing margin and sense You can increase the speed. Hereinafter, the process will be described with reference to FIGS. 4 and 5. In another embodiment, the second sense amplifier 163 may be driven by sequentially applying at least two source voltages lower than the target source voltage VDDA in order of voltage level, and then driving the second sense amplifier 163 by applying the target source voltage VDDA. .

4 is a partial circuit diagram of a voltage supply circuit 182 'corresponding to a sense amplifier 163, i.e., a second sense amplifier 163, comprising a P-type MOS transistor pair. In the data sensing operation, the source voltage VDDA ′ having a voltage level higher than that of the target source voltage VDDA is applied to the common source S2 of the P-type MOS transistors MP1 and MP2 of the second sense amplifier 163. To supply the target source voltage VDDA after supply. An operation of the voltage supply circuit 182 'will be described with reference to FIGS. 2 and 4.

The voltage supply circuit 182 ′ may include a voltage generator (not shown) for generating a target source voltage VDDA and a source voltage VDDA ′. The voltage supply circuit 182 'includes switch circuits MP3 and MP4 for supplying a source voltage VDDA' to a common source of the P-type MOS transistors MP1 and MP2 and then supplying a target voltage.

In the data sensing operation, the second sense amplifier 163 performs data sensing based on the source voltage VDDA 'higher than the target source voltage VDDA, and then performs the data operation sensing based on the target source voltage VDDA. do. By the operation of the second sense amplifier 163, the sensing margin of the second sense amplifier 163 increases.

At the start of the data sensing operation, a source voltage VDDA 'higher than the target source voltage VDDA is applied to the common source S2 of the P-type MOS transistors MP1 and MP2 so that the gate source of the P-type MOS transistors MP1 and MP2 is applied. The voltage is relatively lower than when the target source voltage VDDA is supplied. The sensing margin of the second sense amplifier 163 is increased by the gate source voltage of the relatively lower P-type MOS transistors MP1 and MP2. . Furthermore, the relatively low gate source voltage of the P-type MOS transistors MP1 and MP2 also increases the operating speed of the second sense amplifier 163.

 Although not shown in FIG. 4, the voltage supply circuit 180 lines the source voltage VDDA ′ to stably supply the source voltage VDDA ′ to the common source S2 of the P-type MOS transistors MP1 and MP2. And a capacitor connected between the ground voltage line and the ground line.

Referring to FIG. 4, one source voltage VDDA ′ is supplied to the common source S2 of the second sense amplifier 163, and then a target source voltage VSSA is supplied. It is not limited. For example, the common source S2 of the second sense amplifier 163 has at least one source voltage having a voltage level higher than that of the target source voltage VDDA in reverse order, that is, from a source voltage having a high voltage level to a low level. In order of source voltage, the next target source voltage VDDA may be supplied.

FIG. 5 is a timing diagram for describing an operation of the sense amplifier 163, that is, the second sense amplifier 163 including the voltage supply circuit shown in FIG. 4 and the P-type MOS transistor pair. 2 and 4 to 5, the operation of the sense amplifier, the input / output circuit 160, and the voltage supply circuit 180 will be described based on the voltage supplied to the second sense amplifier 163.

The precharged state of the bit line BL and the complementary bit line BLB is maintained until the time t0. From the time t1 at which the word line select signal WL is enabled, the time stored at a time t1 after the predetermined time has elapsed, the charge stored in the pair of memory cells is output, thereby causing a voltage difference between the bit line BL and the complementary bit line BLB. do.

From time t2, the switch MP4 for supplying the source voltage VDDA 'to the second sense amplifier 163 is shorted in response to the fourth voltage supply signal LAPG' to short-circuit the bit line BL and the complementary bit line ( BLB) begins to develop. The target source voltage VDDA is transferred to the second sense amplifier 163 after a predetermined time elapses after the switch MP4 for supplying the source voltage VDDA 'to the second sense amplifier 163 is shorted. The switch MP3 for supplying is shorted in response to the third voltage supply signal LAPG so that the bit line BL and the complementary bit line BLB are fully developed.

According to the above-described process, the sensing operation is performed based on the source voltage VDDA 'higher than the target source voltage VDDA, and then the sensing operation is performed based on the target source voltage VDDA. The sensing margin and the sensing speed can be increased.

6 is a circuit diagram of another embodiment of the sense amplifier and input / output circuit 160 and the voltage supply circuit of the semiconductor memory device 100 according to the embodiment of the present invention. Referring to FIG. 6, the sense amplifier and input / output circuit 160 includes a main sense amplifier 162 and an auxiliary sense amplifier 162 ′, and the voltage supply circuit 180 includes a main sense amplifier 162 and an auxiliary sense amplifier. Switch circuits 184a and 184b for supplying a voltage to 162 '.

The main sense amplifier 162 includes N-type MOS transistor pairs MN1 and MN2 that perform data sensing operations based on the target source voltage VSSA supplied to the common source S1. The auxiliary sense amplifier 162 'is connected between the bit line BL and the complementary bit line BLB, and the data sensing operation is performed based on the source voltage VBB having a voltage level lower than the level of the target source voltage VSSA. N-type MOS transistor pairs MN1 ′ and MN2 ′ may be included.

The size of the N-type MOS transistor pairs MN1 ′ and MN2 ′ of the auxiliary sense amplifier 162 ′ may reduce the data sensing loading based on the source voltage VBB and increase the operating speed of the main sense amplifier 162. It is desirable to have a smaller size than the N-type MOS transistor pairs MN1 and MN2.

The voltage supply circuit 180 supplies the source voltage VBB to the auxiliary sense amplifier 162 'during the data sensing operation, and then common source S1 of the N-type MOS transistor pairs MN1 and MN2 of the main sense amplifier 162. ) May supply a target source voltage VSSA. The voltage supply circuit 180 may include a target source voltage VSSA and a voltage generation circuit (not shown) for generating the source voltage VBB. The switch circuits 184a and 184b supply a source voltage VBB to one of the sources of the N-type MOS transistor pairs MN1 'and MN2' of the auxiliary sense amplifier 162 'and then the main sense amplifier 162. The target source voltage VSSA may be supplied to the common source S1 of the N-type MOS transistor pairs MN1 and MN2.

The operation of the sense amplifier and the input / output circuit 160 will be described sequentially based on the voltages supplied to the main sense amplifier 162 and the auxiliary sense amplifier 162 '.

First, a switch of any one of the switches MN3a and MN3b included in the first switch circuit 184 is shorted based on the voltages of the bit line BL and the complementary bit line BLB, so that the auxiliary sense amplifier 162 'is shorted. A source voltage VBB is supplied to a source of one of the N-type MOS transistor pairs MN1 'and MN2' of the N-type MOS transistor pair, and the N-type of the auxiliary sense amplifier 162 'is responsive to the first voltage supply signal LANG1. MOS transistor pairs MN1 and MN2 are turned on.

The auxiliary sense amplifier 162 ′ has a gate source voltage of the turned-on transistor that is relatively lower than when the target source voltage VSSA is applied due to the application of the source voltage VBB lower than the target source voltage VSSA. Performs a data sensing operation. After the data sensing operation of the auxiliary sense amplifier 162 ', the main sense amplifier 162 performs the data sensing operation based on the target source voltage VSSA.

That is, in the early stage of data sensing, the auxiliary sense amplifier 162 ′ having a large sensing margin and a fast operation speed performs a data sensing operation, and then the main sense amplifier 162 performs a data sensing operation. In another embodiment of the present invention, the main sense amplifier (not shown) and the auxiliary sense amplifier (not shown) may be implemented as a P-type MOS transistor pair.

In this case, the second sense amplifier 163 performing a data sensing operation based on the target source voltage VDDA shown in FIG. 2 is used as the main sense amplifier and the data sensing is performed based on a source voltage lower than the target source voltage VDDA. By operating the auxiliary amplifier performing the operation at the beginning of data sensing, the data sensing margin and the data sensing speed may be increased. The auxiliary sense amplifier may be similar to the auxiliary sense amplifier 162 ′ shown in FIG. 6.

At this time, the auxiliary sense amplifier is connected between the bit line BL and the complementary bit line BLB, and has a smaller size than the main sense amplifier 163 P-type MOS transistors MP1 and MP2, and has a target source voltage VDDA. It may include a P-type MOS transistor pair for performing a data sensing operation based on a source voltage having a voltage level higher than the level of.

The voltage supply circuit 180 supplies a source voltage lower than a target source voltage VDDA to the auxiliary sense amplifier during a data sensing operation, and then supplies a common source of the P-type MOS transistors MP1 and MP2 of the main sense amplifier 163. The target source voltage VDDA can be supplied to S2). At this time, the voltage supply circuit 180 supplies the source voltage to one of the common sources of the P-type MOS transistor pair of the auxiliary sense amplifier, and then the target source to the common source of the P-type MOS transistor of the main sense amplifier. It may include a switch circuit for supplying a source voltage.

FIG. 7A is a graph illustrating a data sensing result of the semiconductor memory device 100 according to an exemplary embodiment when the driving voltage is 1V. FIG. 7B illustrates a semiconductor memory device according to the comparative example of the present invention when the driving voltage is 1V. This graph shows the result of data sensing.

7A and 7B, in the case of the semiconductor memory device 100 according to an embodiment of the present invention, the voltage difference between the bit line BL and the complementary bit line BLB from the time when a voltage is supplied to the sense amplifier. Is 500mV, which is 2.41 nsec, and 3.28 nsec in the case of the semiconductor memory device according to the comparative example of the present invention. That is, the data sensing speed of the semiconductor memory device 100 according to the exemplary embodiment of the present invention is faster than the conventional semiconductor memory device.

8A is a graph illustrating a data sensing result of the semiconductor memory device 100 according to an exemplary embodiment when the driving voltage is 0.9 V. FIG. 8B illustrates a semiconductor according to the comparative example of the present invention when the driving voltage is 0.9V. A graph showing a data sensing result of a memory device.

8A and 8B, in the case of the semiconductor memory device 100 according to an embodiment of the present invention, the voltage difference between the bit line BL and the complementary bit line BLB from the time when the voltage is supplied to the sense amplifier. Is 3.27 nsec, which is 500 mV, and 4.64 nsec for the semiconductor memory device according to the comparative example of the present invention. That is, the data sensing speed of the semiconductor memory device 100 according to the exemplary embodiment of the present invention is faster than the conventional semiconductor memory device.

FIG. 9A is a graph illustrating a data sensing result of the semiconductor memory device 100 according to an exemplary embodiment when the driving voltage is 0.8 V. FIG. 9B illustrates a semiconductor according to the comparative example of the present invention when the driving voltage is 0.9V. A graph showing a data sensing result of a memory device.

9A and 9B, in the case of the semiconductor memory device 100 according to an exemplary embodiment of the present invention, the voltage difference between the bit line BL and the complementary bit line BLB from the time when a voltage is supplied to the sense amplifier. Is 500mV, which is 5.08 nsec, and 7.50 nsec in the case of the semiconductor memory device according to the comparative example of the present invention. That is, the data sensing speed of the semiconductor memory device 100 according to the exemplary embodiment of the present invention is faster than the conventional semiconductor memory device.

As described with reference to FIGS. 7A to 9B, it can be seen that the data sensing speed of the semiconductor memory device 100 according to the exemplary embodiment of the present invention increases as the driving voltage decreases.

The semiconductor memory device 100 according to an embodiment of the present invention may be mounted using various types of packages. For example, the semiconductor memory device 100 according to an embodiment of the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) It can be implemented using packages such as Wafer-Level Processed Stack Package (WSP).

Although the invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

2 is a circuit diagram of an embodiment of a sense amplifier and input / output circuit and a voltage supply circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 3 is a timing diagram illustrating the operation of the sense amplifier, the input / output circuit, and the voltage supply circuit shown in FIG. 2.

4 is a circuit diagram of a voltage supply circuit corresponding to a sense amplifier including a P-type MOS transistor pair.

FIG. 5 is a timing diagram for describing an operation of a sense amplifier including the voltage supply circuit shown in FIG. 4 and a P-type MOS transistor pair.

6 is a circuit diagram of another embodiment of a sense amplifier and an input / output circuit and a voltage supply circuit of a semiconductor memory device according to an embodiment of the present invention.

FIG. 7A is a graph illustrating a data sensing result of a semiconductor memory device according to an exemplary embodiment when the driving voltage is 1 V. FIG. 7B is a graph illustrating data sensing of a semiconductor memory device according to a comparative example of the present invention when the driving voltage is 1V. A graph showing the results.

8A is a graph illustrating a data sensing result of a semiconductor memory device according to an exemplary embodiment of the present invention when the driving voltage is 0.9V. FIG. 8B illustrates a semiconductor memory device according to a comparative example of the present invention when the driving voltage is 0.9V. This graph shows the results of data sensing.

FIG. 9A is a graph illustrating a data sensing result of a semiconductor memory device according to an exemplary embodiment when the driving voltage is 0.8 V. FIG. 9B is a graph illustrating a semiconductor memory device according to the comparative example of the present invention when the driving voltage is 0.9V. This graph shows the results of data sensing.

Claims (10)

A sense amplifier comprising a pair of transistors cross-coupled between the bit line and the complementary bit line; And And a voltage supply circuit configured to supply at least one source voltage having a voltage level different from that of a target source voltage to a common source of the pair of transistors during a data sensing operation of the sense amplifier, and then supply the target source voltage. Device. The method of claim 1, wherein the transistor pair is N-type metal oxide semiconductor (MOS) transistor pairs, The voltage supply circuit And supplying the target source voltage to at least one source voltage having a voltage level lower than that of the target source voltage to a common source of the N-type MOS transistor pair. The method of claim 1, wherein the transistor pair is P-type MOS transistor pair, The voltage supply circuit And supplying the target source voltage to at least one source voltage having a voltage level higher than that of the target source voltage to a common source of the P-type MOS transistor pair. The method of claim 2 or 3, wherein the voltage supply circuit A voltage generator circuit for generating the target source voltage and the at least one source voltage; And And a switch circuit for supplying the at least one source voltage and the target source voltage to a common source of the N-type MOS transistor pair or to a common source of the P-type MOS transistor. A first sense amplifier comprising an N-type MOS transistor pair cross-coupled between the bit line and the complementary bit line; A second sense amplifier comprising a P-type MOS transistor pair cross coupled between the bit line and the complementary bit line; And In the data sensing operation, at least one first source voltage having a voltage level lower than a level of a first target source voltage is sequentially supplied to a common source of the N-type MOS transistor pair, and then the first target source voltage is supplied. And a voltage supply circuit supplying at least one second source voltage having a voltage level higher than a level of a second target source voltage to a common source of the P-type MOS transistor pair in reverse order, and then supplying the second target source voltage. Semiconductor memory device comprising a. The method of claim 5, wherein the voltage supply circuit A voltage generation circuit configured to generate the first target source voltage, the second target source voltage, the at least one first source voltage, and the at least one second source voltage; And Sequentially supplying the at least one first source voltage and the first target source voltage to a common source of the N-type MOS transistor pair, and supplying the at least one second source voltage and the second target source voltage to the P-type. A semiconductor memory device comprising a switch circuit for supplying the common source on the MOS transistors in reverse order. A main sense amplifier cross-coupled between the bit line and the complementary bit line, the main sense amplifier including an N-type MOS transistor pair to perform a data sensing operation based on a target source voltage supplied to a common source; An N-type connected between the bit line and the complementary bit line, the N-type MOS transistor being smaller in size than the N-type MOS transistor pair, and performing a data sensing operation based on a source voltage having a voltage level lower than that of the target source voltage. An auxiliary sense amplifier comprising a MOS transistor pair; And And supplying the source voltage to the auxiliary sense amplifier and supplying the target source voltage to a common source of the N-type MOS transistor of the main sense amplifier during a data sensing operation. 8. The circuit of claim 7, wherein the voltage supply circuit is A voltage generator circuit for generating the target source voltage and the source voltage; And A switch circuit for supplying the source voltage to one of the common sources of the N-type MOS transistor pair of the auxiliary sense amplifier and then supplying the target source voltage to the common source of the N-type MOS transistor of the main sense amplifier. A semiconductor memory device. A main sense amplifier cross coupled between the bit line and the complementary bit line, the main sense amplifier including a P-type MOS transistor pair performing a data sensing operation based on a target source voltage supplied to a common source; A P-type connected between the bit line and the complementary bit line, the P-type MOS transistor being smaller in size than the P-type MOS transistor pair, and performing a data sensing operation based on a source voltage having a voltage level higher than that of the target source voltage. An auxiliary sense amplifier comprising a MOS transistor pair; And And supplying the source voltage to the auxiliary sense amplifier and supplying the target source voltage to a common source of the P-type MOS transistor of the main sense amplifier during a data sensing operation. 10. The circuit of claim 9, wherein the voltage supply circuit is A voltage generator circuit for generating the target source voltage and the source voltage; And A switch circuit for supplying the source voltage to one of the common sources of the P-type MOS transistor pair of the auxiliary sense amplifier and then supplying the target source voltage to the common source of the P-type MOS transistor of the main sense amplifier. A semiconductor memory device.

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