KR20100120878A - Self refresh control circuit - Google Patents

Self refresh control circuit Download PDF

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Publication number
KR20100120878A
KR20100120878A KR1020090039739A KR20090039739A KR20100120878A KR 20100120878 A KR20100120878 A KR 20100120878A KR 1020090039739 A KR1020090039739 A KR 1020090039739A KR 20090039739 A KR20090039739 A KR 20090039739A KR 20100120878 A KR20100120878 A KR 20100120878A
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KR
South Korea
Prior art keywords
signal
refresh
self
self refresh
calculator
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Application number
KR1020090039739A
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Korean (ko)
Inventor
김상희
장지은
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020090039739A priority Critical patent/KR20100120878A/en
Publication of KR20100120878A publication Critical patent/KR20100120878A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

The present invention relates to a self refresh control circuit for controlling a self refresh operation so that a stable operation can be performed in a semiconductor device. The self-refresh control circuit according to the embodiment of the present invention is characterized in that the self-refresh operation is controlled to perform the self-refresh end operation after ensuring the tRAS period when the self-refresh end command is input during the first self-refresh period. Therefore, in the present invention, after the refresh period ends, the predetermined operation is performed only after returning to a stable state after a predetermined time has elapsed, thereby stabilizing the operation of the semiconductor device.

Description

Self Refresh Control Circuit {SELF REFRESH CONTROL CIRCUIT}

The present invention relates to a self refresh control circuit for controlling a self refresh operation so that a stable operation can be performed in a semiconductor device.

In general, in a memory device such as a DRAM, a cell is dynamically configured, and cell data may be destroyed due to leakage current. Therefore, before the data of the cell becomes small enough to be detected, the data of the cell is sensed and amplified and rewritten in the cell. This operation is called a refresh operation.

The refresh method includes a method of performing refresh by inputting a low address to be refreshed from the outside, and refreshing the address by inputting a control signal (CBR) for refreshing externally and generating an address to be refreshed internally. There is a method (CBR refresh) and a hidden refresh method in which such a CBR refresh operation appears in conjunction with a normal operation. Recently, when the external control signal enters a constant state and continues without changing the state, a method of periodically making a CBR state inside the device and performing refresh is used. This method is called self refresh. do.

1 to 3 are conventional self refresh control circuits and operation timing diagrams.

In the self refresh operation, when the self refresh command AFACT is input, the internal refresh operation is performed once every predetermined period. At this time, the self refresh command is generated by the combination of the refresh command AFACT and the clock signal CKE.

The self refresh operation is divided into a refresh period and a precharge power down period. At this time, the first refresh operation in the refresh operation is a self-refresh command is entered (ENTRY) to generate a refresh command (AFACT) with a refresh command to perform a refresh operation. The refresh operation thereafter generates an internal command PSRF after a predetermined period of time internally to perform the refresh operation.

The self refresh operation is a sensing operation and a precharging operation during the tRAS period after the subword line becomes operable. In addition, the precharge power-down state remains in the tREFi section except for the tRAS section.

In general, the path from which the data is read from the DRAM from the moment the row address signal (hereinafter referred to as RAS) is activated, and the row address buffer is activated by a control signal generated from the row address buffer. This accepts the X-address and sends it to the decoder. Therefore, when the corresponding word line is activated, the cell data can be completely restored and then precharged again.

The time required until the RAS activation time (hereinafter referred to as tRAS). When the refresh operation starts in the DRAM, the word line is activated. After the word line is activated, the word line passes through the internal delay path for tRAS time and is disabled.

When the self refresh operation ends, the self refresh end command SELF REFRESH EXIT COMMAND is input as the clock signal CKE transitions to a high level. In the self refresh end operation, when the input point of the self refresh end command is the tRAS period, the self refresh end operation is performed after the tRAS operation is completed. When the input point of the self refresh end command is a section other than the tRAS section, the self refresh end command is input and the self refresh end operation is performed.

However, the conventional self refresh control circuit has the following problems. When the self refresh end command is input even within the tRAS section during the first refresh operation, the self refresh end command is input and the self refresh end operation is performed.

That is, as shown in Fig. 1, the first self refresh end command NET1 is the refresh active signal AFACT, the internal self refresh pulse SRF (high state during the tRAS period, the bank is active), and the clock signal. This signal is generated by the combination of the inverted signal CKEB of CKE and the signal CCLKB having a signal in phase.

Therefore, the high level signal of the self refresh command SRF is delayed by the delay unit 10 for a predetermined time, is converted to the low level signal via the inverter 20, and is input to the noar gate 12. At this time, the refresh active signal AFACT has a low level state. In this manner, when the clock signal CKE transitions to the high level state during the high level section of the self refresh command SRF and the low level section of the refresh active signal AFACT, the output signal NET1 of the NOA gate 12 is at a high level. Transition to a signal.

The output signal of the NAND gate 20 generates a low signal based on the output signal NET1, and the self-refresh end command SRFEXT via the inverter 22 transitions to a high level and is generated.

The second self refresh end command NET2 is determined by an internal command PSRF, a pulse signal RE for precharging after a tRAS period after bank activation, and an initial value by the setting signal RST.

Therefore, the NET2 signal, which is the output signal of the latch units 14 and 16, remains enabled by the initial value setting signal RST, but is disabled by the internal command (PSRF) signal. As the pre-charged pulse signal RE transitions to a high level, the signal is switched back to the enabled state. In this manner, the output signals NET2 of the latch units 14 and 16 transition to the high level.

The output signal of the NAND gate 20 generates a low signal based on the output signal NET1, and the self-refresh end command SRFEXT via the inverter 22 transitions to a high level and is generated.

That is, the first self refresh end operation is generated when the clock signal CKE transitions to the high level as shown in the operation timing diagram shown in FIG. 2. Then, the self refresh end operation is generated by the precharge pulse signal RE. Since the pulse signal RE is generated at the end of the tRAS interval, the self-refresh termination operation from the second time onwards does not occur in the tRAS interval.

However, as shown in FIG. 1, there is a fear that the self refresh end operation may occur regardless of the tRAS period within the first self refresh period. In this case, the semiconductor memory device may perform an operation failure while preparing a normal operation in an unstable state while a large current is consumed by the refresh period operation.

That is, a large amount of current consumption is generated while many sense amplifiers operate during the self refresh operation. Therefore, in the specification of a general semiconductor memory device, a self refresh operation is performed for 4tck periods, and then preparation for normal operation is performed for 512tck periods. However, if the self-refresh end operation is performed while the tRAS period is not terminated in the state where much current is consumed by the refresh period operation as described above, the operation of the semiconductor memory device becomes unstable. A problem arises.

Accordingly, an object of the present invention is to provide a self-refresh control circuit that can adjust an end point of a self-refresh operation in a first self-refresh operation section.

The self-refresh control circuit according to an embodiment of the present invention for achieving the above object is to generate a first ready signal for the self-refresh end operation by the combination of the self-refresh active signal AFACT and the clock signal (CCLKB). A first calculating unit; A second calculator configured to generate a second ready signal for the self refresh end operation to perform the self refresh end operation when the tRAS period ends; And a third calculator configured to generate a self-refresh end operation signal by combining the ready signals generated by the first and second calculators.

In an embodiment of the present invention, the second calculator may include a first calculator that combines an internal command PSRF and a self refresh active signal AFACT; And a second operator for generating a signal by combining a pulse signal RE for initial precharging after a tRAS period after bank activation, an initial value setting signal RST, and an output of the first operator.

In an embodiment of the present invention, the first calculating unit may further use an internal self refresh pulse (SRF) signal.

In an embodiment of the present invention, the first operation unit may include a delay unit for delaying an internal self refresh pulse (SRF) signal; And a calculator for generating a signal by combining the delayed signal, the self refresh active signal AFACT, and the clock signal CCLKB.

The self-refresh control circuit according to an embodiment of the present invention, when the self-refresh operation is input during the first self-refresh period, the self-refresh control circuit controls to perform the self-refresh end operation after ensuring the tRAS period. It is done. Therefore, in the present invention, after the refresh period ends, the predetermined operation is performed only after returning to a stable state after a predetermined time has elapsed, thereby stabilizing the operation of the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In addition, in the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout the specification.

4 is a self-refresh control circuit diagram according to an embodiment of the present invention. 5 and 6 are operation timing diagrams of the self-refresh control circuit according to the present invention.

In the self refresh operation, when the self refresh command AFACT is input, the internal refresh operation is performed once every predetermined period. At this time, the self refresh command is generated by the combination of the refresh command AFACT and the clock signal CKE.

The self refresh operation is divided into a refresh period and a precharge power down period. At this time, the first refresh operation in the refresh operation is a self-refresh command is entered (ENTRY) to generate a refresh command (AFACT) with a refresh command to perform a refresh operation. The refresh operation thereafter generates an internal command PSRF after a predetermined period of time internally to perform the refresh operation.

The self refresh operation is a sensing operation and a precharging operation during the tRAS period after the subword line becomes operable. In addition, the precharge power-down state remains in the tREFi section except for the tRAS section.

Meanwhile, in the present invention, the end of the self refresh operation is controlled to perform the self refresh end operation by the self refresh end command after ensuring the tRAS period in the same manner as the first self refresh operation period or the other self refresh operation period.

First, when the self refresh end command is input in the tRAS section during the first refresh operation, the self refresh end operation is performed at the end of the tRAS section.

First, a signal CCLKB having a signal in phase with the refresh active signal AFACT, the internal self refresh pulse SRF (high state during the tRAS period, the bank is active), and the inverted signal CKEB of the clock signal CKE. By the combination of the output signals of the NOA gate 112 is generated.

Therefore, the high level signal of the self refresh command SRF is delayed by the delay unit 110 for a predetermined time, is converted to the low level signal via the inverter 120, and is input to the noar gate 112. At this time, the refresh active signal AFACT has a low level state. As such, when the clock signal CKE transitions to the high level state during the high level section of the self refresh command SRF and the low level section of the refresh active signal AFACT, the output signal NET1 of the NOA gate 112 is at a high level. Transition to a signal.

However, the latch unit 114 in which the output signal is determined by a combination of an internal command PSRF, a pulse signal RE for precharging after a tRAS period after bank activation, and an initial value of the setting signal RST is used. The output signal NET1 of 112 is already transitioned to the low level state before the transition to the high level signal. That is, the latch unit 114 may refresh the internal command PSRF, a pulse signal RE for precharging after a tRAS period after bank activation, and an initial value regardless of the signal state of the setting signal RST. When (AFACT) transitions to the high level state, it transitions to the low level state.

Therefore, when the self-refresh end command SRFEXT is input and the clock signal CKE is switched to the high level, the refresh active signal AFACT and the internal self refresh pulse SRF (high state during the tRAS period and banks are changed). Active) and the signal CCLKB having a signal in phase with the inverted signal CKEB of the clock signal CKE, the output signal of the NOA gate 112 becomes a high level state, but the latch portions 114 and 116 The output signal of NAND gate 130 becomes a high signal, and the signal via the inverter 122 becomes a low signal because the output signal of the "

Therefore, even when the self-refresh end command SRFEXT is input and the clock signal CKE is switched to the high level, the operation signal for the self-refresh end is maintained in the disabled state (low signal). Then, when the output signal of the latch unit 114 is enabled as a high signal at the time when the tRAS period is pre-charged and the pre-charged pulse signal RE is input, the output signal of the NAND gate 130 is low. The signal is output, and thus the self refresh end operation signal via the inverter 122 is enabled in a high state.

The second self refresh end command NET2 is determined by an internal command PSRF, a pulse signal RE for precharging after the tRAS period after bank activation, and an initial value of the set signal RST.

Therefore, the NET2 signal, which is the output signal of the latching units 114 and 116, remains enabled by the initial value setting signal RST, but is disabled by the internal command PSRF signal. The charging pulse signal RE transitions to the high level and is switched back to the enabled state. In this way, the output signals NET2 of the latches 114 and 116 transition to the high level.

The output signal of the NAND gate 130 generates a low signal based on the output signal NET1, and the self-refresh end command SRFEXT via the inverter 122 transitions to a high level.

That is, in the first self refresh end operation, as shown in the operation timing diagram shown in FIG. 5, even if the self refresh end command is input and the clock signal CKE transitions to the high level, the self refresh end is performed when the current operation section is the tRAS period. No action is taken. That is, when the tRAS period ends, the self refresh end operation is generated by the precharge pulse signal RE. In addition, since the pulse signal RE is generated at the end of the tRAS period, the self-refresh termination operation from the second time onwards does not occur in the tRAS period.

The above-described preferred embodiment of the present invention has been disclosed for the purpose of illustration, and when the self-refresh end command is input during the first self-refresh period in the self-refresh operation, control to perform the self-refresh end operation after guaranteeing the tRAS period. Applicable if Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a conventional self refresh control circuit diagram,

2 is a timing chart of a conventional first self refresh operation;

3 is a timing diagram of a self refresh operation according to the related art.

4 is a self-refresh control circuit diagram according to an embodiment of the present invention;

5 is a timing diagram of a first self refresh operation according to an embodiment of the present invention;

6 is a second and subsequent self refresh operation timing diagram according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

110: delay 112,118: noah gate

120,122,124: Inverter 114,116: Latch

130: NAND Gate

Claims (4)

A first calculating unit which generates a first preparation signal for the self refresh end operation by a combination of the self refresh active signal AFACT and the clock signal CCLKB; A second calculator configured to generate a second ready signal for the self refresh end operation to perform the self refresh end operation when the tRAS period ends; And a third operation unit configured to generate a self-refresh end operation signal by combining the preparation signals generated by the first and second operation units. The method of claim 1, The second calculator may include a first calculator that combines an internal command PSRF and a self refresh active signal AFACT; And a second calculator for generating a signal by combining a pulse signal RE and an initial value setting signal RST for precharging after a tRAS period after bank activation, and an output of the first calculator. Control circuit. The method of claim 1, And the first calculating unit further uses an internal self refresh pulse (SRF) signal. The method of claim 3, wherein The first operation unit may include a delay unit for delaying an internal self refresh pulse (SRF) signal; And a calculator for generating a signal by combining the delayed signal, the self refresh active signal AFACT, and the clock signal CCLKB.
KR1020090039739A 2009-05-07 2009-05-07 Self refresh control circuit KR20100120878A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150071804A (en) * 2013-12-18 2015-06-29 에스케이하이닉스 주식회사 Semiconductor memory device and operation method for the same
CN108231104A (en) * 2016-12-15 2018-06-29 爱思开海力士有限公司 Memory device, including its storage system and storage system operating method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150071804A (en) * 2013-12-18 2015-06-29 에스케이하이닉스 주식회사 Semiconductor memory device and operation method for the same
US9263118B2 (en) 2013-12-18 2016-02-16 SK Hynix Inc. Semiconductor memory device and method for operating the same
CN108231104A (en) * 2016-12-15 2018-06-29 爱思开海力士有限公司 Memory device, including its storage system and storage system operating method
CN108231104B (en) * 2016-12-15 2021-08-27 爱思开海力士有限公司 Memory device, memory system including the same, and method of operating the memory system

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