KR20100120518A - Data storage device and read commands execution method thereof - Google Patents

Abstract

PURPOSE: A data storing device and a method for processing reading command of the same are provided to shorten the execution time about a plurality of read commands performed continuously. CONSTITUTION: A plurality of memories(310~330) is electrically connected to a plurality of channels. A controller(100) performs a queuing of a plurality of commands in a plurality of memories. Based on queued commands, the controller controls the performance of data detection section of a second command which will be performed after a first command during data transmission section of a first read command while currently performing about a plurality of channels.

Description

DATA STORAGE DEVICE AND READ COMMANDS EXECUTION METHOD THEREOF}

The present invention relates to a data storage device, and more particularly, to a data storage device employing a semiconductor as a main storage and a read command processing method thereof.

With the advent of the information society, the amount of data that individuals need to store and move is exploding. Due to the increased demand for information storage media, various types of personal data storage devices have been developed.

Among data storage devices, hard disk drives (HDDs) are widely used due to their high recording density, high data transfer speed, fast data access time, and low cost. However, since the hard disk drive has a complicated structure composed of mechanical parts, there is a problem that even a small shock and vibration may fail.

Recently, a semiconductor disk (Solid State Disk or Solid State Drive, or SSD) device adopting a semiconductor memory as the main storage has been developed as a data storage device to replace the hard disk drive. SSDs, unlike hard disk drives, do not have a mechanical configuration for driving a disk, such as a platter, a thermomotor, or the like. Thus, SSDs can reduce latency and other mechanical drive times and perform high-speed read / write operations compared to hard disk drives. And since SSDs can reduce errors caused by latency and mechanical friction, the SSD has the advantage of improving the reliability of read / write operations. In addition, since it generates little heat and noise during operation and is strong against external shocks, it is highly regarded as a data storage device suitable for a portable device compared to a conventional hard disk drive.

An object of the present invention is to provide a data storage device and a read command processing method thereof that can improve read performance.

In accordance with an aspect of the present invention, a data storage device includes: a plurality of memories electrically connected to a plurality of channels; And a controller for queuing a plurality of commands to be performed in the plurality of memories, wherein the controller is further configured to transmit data of a first read command currently being executed for each of the plurality of channels based on the queued commands. The data sensing section of the second read command to be performed after the first command is performed during the section.

In the present embodiment, the data sensing section of the second read command overlaps with at least a portion of the data transmission section of the first read command.

In the present embodiment, the data detection section of the second read command is started immediately before the data transmission section of the first read command is started.

In the present exemplary embodiment, the first read command and the second read command may be performed in different flash memories connected to any one of the plurality of channels.

In this embodiment, the controller is characterized in that for queuing the plurality of commands using any one of the Native Command Queuing (NCQ), and Tagged Command Queuing (TCQ).

In this embodiment, the controller supports at least one of a Serial AT Attachment (SATA) interface, a Small Computer System Interface (SCSI) interface, and a Serial Attached SCSI (SAS) interface to queue the plurality of commands. It features.

In the present exemplary embodiment, the plurality of memories may be any one of a nonvolatile memory and a volatile memory.

In order to achieve the above object, a method of processing a plurality of read commands in each channel provided in the data storage device according to the present invention comprises the steps of: sensing data stored in the first flash memory in response to the first read command; And transmitting the sensed data to a controller, wherein the data stored in the second flash memory is sensed in response to a second read command to be performed after the first read command while the sensed data is transmitted to the controller. Characterized in that.

In the present embodiment, the first read command and the second read command may be one of a native command queuing (NCQ) and a tagged command queuing (TCQ) scheme before the first read command and the second read command are executed. It is characterized by being queued using either.

In this embodiment, the section for detecting the data stored in the second flash memory, characterized in that overlapping with at least a portion of the section for transmitting the data detected from the first flash memory.

In this embodiment, the sensing of the data stored in the second flash memory is characterized in that it starts just before the step of transmitting the sensed data from the first flash memory.

In the present exemplary embodiment, the first read command and the second read command may be performed in different flash memories connected to any one of a plurality of channels.

In order to achieve the above object, a method of processing a plurality of read commands in each channel provided in the data storage device according to the present invention comprises: determining whether a data sensing operation corresponding to a first read command is performed; Sensing data from a first memory designated by the first read command when a data sensing operation corresponding to the first read command is not performed; Determining whether a second command to be executed after the first read command is queued; If the second command is queued, sensing data from a second memory designated by the second read command; And transmitting data sensed from the first memory to the controller while data is detected from the second memory.

In order to achieve the above object, a computing system according to the present invention includes a host; And a data storage device for writing or reading data in response to a plurality of commands in response to a request of the host, wherein the data storage device comprises: a plurality of memories electrically connected to the plurality of channels; And queuing the plurality of commands, and based on the queued commands, of a second read command to be performed after the first command during a data transfer interval of a first read command currently being performed for each of the plurality of channels. And a controller for controlling the data sensing section to be performed.

In order to achieve the above object, a storage medium capable of recording and reading a method of processing a plurality of read commands in each channel included in the data storage device of the present invention is stored in the first flash memory in response to the first read command. Sensing data; And transmitting the sensed data to a controller, wherein the data stored in the second flash memory is sensed in response to a second read command to be performed after the first read command while the sensed data is transmitted to the controller. The method comprising the step of recording to a program for executing in a computer and characterized in that the computer readable.

According to the present invention as described above, the execution time for a plurality of read commands that are continuously executed is shortened, and the read performance of the data storage device is improved.

Exemplary embodiments of the invention will be described in detail below on the basis of reference drawings. However, the circuit configuration and operation of the data storage device of the present invention to be described below are merely described, for example, and various changes and modifications may be made without departing from the technical spirit of the present invention.

As the data storage device of the present invention, an SSD employing a flash memory as a main storage among semiconductor memories will be exemplarily described. The data storage device (e.g., SSD) of the present invention detects data stored in another flash memory in response to a read command to be performed next while data sensed by a currently executed read command is transferred from the flash memory to the controller. To perform the operation. According to such a configuration, since the data sensing operation of the next read command to be performed can be performed in advance while the current read command is performed, the execution time of the read command is effectively shortened.

1 is a block diagram illustrating a configuration of a data storage device 500 and a memory system 1000 including the data storage device 500 according to the present invention.

Referring to FIG. 1, the memory system 1000 may include a data storage device 500 and a host 900. The data storage device 500 may include a controller 100 and a data storage unit 300.

In FIG. 1, an SSD employing a semiconductor memory as a main storage will be exemplarily described as a data storage device 500. Although not shown in FIG. 1, the data storage device 500 temporarily stores data transmitted and received between the controller 100 and the data storage unit 300 and data transmitted and received between the controller 100 and the host 900. It can have a buffer memory that can be stored as. A buffer memory control function may be provided inside the controller 100 to control data input and output of the buffer memory. This means that the data input / output operation of the buffer memory can be performed through the controller 100. The buffer memory may be provided outside the controller 100 or may be provided inside the controller 100. The buffer memory may be configured as a randomly accessible memory such as DRAM or SRAM.

The data storage unit 300 is data main storage of the data storage device 500 and stores data using semiconductor memory chips instead of a platter of a hard disk drive (HDD). The data storage unit 300 may be configured as a nonvolatile memory or a volatile memory, and a plurality of channels (eg, N) may be configured between the controller 100 and the data storage unit 300.

In the present invention, a case in which the data storage unit 300 is composed of a flash memory which is a nonvolatile memory will be described. However, in the present invention, the memory applied to the data storage unit 300 may be configured in various forms without being limited to a specific kind and a specific form. For example, the memory applied to the data storage unit 300 may include not only flash memory but also nonvolatile memory such as MRAM and PRAM. In addition, the memory applied to the data storage unit 300 may include a volatile memory such as DRAM. The data storage unit 300 may be configured by mixing at least one nonvolatile memory and at least one volatile memory, or may be configured by mixing at least two types of nonvolatile memories.

In addition, the number of data bits stored in each memory cell of the flash memories included in the data storage unit 300 may be configured in various forms. For example, flash memories may consist of single-level flash memory cells in which one bit of data is stored per cell, or may consist of multi-level flash memory cells in which a plurality of bits of data are stored per cell. The type of memory cells constituting the flash memories may also be configured in various forms. For example, the flash memories may be composed of at least one of NAND flash memory, NOR flash memory, One_NAND flash memory (where the flash memory core and the memory control logic are implemented in a single chip), At least two kinds of flash memories may be configured in a hybrid form. In addition, the structure of the charge storage layer of the memory cell of the flash memories may also be configured in various forms. For example, the charge storage layer of the memory cell may be made of conductive polycrystalline silicon or the like, or may be formed using an insulating film such as Si 3 N 4, Al 2 O 3, HfAlO, HfSiO, or the like. A flash memory structure using an insulating film such as Si 3 N 4, Al 2 O 3, HfAlO, HfSiO, or the like as a charge storage layer is also referred to as a charge trap type flash (“CTF”) memory.

The controller 100 controls an operation of writing / reading data to / from the data storage unit 300 in response to a command input from the host 900. The controller 100 controls overall operations of the SSD, also referred to as SSD controller. The controller 100 may include one or more CPUs or cores for controlling the operation of the controller 100. A case where one CPU or core is provided is called a single core processor, and a case where a plurality of CPUs or cores is provided is called a multi-core processor. The control algorithm executed in the CPU or core may be stored in the form of firmware in the controller 100.

 The controller 100 of the present invention is capable of queuing a plurality of commands to be executed in the data storage unit 300, and each operation section of the queued commands (in particular, a read section of the read command and a data transmission section). Function to control. As a function of queuing a plurality of commands to be performed, native command queuing (NCQ), tagged command queuing (TCQ), or the like may be used.

The controller 100 may include a universal serial bus (USB), a MultiMediaCard (MMC) interface, a PCIExpress (PCI-E) interface, a serial AT attachment (SATA), a parallel AT attachment (PATA), a small computer system interface (SSC), and a SAS ( Data may be exchanged with the host 900 through one of a variety of interface protocols such as Serial Attached SCSI (ESC), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) interface. In particular, the controller 100 of the present invention may be configured to support any one of a SATA interface, a SCSI interface, a SAS interface, and corresponding interfaces to provide a queuing function for a plurality of commands.

As will be described in detail below, the controller 100 of the present invention controls the data sensing operation of the next read command to be performed in advance during the data transmission interval of the currently executing read command based on the information of the queued commands. do. As a result, the data sensing operation of the next read command to be performed can be performed in advance while the current read command is performed, thereby reducing the execution time of the read command. This means that the read performance of the data storage device 500 is improved.

The data sensing section tR refers to a section for sensing data stored in the flash memory using the page buffer. Data sensed in the data detection period tR is stored in a data storage unit (eg, an IO buffer inside the flash memory) inside the flash memory. The data transfer section (see tDMA) refers to a section in which data sensed in the flash memory is transmitted from the flash memory to the controller 100. In the data transmission period (see tDMA), data transmission by a direct memory access (DMA) transmission method may be performed. The DMA transfer scheme refers to a scheme in which flash memories and a buffer memory on the controller 100 directly transfer data without passing through a CPU bus inside the controller 100. Data transmitted to the controller 100 during the data transmission period (see tDMA) is stored in the buffer memory.

The method of performing a read command of the present invention may be applied to a case in which a single CPU or a single core is provided in the controller 100, or may be applied to a case in which multiple CPUs or multi-cores are provided in the controller 100. In addition, the method of performing a read command of the present invention may be applied to a plurality of ways provided in different channels, and may be applied to a plurality of ways provided in the same channel. As will be described in detail below, in the method of performing a read command of the present invention, when a read command is continuously performed in a plurality of ways belonging to the same channel, data transmission efficiency for the corresponding channel can be further improved.

FIG. 2 is a diagram illustrating a configuration of a channel and a way of the data storage unit 300 shown in FIG. 1.

Referring to FIG. 2, a plurality of channels (for example, N) may be configured between the controller 100 and the data storage unit 300. A plurality of flash memories 310, 320, and 330 may be electrically connected to each channel CH0, CH1,..., CH (N-1). Each channel CH0 to CH (N-1) represents an independent bus capable of transmitting and receiving commands and data to corresponding flash memories. Flash memories 310, 320, and 330 connected to different channels CH0, CH1,..., And CH (N-1) may operate independently.

The plurality of flash memories 310, 320, and 330 connected to each channel may constitute a plurality of ways (way0-way3). For example, the flash memories 310 may constitute four ways (way0 to way3) in channel 0 (CH0), and the flash memories of 320 are 4 ways in channel 1 (CH0). Can be constituted by way0 to way3. In addition, the flash memories 330 may configure four ways way0 to way3 in channel (N-1) CH (N-1). A way is a unit for distinguishing flash memory chips that share one channel. Each flash memory chip may be identified according to a channel number corresponding to each flash memory chip and a way number corresponding to each flash memory chip. For example, the flash memory chip corresponding to the first wayway1 of the zeroth channel CH0 represents "Chip N". The flash memory chip corresponding to the 3rd way3 of the 1st channel CH1 represents "Chip (3N + 1)". Whether a command provided from a host is performed on a flash memory chip of which channel of a channel may be determined by a logical block address (LBA) transmitted from the host 900.

3 is a flowchart illustrating a read command processing method according to the present invention.

3 exemplarily shows a procedure when processing one read command.

Referring to FIG. 3, the method of processing a read command according to the present invention first determines whether a command or a control signal for executing a data sensing interval tR of a read command to be currently performed has previously been issued ( S1000 step).

As a result of the determination in step S1000, if a command or a control signal for executing the data sensing section tR of the read command to be performed currently has not been previously issued, the controller 100 may detect the data sensing section of the read command to be performed ( A command or control signal for executing tR) is issued to the flash memory (step S1100). If a command or a control signal for executing the data sensing interval tR of the read command to be currently executed has not been previously issued, it means that the current read command is the first read command among a plurality of consecutive read commands. In response to the command or control signal issued in step S1100, data is sensed from the flash memory of the channel and way specified by the current read command. The sensing operation of the flash memory is performed by a page buffer provided in the flash memory. Data sensed from the flash memory is stored in a data storage unit (eg, an IO buffer) provided in the corresponding flash memory. Subsequently, it is determined whether a read command to be performed next is queued to the controller 100 (step S1200). The queuing function for the commands to be performed next may be performed by a command queuing scheme such as NCQ, TCQ, and the like.

On the other hand, if it is determined in step S1000 that a command or a control signal for executing the data sensing interval tR of the read command to be currently executed is previously issued, the procedure proceeds to step S1200 and the next read command to be executed is a controller. It is determined whether or not it is queued at 100. If a command or a control signal for executing the data sensing interval tR of the read command to be currently executed is previously issued, it means that the current read command is not the first read command among a plurality of consecutive read commands.

Subsequently, if the read command to be performed next is queued in the controller 100 as a result of the determination in step S1200, the controller 100 may execute a command for executing a data sensing interval tR of the read command to be performed next, or The control signal is issued (step S1300). In response to the command or control signal issued in step S1300, data is sensed from the flash memory of the channel and the way specified by the read command to be performed next. The detected data is stored in the data storage unit in the corresponding flash memory. After the command or control signal for executing the data detection section tR of the next read command is issued in step S1300, the controller 100 executes the command or control signal for executing the data transfer section tDMA of the current read command. Issue (step S1400).

If the read command to be performed next is not queued as a result of the determination in step S1200, the controller 100 proceeds to step S1400 and executes a data transfer period tDMA corresponding to the current read command. In the data transfer period tDMA, data sensed in the flash memory by the current read command is provided to the controller 100 by the DMA transfer method. Data provided to the controller 100 is stored in the buffer memory.

In FIG. 3, only data sensing and data transfer operations performed between the flash memory and the controller 100 are illustrated, and data transfer operations between the controller 100 and the host 900 are not illustrated. Although not shown in FIG. 3, the data sent to the controller 100 by the read command will ultimately be provided as read data to the host 900.

The read command processing method according to the embodiment of the present invention described above may be independently performed for each channel. In the present invention, when processing a plurality of queued read commands, first, the plurality of read commands may be processed in parallel on a channel basis. In this case, by applying the read command processing method shown in FIG. 3 to each channel, the execution time of the read commands continuously executed on the same channel is shortened and the data transmission efficiency for each channel is maximized. The larger the number of read commands assigned to each channel, the better the increase in read efficiency according to the present invention will be.

4 is a timing diagram illustrating a read command processing method according to the present invention. 4 illustrates a timing diagram when four read commands CMD0, CMD1, CMD2, and CMD3 are successively performed on four ways included in the same channel. Read commands executed in succession may refer to commands queued by the NCQ method or the corresponding command queuing method.

Referring to FIG. 4, after the data sensing section tR of the first command CMD0 is performed, the data sensing section tR of the second command CMD1 starts to be performed. When it is confirmed that the data detection section tR of the second command CMD1 starts to be performed, the data transmission section tDMA0 of the first command CMD0 starts to be performed. When the data transmission section tDMA0 of the first command CMD0 ends, the data detection section tR of the third command CMD2 starts to be performed. When it is confirmed that the data detection section tR of the third command CMD2 starts to be performed, the data transmission section tDMA1 of the second command CMD1 starts to be performed. When the data transmission section tDMA1 of the second command CMD1 ends, the data detection section tR of the fourth command CMD3 starts to be performed. When it is confirmed that the data detection section tR of the fourth command CMD3 starts to be performed, the data transmission section tDMA2 of the third command CMD2 starts to be performed. When the data transfer section tDMA2 of the third command CMD2 ends, the data transfer section tDMA3 of the fourth command CMD3 starts to be performed.

That is, when four read commands CMD0 to CMD3 are sequentially performed on four ways included in the same channel, at least one data sensing interval tR and at least one data transmission interval tDMA0 to tDMA3 may be used. It can be seen that some or all overlap each other. In this case, the time point at which the overlapping data sensing section tR and the data transmission section tDMA0 to tDMA3 starts is slightly earlier or substantially the same as the start time point of the data transmission section tDMA0 to tDMA3 to which tR corresponds. The start and end time points of the data detection section tR and the data transmission section tDMA0 to tDMA3 for the plurality of read commands CMD0 to CMD3 have the same control functions as the controller 100 or the controller 100. It can be variously adjusted by various kinds of control agents.

As described above, when the data storage device 500 of the present invention processes a plurality of queued read commands, first, the plurality of read commands are processed in parallel in units of channels. At this time, by applying the read command processing method shown in Figs. 3 and 4 for each channel, the execution time of the read commands that are continuously performed on the same channel is shortened. As a result, the processing efficiency of the read command and the data transmission efficiency for each channel are maximized.

5 illustrates a configuration of a computing system 2000 according to the present invention.

Referring to FIG. 5, the computing system 2000 according to the present invention includes a controller 100, a microprocessor 200, a data storage unit 300, and a baseband chipset electrically connected through a bus. Modem 600, and user interface 800.

The controller 100 and the data storage unit 300 illustrated in FIG. 5 constitute a data storage device 500. The data storage device 500 may configure the SSD or the memory card and / or the memory card system illustrated in FIGS. 1 and 2. Detailed configurations of the controller 100 and the data storage unit 300 illustrated in FIG. 5 are substantially the same as those described above. Therefore, the same reference numerals will be used for the same configuration, and redundant description will be omitted below.

In the data storage 300, N-bit data (N is an integer greater than or equal to 1) to be processed / processed by the microprocessor 200 is stored through the controller 100. The data storage unit 300 may be configured as a nonvolatile memory supporting a plurality of channels and a plurality of ways, and may be preferably configured as a flash memory among the nonvolatile memories. However, this is an example to which the present invention is applied. In addition to the flash memory, other types of nonvolatile memory devices may be applied to the present invention. In addition, the data storage unit 300 may be configured as a volatile memory as well as a nonvolatile memory.

The controller 100 controls a read / write / erase operation of the data storage unit 300. During the read operation, the controller 100 simultaneously performs the data sensing section of the next read command to be performed during the data transmission section of the currently executing read command. That is, the data sensing operation of the next read command to be performed is performed in advance while the current command is executed. As a result, the execution time of the read command is effectively shortened.

When the computing system 2000 according to the present invention is a mobile device, a battery 700 for supplying an operating voltage of the computing system 2000 may be additionally provided. Although not shown in the drawings, the computing system 2000 according to the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, or the like. Recently, data storage units using heterogeneous nonvolatile memories have been installed in the notebook, desktop, and server markets. In such a market situation, the present invention may greatly improve the performance limitations that existed earlier, thereby accelerating the expansion of the base of the data storage unit using the nonvolatile memory.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

In addition, the present invention can also be embodied as computer readable code on a computer readable storage medium. The computer-readable storage medium includes all kinds of recording devices in which data that can be read by a computer system is stored. Examples of computer-readable storage media include ROM, RAM, CD-ROM, magnetic tape, floppy disk, hard disk, optical data storage, SSD, etc. Also, carrier wave (for example, transmission over the Internet) It also includes the implementation in the form of. The computer readable storage medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion.

1 is a block diagram showing the configuration of a data storage device and a memory system including the same according to the present invention.

FIG. 2 is a diagram illustrating a configuration of a channel and a way of the data storage unit illustrated in FIG. 1.

3 is a flowchart illustrating a read command processing method according to the present invention.

4 is a timing diagram illustrating a read command processing method according to the present invention.

5 illustrates a configuration of a computing system according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: controller 300: data storage

500: data storage device 900: host

Claims (15)

A plurality of memories electrically connected to the plurality of channels; And A controller for queuing a plurality of commands to be performed in the plurality of memories, The controller performs a data sensing interval of a second read command to be performed after the first command during a data transmission interval of a first read command currently being executed for each of the plurality of channels based on the queued commands. Data storage device that controls it. The method of claim 1, And the data sensing section of the second read command overlaps at least a portion of the data transfer section of the first read command. The method of claim 1, And the data sensing section of the second read command starts just before the data transmission section of the first read command begins. The method of claim 1, And the first read command and the second read command are performed in different flash memories connected to any one of the plurality of channels. The method of claim 1, The controller is configured to queue the plurality of commands using any one of a Native Command Queuing (NCQ) and a Tagged Command Queuing (TCQ) scheme. The method of claim 1, The controller supports at least one of a Serial AT Attachment (SATA) interface, a Small Computer System Interface (SCSI) interface, and a Serial Attached SCSI (SAS) interface to queue the plurality of commands. The method of claim 1, And the plurality of memories are any one of a nonvolatile memory and a volatile memory. In the method for processing a plurality of read commands in each channel provided in the data storage device: Sensing data stored in the first flash memory in response to the first read command; And Transmitting the sensed data to a controller, And detecting data stored in a second flash memory in response to a second read command to be performed after the first read command while the sensed data is transmitted to a controller. The method of claim 8, The first read command and the second read command are queued using any one of a native command queuing (NCQ) and a tagged command queuing (TCQ) method before the first read command and the second read command are executed. How to handle read commands on data storage devices. The method of claim 8, And a section for detecting data stored in the second flash memory overlaps at least a portion of a section for transmitting the detected data from the first flash memory. The method of claim 8, The detecting of the data stored in the second flash memory may include starting the data immediately before the step of transmitting the detected data from the first flash memory. The method of claim 8, And the first read command and the second read command are performed in different flash memories connected to any one of a plurality of channels. In the method for processing a plurality of read commands in each channel provided in the data storage device: Determining whether a data sensing operation corresponding to the first read command is performed; Sensing data from a first memory designated by the first read command when a data sensing operation corresponding to the first read command is not performed; Determining whether a second command to be executed after the first read command is queued; If the second command is queued, sensing data from a second memory designated by the second read command; And And transmitting data sensed from the first memory to a controller while data is detected from the second memory. Host; And A data storage device for recording or reading data in response to a plurality of commands in response to a request of the host; The data storage device, A plurality of memories electrically connected to the plurality of channels; And Queuing the plurality of commands and based on the queued commands, data of a second read command to be performed after the first command during a data transmission interval of a first read command currently being performed for each of the plurality of channels. Computing system including a controller for controlling the detection interval to be performed. A storage medium capable of recording and reading a method of processing a plurality of read commands in each channel of a data storage device, the method comprising: Sensing data stored in the first flash memory in response to the first read command; And Transmitting the sensed data to a controller, Sensing the data stored in the second flash memory in response to a second read command to be performed after the first read command while the sensed data is transferred to the controller, the method being written into a program for executing on a computer. And computer-readable storage media.

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