KR20100118056A - The apparatus for frequency selective digital transmission - Google Patents

Abstract

PURPOSE: A digital transmission device which selectively selects frequency is provided to select symbol rate which differs according to varying application and one among high performance mode, general mode, and low power mode according to the use clock and selects one among low speed spectrum methods of excellent transmission performance in each mode, thereby providing high quality. CONSTITUTION: A preamble transmission processor(211) generate preamble for frame synchronization. A header transmission processor(213,214) comprises a header including data property information. A data transmission processor(215,216,217) diffuses the transmission data to frequency selective spectrum code after serial-parallel converting about transmission data. A multiplexer(218) performs multiplex of each diffuse preamble, header and data.

Description

Frequency Selective Digital Transmitter {THE APPARATUS FOR FREQUENCY SELECTIVE DIGITAL TRANSMISSION}

The present invention relates to a frequency selective digital transmission apparatus, and more particularly, to avoid a frequency band in which noise power around a human body is concentrated compared to other bands, and the human body acts as a waveguide to radiate the intensity of a transmitted signal to the outside of the human body. A frequency selective digital transmitter using a frequency selective spreading code to use a limited frequency band up to a frequency band larger than the signal strength, which is a high performance mode or a normal mode depending on a symbol rate and a clock used according to various applications. Select one of the two modes, the low power spreading method and the low power spreading method. It is about technology to do.

The present invention is derived from a study conducted as part of the IT source technology development project of the Ministry of Knowledge Economy [Task Management Number: 2006-S-072-04, Task name: Human Communication Controller SoC].

Patent No. 829865, filed in 2006, filed by the present inventors, and registered in 2008, uses a restricted passband from 5 MHz band to 40 MHz band to implement a human body communication system. The present invention discloses a human body communication system and method for performing scrambling, channel coding, interleaving, spreading, etc. using unique user identification information (ID).

In addition, Patent Application No. 2007-0087869, "Modulation and Demodulation Method Using Frequency Selective Baseband," filed in 2007, deals with the entire system using serial-to-parallel conversion, frequency selective baseband transmission, and a limited number of spreading codes. A frequency selective multiplexing scheme is disclosed that can improve the gain and increase the transmission data rate.

However, in the related art, there is no technique for optimizing a frequency selective digital transmitter in consideration of a clock speed, a frequency band, a maximum data rate, and a power consumption suitable for each application in a human body communication system performing various applications.

Accordingly, the present invention is to solve the problems of the prior art as described above, and select one of the high performance mode, the normal mode, and the low power mode according to the symbol rate and the clock used according to various applications, and transmit data in each mode. The present invention provides a frequency selective digital transmission apparatus which can select and use either a high speed diffusion method using a multi-frequency frequency selective spreader having high efficiency and a low speed diffusion method having better transmission performance than transmission efficiency.

According to an aspect of the present invention, there is provided a frequency selective digital transmission apparatus comprising: preamble transmission processing means for generating a frame synchronization preamble and spreading the signal with a predetermined spreading code; Header transmission processing means for constructing a header including data attribute information and spreading the header with a predetermined spreading code; Data transmission processing means for performing a serial-to-parallel conversion on the transmission data according to the selected transmission mode and spreading method and then spreading the spreading signal with a frequency selective spreading code; And multiplexing means for multiplexing the preamble, header, and data spread by the preamble transmission processing means, the header transmission processing means, and the data transmission processing means, respectively, and transmitting them as digital signals.

According to the present invention, a high-speed mode using a multi-structure frequency selective spreader that selects one of a high performance mode, a normal mode, and a low power mode according to a symbol rate and a clock used according to various applications, and improves data transmission efficiency in each mode. By selecting one of the low-speed spreading methods that have better transmission performance than the spreading method and the transmission efficiency, it is possible to provide a human body communication system that is optimized for each application to provide higher quality and operate at lower power. .

1 is a block diagram of a transceiver for human body communication according to an embodiment of the present invention;
2 is a diagram illustrating a subgroup structure of a 64-bit Walsh code according to an embodiment of the present invention;
3A and 3B illustrate a frequency selection method according to an embodiment of the present invention;
4 is a structural diagram of a frequency selective spreader according to an embodiment of the present invention;
5 is a structural diagram of a sub-frequency selective spreader according to an embodiment of the present invention;
6 is a subgroup configuration diagram of a 32-bit Walsh code used in a high performance mode according to an embodiment of the present invention;
7 is a structural diagram of a frequency selective spreader in a high performance mode according to an embodiment of the present invention, and
8 is a structural diagram of a sub-frequency selective spreader in a high performance mode according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. However, in describing the preferred embodiment of the present invention in detail, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, the same reference numerals are used throughout the drawings for parts having similar functions and functions.

In addition, in the entire specification, when a part is referred to as being 'connected' to another part, it may be referred to as 'indirectly connected' not only with 'directly connected' . Also, to "include" an element means that it may include other elements, rather than excluding other elements, unless specifically stated otherwise.

Also, for convenience of description of the present invention, a 64-bit Walsh code is used as a spreading code having a dominant frequency, a 64 MHz clock and a symbol rate of 2 Msps in a high performance mode, a 64 MHz clock and a symbol rate of 1 Msps in a normal mode, In low power mode, it is assumed that a 32 MHz clock and symbol rate of 0.5 Msps are used. However, the Walsh code and the clock and symbol rate used in each mode are not limited thereto.

The transmission device proposed by the present invention uses Frequency Selective Digital Transmission (FSDT). In the frequency selective digital transmission technique, data is spread in the frequency domain using a frequency selective spreading code and transmitted in digital form. In addition, the dominant frequency in which most transmission signals are distributed has a feature that can be selected by using a specific frequency selective spreading code.

1 is a block diagram of a transceiver for human body communication according to an embodiment of the present invention.

As shown in FIG. 1, the transceiver for a human body communication is largely a human body medium access control (MAC) 100, a human body communication physical layer modem 200, a human body communication front end (AFE) 300, and a signal electrode 400. It is composed of

The human body MAC 100 includes a MAC transmitter processor 110 and a MAC receiver processor 120. The MAC transmission processor 110 processes the transmission data and data attribute information received from the upper layer and transmits the data to the transmitter 210 of the human body physical layer modem 200, and the MAC reception processor 120 transmits the human body physical layer modem. It receives and processes the received data and data attribute information from the receiver 220 of 200 and delivers it to a higher layer.

The human body physical layer modem 200 includes a transmitter 210 and a receiver 220.

The transmitter 210 includes a preamble generator 211 and a first spreader 212 for preamble transmission processing, a header generator 213 and a second spreader 214 for header transmission processing, and a data generator 215 for data transmission processing. ), A serial-to-parallel converter (S2P) 216, a frequency selective spreader 217, and a multiplexer 218 to multiplex the processed preambles, headers, and data.

The preamble generator 211 is set to a predefined initial value to generate a preamble for frame synchronization of a predetermined length, and the generated preamble is input to the first spreader 212 and spread with a predetermined spread code.

The header generator 213 receives data attribute information of transmission data, for example, a transmission speed, a modulation scheme, a frequency band, and a data length, from the MAC transmission processor 110 of the human body MAC 100, and determines a predetermined bit. The header has a number and configures a header including a header header check sequence (HCS), and the configured header is input to the second spreader 214 to be spread with a predetermined spreading code.

The data generator 215 receives the transmission data from the MAC transmission processor 110 of the human body MAC 100 and outputs data at a desired time, and performs data control processing and data HCS generation for variable data transmission.

The S2P 216 receives the data output from the data generator 215 and performs N-bit serial-to-parallel conversion. As a result of the serial-to-parallel conversion, the frequency band used is reduced to 1 / N, which allows more data to be transmitted within the same frequency band or higher quality data by using larger spreading code gains within the same frequency band. It has the advantage of being able to transmit. In addition, the S2P 216 may be optimized for various applications by operating at different clocks and symbol rates according to a transmission mode selected from a high performance mode, a normal mode, and a low power mode.

The frequency selective spreader 217 receives N bits that are outputs of the S2P 216 in parallel and outputs a frequency selective spreading code. In addition, the frequency selective spreader 217 may select a fast spread method or a slow spread method in each mode. The structure and function of the frequency selective spreader 217 will be described in detail with reference to FIGS. 4, 5, 7 and 8.

The multiplexer 218 outputs preambles, headers, and data spread by the first spreader 212, the second spreader 214, and the frequency selective spreader 217, respectively.

In the present invention, the use of the frequency selective spreader 217 enables digital transmission using the desired frequency band. In addition, the output of the multiplexer 218 is capable of digital direct transmission in one bit. Accordingly, the output signal of the transmitter 210 may be input to the signal electrode 400 through the transmit / receive switch 310 without being processed by a separate analog transmitter such as a digital-analog converter, an intermediate frequency converter, and transmitted into the human body. have.

In Fig. 1, a header generator 213 and a second spreader 214, which are header transmission processing means, a data generator 215, a serial-to-parallel converter (S2P) 216, and a frequency selective spreader 217, which are data transmission processing means. ) Are separately shown, the header transmission processing means and the data transmission processing means may be integrated into one and implemented as one header / data transmission processing means. In this case, the header / data transmission processing means comprises a header / data generator, an S2P and a frequency selective spreader. The header / data generator performs both the functions of the header generator 213 and the data generator 215 described above, and its output is sequentially input to the S2P and the frequency selective spreader so that the header and the data can be transmitted together by the frequency selective spreading scheme. Can be.

Meanwhile, the receiver 220 performs the inverse function of the transmitter 210 described above, and includes a demultiplexer 221, a despreader 222, a header processor 223, a frequency selective despreader 224, and a parallel-serial converter. (P2S) 225, a data processor 226, a frame synchronizer 227 and a common control signal generator 228, the operation of receiving and processing signals from the human body communication AFE (300) is as follows. Is the same as

The received signal input through the signal electrode 400 passes through the noise / reduction filter 320 for removing the noise added during transmission in the human body through the transmission / reception switch 310, and then the desired size by the amplifier 330. Is amplified by the signal. The amplified received signal is input to the Clock Recovery & Data Retiming (hereinafter referred to as " CDR ") 340 to compensate for timing synchronization and frequency offset with the receiver clock. The received signal and the clock whose timing synchronization and frequency offset are compensated for the output of the CDR 340 are input to the receiver 220 of the human body physical layer modem 200. In this case, the CDR 340 outputs a 64 MHz clock when the selected transmission mode is a high performance mode or a normal mode, and outputs a 32 MHz clock divided by 64 MHz in the low power mode.

First, a received signal input to the receiver 220 before frame synchronization is input to the frame synchronizer 227 to perform frame synchronization using a preamble.

When frame synchronization is obtained by the frame synchronizer 227, the demultiplexer 221 separates and outputs a header portion and a data portion among the received signals.

The header portion output from the demultiplexer 221 is input to the header processor 223 via the despreader 222, and the header processor 223 inspects the HCS included in the header and retrieves data attribute information of the received data from the header. Extract it and send it to the MAC processor 120.

The data portion output from the demultiplexer 221 is input to the frequency selective despreader 224. The frequency selective despreader 224 calculates a correlation value and then transmits the data having the largest correlation value according to the selected transmission mode. Output in bits. The N bits output from the frequency selective despreader 224 are input to the P2S 225, converted into serial, and then input to the data processor 226. The data processor 226 performs a data HCS check and then performs a MAC reception processor. Send to 120.

In addition, when the header transmission processing means and the data transmission processing means are integrated in the transmitter 210 so that the header and the data are transmitted together by the frequency selective spreading method, the receiver 220 similarly means for processing the header and the data. Integrated implementation with optional despreader, P2S and header / data processor ensures that header and data are processed together by frequency selective despreading.

2 is a diagram illustrating a subgroup configuration of a 64-bit Walsh code according to an embodiment of the present invention.

The 64 Walsh codes from W ₀ to W ₆₃ are divided into exactly 64 frequency bands so that the most predominant frequency fd of each Walsh code is sequentially mapped to the divided frequencies.

In this embodiment, 64 Walsh codes are used as the spreading codes, which are grouped by 8 and divided into 8 subgroups. As a result of measuring noise characteristics around the human body, only the top four subgroups are used to avoid low frequency bands in which noise power is concentrated compared to other bands. Subgroup 4 (SGN = "100") used is W ₃₂ ~ W ₃₉ , subgroup 5 (SGN = "101") is W ₄₀ ~ W ₄₇ , subgroup 6 (SGN = "110") is W ₄₈ ~ W ₅₅ , and subgroup 7 (SGN = "111") is It is defined as W ₅₆ ~ W ₆₃ . The SGN value for each subgroup represents a subgroup number as a binary value of 3 bits and is used in the frequency selective spreader. However, the number of spreading codes and subgroups used is not limited thereto, and a total of 2 ^N spreading codes (N is a real number) is divided into 2 ^M (M is a real number, M <N) to generate a subgroup. P (P is real) subgroups can be adopted and used.

3A and 3B are diagrams illustrating a frequency selection method according to an embodiment of the present invention.

According to an embodiment of the present invention, in the fast frequency selective spreader using the fast spreading method, three of four subgroups are selected and used as shown in FIG. 3A, and the slow frequency selective spreader using the slow spreading method is shown in FIG. As shown in 3b, two of four subgroups are selected and used. In addition, a 4-bit frequency band control bit BAND_SEL is used to select the subgroup to be used.

Specifically, in the case of the fast frequency selective spreader, BAND_SEL has four values of "0111", "1011", "1101", and "1110". In addition, in the case of the slow frequency selective spreader, BAND_SEL has six values of "0011", "0101", "0110", "1001", "1010", and "1100". In this case, when each bit value of the BAND_SEL is '0', the corresponding subgroup is not selected, and when '1', the corresponding subgroup is selected. In other words, when BAND_SEL is "0111" in the fast frequency selective spreader, subgroup 5 (SGN = "101"), subgroup 6 (SGN = 110), and subgroup 7 (SGN = 111) shown in FIG. &Quot;) is selected, and subgroup 6 (SGN = " 110 &quot;) and subgroup 7 (SGN = " 111 &quot;) are selected if BAND_SEL is " 0011 " in the slow frequency selective spreader.

4 is a structural diagram of a frequency selective spreader according to an embodiment of the present invention.

As shown in FIG. 4, the frequency selective spreader 217 uses a fast frequency selective spreader 500 using a fast spread method to increase data transmission efficiency, and uses a slow spread method to provide better transmission performance than the data transmission efficiency. And a multiplexer 700 for selecting and outputting any one of output values of the fast frequency selective diffuser 500 and the slow frequency selective diffuser 600 according to the selected spreading scheme.

In addition, the fast frequency selective spreader 500 includes sub frequency selective spreaders 1 to 3 (510, 520, 530) and a multi-value selector 540, and the slow frequency selective spreader 600 includes a sub frequency selective spreader 4 and 5 (610, 620) and a multiplexer (630).

The operation of the frequency selective spreader 217 according to the selected transmission mode (normal mode or low power mode) and spreading method (fast spreading method or slow spreading method) will be described in detail.

One) Normal mode (64 MHz  Clock, Symbol rate  One Msps ) And fast diffusion method

The S2P 216 converts the input serial data DIN into parallel data of P * (M + 1) bits and outputs it. Thereafter, the P sub-frequency selective spreaders 510, 520, and 530 belonging to the fast frequency selective spreader 500 of the frequency selective spreader 217 receive M + 1 data bits, respectively, and use the M data bits. A spreading code is obtained by selecting one spreading code among 2 ^M spreading codes in the subgroup, and XORing the remaining 1 bit of the M + 1 data bits to the selected value. That is, P spreading codes are obtained through the P sub-frequency selective spreaders 510, 520, and 530. Thereafter, the multivalue selector 540 selects a multiplicity value from the P spread codes acquired through the P sub-frequency selective spreaders 510, 520, and 530 to generate transmission data having a multiplicity value.

As a specific example, when BAND_SEL is designated as "0111", DIN, a signal input to the S2P 216, has a data rate of up to 12 Mbps, and is serial-parallel at a ratio of 1:12 by the S2P 216. The conversion is performed to output 12 bit parallel symbols of b11, b10, ..., b0 as 1Msps. The output parallel symbols are input to the fast frequency selective spreader 500 of the frequency selective spreader 217.

Since BAND_SEL is " 0111 ", subgroup 5 (SGN = "101"), subgroup 6 (SGN = "110") and subgroup 7 (SGN = "111") are selected, thereby subfrequency selective spreader 1 The SGN1 to SGN3 values in the to 3 become "101", "110", and "111", respectively.

Sub frequency selective spreader 1 (510) uses input bits b11, b10, b9, b8 and SGN1 values of "101", and uses eight bits of subgroup 5 (3) of b11, b10, b9 (W _40). W ₄₇ ), and outputs 64-bit A in the form of 1-bit string by XORing the selected value with b8.

Sub frequency selective spreader 2 (520) uses input bits b7, b6, b5, b4 and SGN2 values "110", and uses eight bits of sub-group 6 (3) of b7, b6, b5 (W _48). W ₅₅ ), and outputs the 64-bit (B) in the form of a 1-bit string by XORing the selected value with b4.

The sub-frequency selective spreader 3 (530) uses input bits b3, b2, b1, b0 and SGN3 values "111", and uses eight bits of the subgroup 7 (3) of b3, b2, b1 (W _56). W ₆₃ ), and outputs the 64-bit C in the form of a 1-bit string by XORing the selected value with b0.

The multi-value selector 540 receives a 3-bit string of A, B, and C output from the sub-frequency selective spreaders 1 to 3 (510, 520, and 530), selects a multi-value according to Equation 1, and selects the multi-value. Output the result value D. In Equation 1, 'or' represents an OR gate and 'and' represents an AND gate.

[Equation 1]

D = (A and B) or (B and C) or (C and A)

On the other hand, the Tx_RATE control bit of the multiplexer has a value of '0' when the fast spread method is selected and a value of '1' when the slow spread method is selected. In the present embodiment, the Tx_RATE control bit has a value of '0'. Accordingly, D, which is an output value of the fast frequency selective spreader 500, is selected and output to the output DOUT of the frequency selective spreader 217.

2) Normal mode (64 MHz  Clock, Symbol rate  One Msps ) And slow diffusion method

S2P 216 converts the input serial data DIN into parallel data of S + (M + 1) bits and outputs it. Thereafter, the Q sub-frequency selective spreaders 610 and 620 belonging to the low frequency selective spreader 600 of the frequency selective spreader 217 receive M + 1 data bits, respectively, and use the corresponding M sub-groups. in selecting a spreading code of 2 ^M of the spreading code, and to XOR the remaining one bit of the M + 1 number of data bits to a selected value to obtain a spread code. That is, Q spreading codes are obtained through the Q sub-frequency selective spreaders 610 and 620. Thereafter, the multiplexer 630 generates transmission data by selecting one spreading code using S bits among the input data bits in the Q spreading codes acquired through the Q sub-frequency selective spreaders 610 and 620.

As a specific example, when BAND_SEL is designated as "0011", DIN, a signal input to the S2P 216, has a data transfer rate of up to 5 Mbps, and is serial-parallel at a ratio of 1: 5 by the S2P 216. The conversion is performed to output 5-bit parallel symbols of b4, b3, ..., b0 as 1Msps. The output parallel symbols are input to the low frequency selective spreader 600 of the frequency selective spreader 217.

Since BAND_SEL is "0011", subgroup 6 (SGN = "110") and subgroup 7 (SGN = "111") are selected so that the SGN4 and SGN5 values at sub-frequency selective spreaders 4 and 5 are respectively " 110 "and" 111 ".

Sub-frequency selective spreader 4 (610) uses input bits b3, b2, b1, b0 and SGN4 values of "110", and uses eight bits of subgroup 6 (W ₄₈ ~) using three bits of b3, b2, b1. W ₅₅ ), and outputs 64 bits (F) in the form of a 1-bit string by XORing the selected value with b0.

In the sub-frequency selective spreader 5 620 input bits b3, b2, b1, using b0 and SGN5 value of "111" and, b3, b2, using three bits of b1 wilsi sign of the subgroups 78 (W ₅₆ ~ W ₆₃ ), and the selected value is XORed with b0 to output 64 bits (G) in the form of a 1-bit string.

The multiplexer 630 receives two bit strings of F and G output from the sub-frequency selective spreaders 4 and 5 (610 and 620), receives b4 of the output of the S2P 216, and b4 is '0'. In the case of '1', the output F of the sub frequency selective spreader 4 610 is selected and the output G of the sub frequency selective spreader 5 620 is selected and output to the output H of the low frequency selective spreader 600.

In the present embodiment, the Tx_RATE control bit has a value of '1', so H, which is an output value of the slow frequency selective spreader 600, is selected by the multiplexer 700 to output DOUT of the frequency selective spreader 217. Is output.

3) Low power mode (32 MHz  Clock, Symbol rate  0.5 Msps ) And fast diffusion method

When BAND_SEL is set to "0111", DIN, a signal input to the S2P 216, has a data transfer rate of up to 6 Mbps, and serial-to-parallel conversion is performed at a ratio of 1:12 by the S2P 216 to perform b11 and b10. 12-bit parallel symbols of ..., b0 are output at 0.5Msps. Subsequent operation of the frequency selective spreader is the same as the case where the normal mode and the fast spreading method are selected, and a detailed description thereof will be omitted.

4) Low power mode (32 MHz  Clock, Symbol rate  0.5 Msps ) And slow diffusion method

When BAND_SEL is designated as "0011", DIN, which is a signal input to the S2P 216, has a data transfer rate of up to 2.5 Mbps, and serial-to-parallel conversion is performed at a ratio of 1: 5 by the S2P 216, so that b4, 5-bit parallel symbols b3, ..., b0 are output at 0.5Msps. The operation of the frequency selective spreader thereafter is the same as in the case where the normal mode and the slow diffusion method are selected, and thus a detailed description thereof will be omitted.

5 is a structural diagram of a sub-frequency selective spreader according to an embodiment of the present invention.

As described above, assuming that the BAND_SEL value is "0111" when the general mode and the fast spreading scheme are selected, the sub-frequency selective spreader 1 510 performs subgroup 5 (SGN = 0) according to the input bits b11, b10, and b9. One of the eight Wilsh codes of " 101 ") is generated (64 bits), and this value and b8 are XORed so that 64 bits are sequentially output in a 1-bit string A. At this time, the SGN1 (s2, s1, s0) values used are "101" which is the SGN value of subgroup 5. FIG. In addition, when the low power mode and the high speed diffusion method are selected, except that the clock used is 32 MHz, 64 bits are generated in the same manner as in the normal mode, and output in a 1 bit string form.

Sub-frequency selective spreader 1 510 is comprised of a six-bit counter 511, six XOR logic circuits 512-1 through 512-5, 514 and six AND logic circuits 513-1 through 513-6. And 3 bits of frequency selection control bits (s2, s1, s0) and 4 bits of input bits (b11, b10, b9, b8).

The 6-bit counter 511 is reset to an initial value '0' every symbol period to count 0 to 63 in normal mode and low power mode.

One of the eight Walsh codes included in the subgroup is generated using the three-bit frequency selection control bits (s2, s1, s0) and three of the input bits (b11, b10, b9). The output signal A in the form of a 1-bit string is output by being XORed with the generated Walsh code.

Five XOR logic circuits 512-1 through 512-5 are for gray indexing. The six AND logic circuits 513-1 to 513-6 are C ₅ to C ₀ , which are outputs of the 6-bit counter 511, and s2 and five XOR logic circuits 512-1 to the most significant bits of the frequency selection control bit. The output bits of 512-5) are input respectively. In addition, one XOR logic circuit 514 is for XORing the outputs of the six AND logic circuits 513-1 to 513-6 and b8.

6 is a diagram illustrating a subgroup configuration of a 32-bit Walsh code used in a high performance mode according to an embodiment of the present invention.

In the high performance mode, the symbol rate input to the frequency selective spreader is 2 Mbps, which is twice the symbol rate of 1 Mbps in the normal mode. Therefore, in the high performance mode frequency selective spreader using the same clock, only 32 bits are spread out of the 64 bit Walsh codes included in the selected subgroup to match the symbol rate.

For example, if the 64-bit Walsh code is defined as Wn = [w0, w1, w2, ..., w63], the 32-bit Walsh code selected and used in the high performance mode is Whn1 = [w16, w17, ... , w47], Whn2 = [w32, w33, ..., w63], Whn3 = [w8, w9, ..., w23, w40, w41, ..., w55] and Whn4 = [w16, w17,. .., w31, w48, w49, ..., w63].

In the following description, it is assumed that 32 bits, ie, Whn1 = [w16, w17, ..., w47], which are located in the middle surrounded by solid lines as shown in FIG. That is, when the number of output bits of the Walsh code is N, it is assumed that N / 2 Walsh codes located in the middle of the N-bit Walsh code are used.

The characteristics of the selected 32-bit Wilsh code are 32 bits different for each of the 32 Wilsh codes, and they are orthogonal. However, if '0' and '1' are inverted using XOR as in normal mode and low power mode, they are not inverted. If you do not have a duplicate Wilshire code. For example, the inverted value of the selected 32-bit Walsh code "01100110011001100110011001100110" of W32 and the selected 32-bit Walsh code "10011001100110011001100110011001" of W34 exactly match. This phenomenon occurs when only 32 bits are selected and transmitted from 64 bits. Due to this phenomenon, in the high performance mode in which only 32 bits are spread out of the 64-bit Walsh code in order to double the symbol rate, the 4-bit input bit is used as in the sub-frequency selective spreader in the normal mode and the low power mode. Inverting the output value by XOR using the least significant bit of cannot be used.

7 is a structural diagram of a frequency selective spreader in a high performance mode according to an embodiment of the present invention.

In the high performance mode, the frequency selective spreader 217 also uses a fast spreading method to increase data transmission efficiency. The slow frequency selective spreader uses a slow spreading method to provide better transmission performance than the data transmission efficiency. 600, and a multiplexer 700 for selecting and outputting any one of the output values of the fast frequency selective diffuser 500 and the slow frequency selective diffuser 600, the fast frequency selective diffuser 500 being a sub. The frequency selective spreaders 1 to 3 (510, 520, 530) and the multi-value selector 540, the slow frequency selective spreader 600 is a sub-frequency selective spreaders 4 and 5 (610, 620) and a multiplexer 630 It consists of

The operation of the frequency selective spreader 217 according to the selected spreading method (fast spreading method or slow spreading method) will be described in detail below.

One) High Performance Mode (64 MHz  Clock, Symbol rate  2 Msps ) And fast diffusion method

The S2P 216 converts the input serial data DIN into parallel data of P * M bits and outputs it. Thereafter, the P sub-frequency selective spreaders 510, 520, and 530 belonging to the fast frequency selective spreader 500 of the frequency selective spreader 217 receive M data bits, respectively, and use 2 ^M data bits in the corresponding subgroup. One of the spreading codes is selected. That is, P spreading codes are selected through the P sub-frequency selective spreaders 510, 520, and 530. Thereafter, the multivalue selector 540 selects a multiplicity value from the P spread codes acquired through the P sub-frequency selective spreaders 510, 520, and 530 to generate transmission data having a multiplicity value.

As a specific example, when BAND_SEL is designated as "0111", DIN, a signal input to the S2P 216, has a data rate of up to 18 Mbps, and is serial-parallel at a ratio of 1: 9 by the S2P 216. The conversion is performed, and 9-bit parallel symbols of b8, b7, ..., b0 are output as 2Msps. The output parallel symbols are input to the fast frequency selective spreader 500 of the frequency selective spreader 217.

Since BAND_SEL is " 0111 ", subgroup 5 (SGN = "101"), subgroup 6 (SGN = "110") and subgroup 7 (SGN = "111") are selected, thereby subfrequency selective spreader 1 The SGN1 to SGN3 values in the to 3 become "101", "110", and "111", respectively.

The sub-frequency selective spreader 1 (510) selects one of eight Wilshee codes (W ₄₀ to W ₄₇ ) of subgroup 5 using the input bits b8, b7, b6 and SGN1 value "101" and selects one of the 64 bits selected. 32 bits A are output in the form of 1 bit string.

The sub-frequency selective spreader 2 520 selects one of the 8 Wilsh codes (W ₄₈ to W ₅₅ ) of subgroup 6 using the input bits b5, b4, b3, and the SGN2 value "110", and selects one of the 64 bits selected. Outputs 32 bits (B) in the form of 1 bit string.

The sub-frequency selective spreader 3 (530) selects one of the 8 Wilsh codes (W ₅₆ to W ₆₃ ) of the subgroup 7 using the input bits b2, b1, b0, and the SGN3 value "111", and selects one of the 64 bits selected. Outputs 32 bits (C) in the form of 1 bit string.

The multi-value selector 540 receives the 3-bit strings A, B, and C output from the sub-frequency selective spreaders 1 to 3 (510, 520, and 530), calculates Equation 1, and calculates Output D

In the present embodiment, the Tx_RATE control bit has a value of '0'. Accordingly, D, which is an output value of the fast frequency selective spreader 500, is selected and output to the output DOUT of the frequency selective spreader 217.

2) High Performance Mode (64 MHz  Clock, Symbol rate  2 Msps ) And slow diffusion method

S2P 216 converts the input serial data DIN into parallel data of S + M bits and outputs it. Thereafter, the Q sub-frequency selective spreaders 610 and 620 belonging to the low frequency selective spreader 600 of the frequency selective spreader 217 receive M data bits, respectively, and use the 2 ^M spreading codes in the corresponding subgroup. Select one of the spreading codes. That is, Q spreading codes are obtained through the Q sub-frequency selective spreaders 610 and 620. Thereafter, the multiplexer 630 generates transmission data by selecting one spreading code using S bits among the input data bits in the Q spreading codes acquired through the Q sub-frequency selective spreaders 610 and 620.

As a specific example, when BAND_SEL is designated as "0011", DIN, a signal input to the S2P 216, has a data transfer rate of up to 8 Mbps, and is serial-parallel at a ratio of 1: 4 by the S2P 216. The conversion is performed to output 4-bit parallel symbols of b3, b2, ..., b0 at 2Msps. The output parallel symbols are input to the low frequency selective spreader 600 of the frequency selective spreader 217.

Since BAND_SEL is "0011", subgroup 6 (SGN = "110") and subgroup 7 (SGN = "111") are selected so that the SGN4 and SGN5 values at sub-frequency selective spreaders 4 and 5 are respectively " 110 "and" 111 ".

The sub-frequency selective spreader 4 610 selects one of the 8 Wilsh codes (W ₄₈ to W ₅₅ ) of subgroup 6 using the input bits b2, b1, b0 and the SGN4 values "110", and selects 32 out of the 64 bits selected. Outputs the bit F in the form of one bit string.

The sub-frequency selective spreader 5 620 selects one of the 8 Wilsh codes (W ₅₆ to W ₆₃ ) of subgroup 7 using the input bits b2, b1, b0 and the SGN5 value "111", and selects 32 out of the 64 bits selected. Outputs the bit G in the form of one bit string.

The multiplexer 630 receives two bit strings of F and G output from the sub-frequency selective spreaders 4 and 5 (610 and 620), receives b3 of the output of the S2P 216, and b3 is '0'. In the case of '1', the output F of the sub frequency selective spreader 4 610 is selected and the output G of the sub frequency selective spreader 5 620 is selected and output to the output H of the low frequency selective spreader 600.

In the present embodiment, the Tx_RATE control bit has a value of '1', so H, which is an output value of the slow frequency selective spreader 600, is selected by the multiplexer 700 to output DOUT of the frequency selective spreader 217. Is output.

8 is a structural diagram of a sub-frequency selective spreader in a high performance mode according to an embodiment of the present invention.

Unlike the general mode, the sub-frequency selective spreader has 3 bits of input bits and outputs only 32 bits among the generated 64-bit Walsh codes in the form of 1 bit string.

Sub-frequency selective spreader 1 510 is comprised of a six-bit counter 511, six XOR logic circuits 512-1 through 512-5, 514 and six AND logic circuits 513-1 through 513-6. And three bits of frequency selection control bits (s2, s1, s0) and three bits of input bits (b8, b7, b6).

The 6-bit counter 511 is reset to an initial value '16' every symbol period to count 16 to 47 in the high performance mode.

One of the eight Walsh codes included in the subgroup is generated using the 3-bit frequency selection control bits (s2, s1, s0) and the 3-bit input bits (b8, b7, b6) and output in the form of 1-bit string. (A).

Five XOR logic circuits 512-1 through 512-5 are for gray indexing. The six AND logic circuits 513-1 to 513-6 are C ₅ to C ₀ , which are outputs of the 6-bit counter 511, and s2 and five XOR logic circuits 512-1 to the most significant bits of the frequency selection control bit. The output bits of 512-5) are input respectively. In addition, one XOR logic circuit 514 is for XORing the outputs of the six AND logic circuits 513-1 to 513-6.

The frequency selective digital transmitter in the high performance mode described with reference to FIGS. 6 to 8 may be used in the normal mode or the low power mode as well as the high performance mode.

In addition, although the structure of the frequency selective spreader illustrated in FIGS. 4 and 7 is shown differently to explain the difference between the high performance mode and the normal mode, in an actual implementation, the structure may be integrated into one structure using a control signal.

In addition, the frequency selective spreader may be replaced with a frequency selective spreader having a different structure capable of receiving N bits output from the S2P 216 and outputting the same output as the frequency selective spreaders shown in FIGS. 4 and 7.

In addition, the configurations of the fast frequency selective spreader 500, the slow frequency selective spreader 600, and the multiplexer 700 in the frequency selective spreader 217 shown in FIG. 4 and FIG. It can be implemented with one or more frequency selective spreaders supporting various transmission rates from high speed to high speed. In this case, the frequency selective spreader adjusts the number of output bits spread from the frequency selective spreader per S2P output symbol input to the frequency selective spreader to support various transmission speeds from high speed to low speed, that is, spreading factor. ) To transmit.

The present invention is not limited by the above-described embodiment and the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be substituted, modified, and changed in accordance with the present invention without departing from the spirit of the present invention.

100: human body communication MAC
110: MAC transmit processor 120: MAC receive processor
200: human body communication physical layer modem
210: Transmitter 211: Preamp Generator
212: first diffuser 213: header generator
214: second diffuser 215: data generator
216: S2P 217: frequency selective diffuser
218: multiplexer
220: receiver 221: demultiplexer
222: despreader 223: header processor
224: frequency selective despreader 225: P2S
226: Data Processor 227: Frame Synchronizer
228: common control signal generator
300: human body communication AFE
310: transmit / receive switch 320: noise reduction filter
330: Amplifier 340: Clock Recovery & Data Retiming
400: signal electrode

Claims (13)

Preamble transmission processing means for generating a frame synchronization preamble and spreading the signal with a predetermined spreading code;
Header transmission processing means for constructing a header including data attribute information and spreading the header with a predetermined spreading code;
Data transmission processing means for performing a serial-to-parallel conversion on the transmission data according to the selected transmission mode and spreading method and then spreading the spreading signal with a frequency selective spreading code; And
And multiplexing means for multiplexing the preamble, header, and data spread by the preamble transmission processing means, the header transmission processing means, and the data transmission processing means, respectively, and transmitting them as a digital signal.
The method of claim 1,
The data transmission processing means,
^Divide 2 ^N (N is a real number) spreading codes by 2 ^M (M is a real number, M <N) to create a plurality of subgroups, and adopt P (P is a real number) subgroups from the generated plurality of subgroups. Frequency selective digital transmitter, characterized in that for use.
The method of claim 2,
The data transmission processing means,
A serial-to-parallel converter for performing serial-to-parallel conversion on the transmission data at a preset ratio; And
And a frequency selective spreader which receives the output of the serial-to-parallel converter and spreads the transmission data according to a spreading method selected from a fast spreading method and a slow spreading method.
The method of claim 3, wherein
The frequency selective diffuser,
A fast frequency selective spreader for spreading the transmission data according to the fast spreading method;
A slow frequency selective spreader for spreading the transmission data according to the slow spread method; And
And a multiplexer for selecting and outputting any one of output values of the fast frequency selective spreader and the slow frequency selective spreader according to the selected spreading scheme.
The method of claim 4, wherein
When the fast diffusion method is selected,
The serial-to-parallel converter converts the transmission data into parallel data of P * (M + 1) bits and outputs the converted data.
The fast frequency selective spreader,
M + 1 data bits are inputted from the serial-to-parallel converter to select one spreading code from the corresponding subgroup using M data bits, and to obtain a spreading code by XORing the remaining data bits to the selected value. P sub-frequency selective spreaders; And
And a plurality of value selectors for selecting a plurality of values from the P spreading codes acquired through the P sub-frequency selective spreaders, respectively.
The method of claim 4, wherein
When the fast diffusion method is selected,
The serial-to-parallel converter converts the transmission data into parallel data of P * M bits and outputs the same.
The fast frequency selective spreader,
P sub-frequency selective spreaders that select one spreading code from the subgroup using M data bits received from the serial-to-parallel converter; And
And a plurality of value selectors for selecting a plurality of values from the P spread codes selected through the P sub-frequency selective spreaders, respectively.
The method of claim 4, wherein
When the slow diffusion method is selected,
The serial-to-parallel converter converts the transmission data into parallel data of S + (M + 1) bits and outputs the converted data.
The slow frequency selective spreader,
M + 1 data bits are inputted from the serial-to-parallel converter to select one spreading code from the corresponding subgroup using M data bits, and to obtain a spreading code by XORing the remaining data bits to the selected value. Q sub-frequency selective spreaders; And
And a multiplexer for selecting one spreading code using the remaining S data bits in the Q spreading codes acquired through the Q sub-frequency selective spreaders, respectively.
The method of claim 4, wherein
When the slow diffusion method is selected,
The serial-to-parallel converter converts the transmission data into parallel data of S + M bits, and outputs the converted data.
The slow frequency selective spreader,
Q sub-frequency selective spreaders for selecting one spreading code from the subgroup using M data bits received from the serial-to-parallel converter; And
And a multiplexer for selecting one spreading code using the remaining S data bits in each of the Q spreading codes selected through the Q sub-frequency selective spreaders.
The method of claim 1,
The data transmission processing means,
A frequency selective digital transmitter, characterized by operating at a different clock and symbol rate depending on a transmission mode selected from a normal mode, a low power mode, and a high performance mode.
The method of claim 9,
When the high performance mode is selected,
And said data transmission processing means uses only some of the output bits of said frequency selective spreading code.
The method of claim 10,
And said data transmission processing means uses N / 2 bits located in the center when the number of output bits of said frequency selective spreading code is N.
The method of claim 3, wherein
The data transmission processing means,
And a variable transmission speed by controlling the number of output bits of the frequency selective spreader per output symbol of the serial-to-parallel converter.
Preamble transmission processing means for generating a frame synchronization preamble and spreading the signal with a predetermined spreading code;
A header and data transmission processing means for spreading a header including data attribute information and spreading with a frequency selective spreading code after performing serial-to-parallel conversion on transmission data according to the selected transmission mode and spreading scheme; And
And multiplexing means for multiplexing the preamble, the header and the transmission data spread by the preamble transmission processing means, the header and the data transmission processing means, respectively, and transmitting them as a digital signal.

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