KR20100116960A - Delay cell having improved phase noise characteristic - Google Patents

Delay cell having improved phase noise characteristic Download PDF

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Publication number
KR20100116960A
KR20100116960A KR1020090035651A KR20090035651A KR20100116960A KR 20100116960 A KR20100116960 A KR 20100116960A KR 1020090035651 A KR1020090035651 A KR 1020090035651A KR 20090035651 A KR20090035651 A KR 20090035651A KR 20100116960 A KR20100116960 A KR 20100116960A
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South Korea
Prior art keywords
stage
output
delay cell
phase noise
voltage
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KR1020090035651A
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Korean (ko)
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윤광섭
한윤택
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인하대학교 산학협력단
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Publication of KR20100116960A publication Critical patent/KR20100116960A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/354—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse

Abstract

PURPOSE: A delay cell is provided to simplify a circuit configuration by removing the additional configuration for improving the satellite noise property. CONSTITUTION: An input terminal(302) is inputted with a signal. A cascode stage(303) is connected to the DC power supply voltage and the input terminal. A current path offering stage is connected to both output stages. A cross coupled stage(304) is connected to the both of output terminals. An output load stage(305) is connected to the both of output terminals and the ground.

Description

Delay cell having improved phase noise characteristic

The present invention relates to a delay cell having improved phase noise characteristics, and more particularly, to a delay cell for improving phase noise characteristics such as a voltage controlled oscillator, phase locked loops (PLL), and delay locked loops (DLL).

A voltage controlled oscillator (VCO) is a device that enables output of a desired oscillation frequency with an externally applied voltage. The voltage controlled oscillator is used in a PLL and a DLL.

Typical voltage controlled oscillators include ring oscillators and LC oscillators.

The LC oscillator includes an inductor L and a capacitor C. The LC oscillator generates an oscillation signal by using the resonance characteristics of the inductor and the capacitor. The LC oscillator can obtain a low noise characteristic and a high resonance frequency. However, due to the difficulty of implementing an inductor with low parasitic components, it is not suitable for an integrated circuit for implementing an oscillator and takes a large area.

The ring oscillator is an oscillator using a plurality of delay cells having the same delay characteristics, and extracts an oscillation signal from the output of any one of the delay cells. The ring oscillator may adjust the frequency of the oscillation signal by using a property in which a delay characteristic of the delay cell changes according to a power supply voltage or a supply current supplied to the delay cell. The ring oscillator can be implemented in a small area and has a wide frequency domain. However, the disadvantage is that the phase noise characteristics are not good.

The present invention provides a delay cell having improved phase noise characteristics.

The present invention also provides a ring-voltage controlled oscillator having a low phase noise characteristic including a delay cell having improved phase noise characteristics.

According to an aspect of the present invention, an input terminal for receiving a signal, a cascode terminal connected to a DC power voltage and an input terminal, a current path providing terminal connected to both output terminals, a cross-coupled terminal connected to both output terminals, and an output unit connected to both output terminals and ground There is provided a delay cell with improved phase noise characteristics, including a bottom.

The cascode stage is composed of MOS transistors connected in series to generate a constant output voltage even with a change in the DC power supply voltage.

The input stage consists of two PMOS transistors.

The current path providing stage is composed of transistors connecting both output stages, and the current flows from the high potential stage to the low potential stage by the voltage difference between the two output stages.

In addition, the gate voltage of the current path providing end,

Figure 112009024779552-PAT00001
To model the resistance
Figure 112009024779552-PAT00002
The formula of is as follows.

Figure 112009024779552-PAT00003

The cross-coupled stage is configured such that the gate terminal of one transistor and the drain terminal of the other transistor are connected to each other, and are connected to both output terminals.

In addition, the cross-coupled stage is configured to achieve the symmetry of the rising and falling of the output signal through the positive feedback of both output stages.

The output load stage is a symmetrical load structure composed of MOS transistors.

Figure 112009024779552-PAT00004
Make the value appear linear.

According to the present invention, the ring-voltage controlled oscillator using the delay cell of the present invention can greatly improve the phase noise characteristics compared to the conventional ring-voltage controlled oscillator.

In addition, in the conventional ring-voltage controlled oscillator, an additional configuration is required to improve satellite noise characteristics, and the circuit implementation is complicated. However, the ring-voltage controlled oscillator using the delay cell according to the present invention can be implemented with a simple circuit.

In addition, it is possible to implement a wide tuning range with a smaller area than conventional ring-voltage controlled oscillators.

Therefore, it can be used in place of a low phase noise oscillator such as an LC-tank voltage controlled oscillator.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description.

Hereinafter, an embodiment of a delay cell having improved phase noise characteristics according to the present invention will be described in detail with reference to the accompanying drawings. In the following description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals. Duplicate description thereof will be omitted.

1 is an overall block diagram of a ring-voltage controlled oscillator according to the prior art.

Referring to FIG. 1, the ring-voltage controlled oscillator 100 according to the related art is a three-stage ring-voltage controlled oscillator using a replica bias 101 and a delay cell 102. The ring-voltage controlled oscillator 100 according to the prior art is configured in such a manner that each delay cell 102 is connected in series to each other in an odd number, and the output of the last delay cell is connected to the input of the first delay cell.

2 is a delay cell 200 included in a ring-voltage controlled oscillator according to the prior art.

Referring to FIG. 2, input signals are input to both input terminals 201 and 202, respectively. The current source control voltage 203 is applied to the transistor 204 serving as a current source to maintain a constant amount of current flowing through both input terminals 201 and 202. The output load control voltage 205 serves to finally adjust the delay values of both output terminals 208 and 209 by adjusting the resistance values of the output load units 206 and 207.

3 is a delay cell 300 having improved phase noise characteristics according to an exemplary embodiment of the present invention.

Referring to FIG. 3, a bias input of Vbp1, Vbp2, and Vbn, input and output of in +, in-, out +, and out- signals, and a gate control voltage input for resistance values of M11 of Vr are provided. Here, the biases input to Vbp1, Vbp2, and Vbn may be replica biases.

The following embodiments may be implemented to implement the delay cell 300 with improved noise characteristics of the present invention.

First, M11 constituting the current path providing terminal 301 may be included.

The current path providing stage 301 may be configured by transistors connecting both output stages so that current flows from the high potential stage to the low potential stage by the voltage difference between the two output stages.

The current path providing stage 301 is a gate voltage of M11 (

Figure 112009024779552-PAT00005
) To control the resistance
Figure 112009024779552-PAT00006
Can be modeled with According to the voltage difference between the source terminal and the drain terminal of the M11, that is, the output terminals of the delay cell, the current flows from the terminal having the higher potential to the terminal having the lower potential. In other words, the current flows the most when the output is the same, which slows the effect of noise on the signal.

When the delay cell 300 including the current path providing terminal 301 is compared with delay cells according to the conventional technology (that is, M11 is not included), the phase noise characteristic may be improved by about 5 to 10 dB.

Equation 1 below is a resistance value of M11 constituting the current path providing terminal 301.

Figure 112009024779552-PAT00007
The expression defined for. That is, the gate voltage of the current path providing end
Figure 112009024779552-PAT00008
To model the resistance
Figure 112009024779552-PAT00009
The formula of Equation is as follows.

[ Equation 1]

Figure 112009024779552-PAT00010

Where here

Figure 112009024779552-PAT00011
Hole mobility of M11,
Figure 112009024779552-PAT00012
The oxide capacity of M11,
Figure 112009024779552-PAT00013
Is the width of the channel of M11,
Figure 112009024779552-PAT00014
Is the length of the channel of M11 and
Figure 112009024779552-PAT00015
Is the threshold voltage of M11.

Equation 2 below is Ali Hajimiri's equation, which is a noise analysis model of a ring-voltage controlled oscillator.

[ Equation 2]

Figure 112009024779552-PAT00016

here,

Figure 112009024779552-PAT00017
Is the minimum phase noise of the circuit
Figure 112009024779552-PAT00018
Is the center frequency (
Figure 112009024779552-PAT00019
Is the offset frequency according to η is a proportional constant, kT is thermal energy, N is the number of delay stages, P is the power consumption (P = N · I tail ㆍ V DD ).

Referring to Equation 2, when all conditions are the same, in the case of the delay cell 300 including the current path providing terminal 301 as in the embodiment of the present invention, the current path providing terminal 301 is not included. The effect is to increase the I tail over the delay cell. It can be seen that the phase noise characteristic of the delay cell 300 according to the embodiment of the present invention is improved through the theoretical equation verified as described above.

Next, the input terminal 302 can be configured as a PMOS.

The input terminal 302 for receiving a signal has conventionally used an NMOS, but in the present invention, a PMOS is used. In the case of PMOS, since the majority carrier is a hole, the hole is not moved to the surface but the hole moves deep in the surface, so the noise can be reduced to about 1 / f than the NMOS. That is, by M1 and M2 constituting the input terminal 302 of the present invention, the noise can be reduced to about 1 / f as compared to the input terminal composed of the conventional NMOS.

Next, the cascode terminal 303 is configured such that a power supply voltage is connected to two cascode-connected two MOS transistors M9 and M10.

That is, the cascode terminal 303 may be composed of MOS transistors connected in series.

In addition, the cascode terminal 303 may generate a constant output voltage even with a change in the DC power supply voltage.

Power supply rejection (PSRR) may be increased by M9 and M10 constituting the cascode stage 303. Here, PSRR means keeping the output voltage constant against the variation of the DC power supply voltage.

Next, the cross-coupled end 304 was comprised. The crosscoupled stage is constituted by M3 and M4 that are cross coupled.

That is, the cross-coupled end 304 is configured such that the gate terminal of one transistor and the drain terminal of the other transistor are connected to each other.

In addition, the crosscoupled stage 304 is configured to be connected to both output stages.

The cross-coupled stage 304 is configured to achieve symmetry of the rising and falling of the output signal through the positive feedback of both output stages.

That is, M3 and M4 constituting the cross-coupled stage 304 make the rising and falling of the output signal symmetrical through positive feedback of both output stages, making the signal range as close to rail-to-rail as possible. You can try to improve the phase noise.

Next, the output load end 305 is comprised.

The output load stage 305 is a symmetrical load structure composed of MOS transistors. That is, the output load end 305 is to be composed of the symmetrical load M7 and M8.

The output load stage 305 has a symmetrical load structure according to the input signal.

Figure 112009024779552-PAT00020
You can make the values appear linear. That is, by using the symmetrical loads M7 and M8 constituting the output load stage 305 according to the input signal
Figure 112009024779552-PAT00021
The phase noise is improved by configuring the values linearly. In other words, using a symmetrical load, the output range is limited from 0V to Vout compared to the conventional technology, but can show much better linearity than the linear region load of the prior art.

Number of delay stages (N) and source-drain resistances of M5 to M8 (

Figure 112009024779552-PAT00022
), The load capacitance between each delay stage (
Figure 112009024779552-PAT00023
) And oscillator generation frequency (
Figure 112009024779552-PAT00024
) Can be represented by Equation 3 below.

[ Equation 3]

Figure 112009024779552-PAT00025

Figure 112009024779552-PAT00026

When generating the same frequency, if the number of delay stages is small, the delay value that should be generated in the delay stage should be large. As the delay increases, so does the edge slew rate. Therefore, the sensitivity to the overall noise is reduced.

On the contrary, if the number of delay stages is large, there are many sources in which noise occurs.

Therefore, it is important to set an appropriate number of delay stages accordingly, and the third stage may be the ideal sweet spot. If the delay stage is composed of three stages, gain can be obtained sufficiently by amplification of one stage, and noise can be reduced by a simple configuration.

4 is a perspective view illustrating a phase noise characteristic of a delay cell in which a phase noise characteristic is to be improved according to an exemplary embodiment of the present invention.

Referring to FIG. 4, an operating frequency (Center Frequency) is 1.9 GHz and an Offset Frequency is about 200 KHz (199.906 KHz). At this time, the phase noise characteristic is -101.148dBc / Hz.

Also, if the offset frequency is 600KHz (600.068KHz), the phase noise characteristic is -110.699dBc / Hz.

 As described above, the delay cell having the improved phase noise characteristic according to the present invention can significantly improve the phase noise characteristic than the delay cell according to the prior art. In addition, it can be implemented in a simple circuit compared to the prior art. Therefore, there is an advantage that a wide tuning range can be realized with a smaller area than before.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

1 is an overall block diagram of a ring-voltage controlled oscillator according to the prior art.

2 is a circuit diagram illustrating a delay cell included in a ring-voltage controlled oscillator according to the prior art.

3 is a circuit diagram illustrating a delay cell having improved phase noise characteristics according to an exemplary embodiment of the present invention.

4 is a perspective view showing phase noise characteristics of a delay cell having improved phase noise characteristics according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

301: current path providing stage 302: bias input stage

303: cascode end 304: cross couple end

305: output load end

Claims (12)

An input terminal for receiving a signal; A cascode terminal connected to a DC power supply voltage and the input terminal; A current path providing stage connected to both output stages; A cross-coupled end connected to both output terminals; And And a delay cell having an output load connected to both output terminals and ground. The method of claim 1, And the cascode stage comprises a MOS transistor connected in series. The method of claim 1, And the cascode stage generates a constant output voltage even when the DC power supply voltage is fluctuated. The method of claim 1, And the input stage comprises two PMOS transistors. The method of claim 1, And the current path providing stage comprises a transistor connecting the both output stages. The method of claim 1, And the current path providing stage allows current to flow from a high potential stage to a low potential stage by a voltage difference between the two output stages. The method of claim 1, A resistance value modeled by controlling V_R, which is a gate voltage of the current path providing end,
Figure 112009024779552-PAT00027
The delay cell of the improved phase noise, characterized in that as follows. Equation
Figure 112009024779552-PAT00028
 (here,
Figure 112009024779552-PAT00029
Hole mobility of M11,
Figure 112009024779552-PAT00030
The oxide capacity of M11,
Figure 112009024779552-PAT00031
Is the width of the channel of M11,
Figure 112009024779552-PAT00032
Is the length of the channel of M11 and
Figure 112009024779552-PAT00033
Is the threshold voltage of M11) The method of claim 1, And wherein the cross-coupled stage is configured such that a gate terminal of one transistor and a drain terminal of the other transistor are connected to each other. The method of claim 1, And the cross-coupled stage is connected to both output stages. The method of claim 1, The cross-coupled end of the delay cell is improved phase noise, characterized in that configured to achieve the symmetry of the rising and falling of the output signal through the positive feedback of both outputs. The method of claim 1, And the output load end is a symmetrical load structure consisting of MOS transistors. The method of claim 1, The output load end is in accordance with the input signal by the symmetrical load structure
Figure 112009024779552-PAT00034
Delay cell with enhanced phase noise, characterized in that the value appears linearly.
KR1020090035651A 2009-04-23 2009-04-23 Delay cell having improved phase noise characteristic KR20100116960A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112257191A (en) * 2020-12-23 2021-01-22 中国人民解放军国防科技大学 Load platform integrated microsatellite thermal control subsystem optimization method and system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112257191A (en) * 2020-12-23 2021-01-22 中国人民解放军国防科技大学 Load platform integrated microsatellite thermal control subsystem optimization method and system

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