KR20100115268A - Solid state drive - Google Patents

Abstract

PURPOSE: A solid state drive is provided to offer single package type SSD with increased storage capacity, reduced size, and improved reliability. CONSTITUTION: A host interface(100) of the LGA(Land Grid Array) or the BGA(Ball Grid Array) type is connected to external host. A controller(300) is electrically connected to the host interface and semiconductor memory device. The controller controls data read and write operation about the semiconductor memory device and data transceiver operation with the external host. The number of host interface terminal is determined by the host interface communication protocol. The above semiconductor memory device is the nonvolatile memory.

Description

Solid State Drives {Solid State Drive}

FIELD OF THE INVENTION The present invention relates to data storage devices, and more particularly to solid state drives (SSDs).

A solid state drive (hereinafter referred to as 'SSD') is a data storage device that uses a semiconductor memory element such as, for example, a flash memory, a DDR memory, but not a hard disk as a data storage medium. SSDs, unlike traditional hard disk drives (HDDs), do not require motors and mechanical drives, generate little heat and noise during operation, are extremely resistant to external shocks, and consume very little power. In addition, SSDs can achieve significantly improved data transfer / write / read rates compared to HDDs. Thus, SSDs are attracting attention as next-generation storage devices that can replace HDDs.

Conventional SSDs take the form of a disk on module (DOM) such as a flash disk module (FDM). Conventional DOM-type SSDs typically have capacities ranging from 16 MB to 2 GB and are equipped with NAND flash controllers, IDE or SATA interface circuits, and IDE or SATA connectors. This DOM-type SSD is designed to support 8 / 16-bit transfer with a host and to support file systems of existing OSs (ie, DOS, Windows, Unix, etc.). Thus, the conventional SSD SSD is 100% compatible with the existing HDD in terms of appearance and functionality.

As such, the conventional DOM-type SSD can be connected to the host interface via a 40-pin IDE connector, a 44-pin mini-IDE connector or a SATA connector, thereby providing a PC, an internet terminal, and an Internet set-top box. Widely used in (internet set top box) and the like.

However, emerging host systems such as Ultra Mobile Personal Computers (UMPCs) or Mobile Internet Devices (MIDs), i.e. more complex functionality, smaller form factors, and higher reliability in harsh environments are required. To be applied to host systems, conventional FDM or DOM type SSDs are still not suitable.

Specifically, a conventional SSD in the form of FDM or DOM has insufficient storage capacity. In addition, the conventional FDM or DOM type SSD has an IDE connector, a mini-IDE connector or a SATA connector, it is impossible to further miniaturize. In addition, the SSD of the conventional FDM or DOM type, due to the weakness of the internal structure of the module (module), it is still sensitive to the external shock and high temperature and high humidity environment, the quality and reliability in more harsh environment Defects are very likely to occur.

It is an object of the present invention to provide an SSD in a single package that can easily achieve increased storage capacity, further reduced size and improved reliability.

SSD of a single package provided by the present invention,

A host interface in the form of a land grid array (LGA) or a ball grid array (BGA) for connecting to an external host;

At least one semiconductor memory device; And

And a controller electrically connected to the host interface and the semiconductor memory device to control data transmission / reception with an external host and data read / write operations to the semiconductor memory device.

In another embodiment of the SSD of the present invention, the number of terminals of the host interface is determined according to the host interface communication protocol.

In another embodiment of the SSD of the present invention, the host interface communication protocol is integrated drive electronics (IDE), enhanced integrated drive electronics (EIDE), serial AT attachment (SATA), small computer system interface (SAS), SAS (SAS). serial attached SCSI) or compact flash.

In another embodiment of the SSD of the present invention, the semiconductor memory device is a nonvolatile memory.

In another embodiment of the SSD of the present invention, the semiconductor memory device is mounted in the form of a bare chip.

In another embodiment of the SSD of the present invention, the semiconductor memory devices are mounted in a stacked arrangement.

In another embodiment of the SSD of the present invention, the SSD further comprises a resin sealing part for blocking the semiconductor memory device and the controller from an external environment.

Another embodiment of the SSD of the present invention further includes a terminal for testing an internal circuit.

SSDs in the form of a single package of the present invention can easily achieve increased storage capacity, further reduced size and improved reliability.

Hereinafter, a single packaged SSD of the present invention will be described in more detail with reference to FIG. 1. 1 is a cross-sectional view schematically showing an SSD in the form of a single package according to an embodiment of the present invention.

The SSD of the embodiment of FIG. 1 includes a substrate 10, a host interface 100 formed on one surface of the substrate 10, a semiconductor memory device 200 mounted on the other surface of the substrate 10, and a substrate 10. The controller 300 is mounted on the other side of the substrate, and the resin sealing part 400 is provided to block the semiconductor memory device 200 and the controller 300 mounted on the other surface of the substrate 10 from the external environment. Thus, the overall appearance of the SSD of the embodiment of FIG. 1 is similar to a semiconductor device in the form of a single package.

The substrate 10 includes electrical connection means such as, for example, circuit patterns and via holes, thereby providing electrical connection of the host interface 100, the semiconductor memory device 200, and the controller 300.

The host interface 100 may be in the form of a land grid array (LGA) or a ball grid array (BGA). Land grid array (LGA) is a kind of semiconductor package method and is known as a term referring to a package method in which chip electrodes are formed in an array form on the bottom of the semiconductor package. In the present invention, LGA refers to an array electrode formation method employed in such an LGA semiconductor package method. A ball grid array (BGA) is a type of semiconductor package. A package that replaces leads by arranging solder terminals with solder balls in a two-dimensional array on the back of a printed circuit board (PCB) on which semiconductor chips are placed. Known as a term that refers to. In the present invention, BGA refers to an electrode forming method in the form of solder terminals on a two-dimensional array employed in such a BGA semiconductor package method. By taking this form, the host interface 100 has a much smaller footprint compared to the standard IDE port, mini-IDE port or SATA port provided in a conventional SSD. As a result, the overall size of the SSD can be reduced. In addition, by mounting more semiconductor memory devices in the free space obtained from the reduction of the occupied space of the host interface 100, the storage capacity of the SSD may be further enhanced. In addition, the host interface 100 in the form of LGA or BGA is inexpensive compared to the standard IDE port, mini-IDE port or SATA port provided in the conventional SSD, and can greatly simplify the SSD manufacturing process. have.

When providing a detachable SSD from an external host, the host interface 100 is preferably in the form of LGA. When providing an "embedded SSD" fixed to an external host, the host interface 100 is preferably in the form of a BGA.

The number of terminals (or pins) of the host interface 100 may be easily determined according to the selected host interface communication protocol. For example, when IDE is selected as the host interface communication protocol, the number of terminals of the host interface 100 may be 40, 44 in the case of mini-IDE, and 7 in the case of SATA.

The arrangement of the terminals of the host interface 100 is not particularly limited, and may simply be identical to the arrangement of the terminals of the external host to be applied. Conversely, the terminal arrangement method of the external host may be changed according to the terminal arrangement method of the host interface 100. Therefore, the SSD of the present invention can be easily applied to general-purpose systems as well as embedded systems. Specific examples of the arrangement of the host interface 100 terminals are illustrated in FIGS. 3 and 4. 3 and 4 are bottom views of the SSD of FIG. 1. In FIG. 3, terminals of the host interface 100 are arranged at the center of the bottom surface of the substrate 10. In FIG. 4, terminals of the host interface 100 are arranged at the periphery of the bottom of the substrate 10.

In addition, since the host interface 100 takes the form of LGA or BGA, various types of host interface communication can be performed in a fixed number of terminals and in an arrangement manner by disabling or enabling some of the terminals of the host interface 100. It is very easy to have protocol support.

The host interface 100 may further include a terminal for supplying power necessary for the operation of the controller 300 or the semiconductor memory device 200 as well as a terminal necessary for performing the host interface communication protocol.

The semiconductor memory device 200 may be, for example, a volatile memory or a nonvolatile memory. In terms of not requiring a backup power supply, the semiconductor memory device 200 is preferably a nonvolatile memory. As the nonvolatile memory, for example, flash memory, EPROM, EEPROM, FeRAM, MRAM, PRAM, SONOS, RRAM, NRAM, and the like can be used. As the flash memory element, for example, a nand flash memory element or a nor flash memory element can be used.

The semiconductor memory device 200 is preferably mounted in the form of a bare chip. Compared to the semiconductor memory device in the form of a package having a resin sealing part, the size of the SSD can be further reduced by using a bare chip type semiconductor memory device in which the resin sealing part is omitted. In addition, by using a semiconductor device in the form of a bare chip, since more semiconductor memory devices can be mounted in a limited space, the storage capacity of the SSD can be further increased.

When a plurality of semiconductor memory devices 200 are mounted, the semiconductor memory devices 200 may be mounted in a planar array or a stacked array. According to the aspect ratio of the external shape of the SSD to be implemented, an arrangement method of the plurality of semiconductor memory devices 200 may be easily selected to optimize the external size and storage capacity of the SSD. Preferably, by stacking a bare chip type semiconductor memory device, an SSD having a larger storage capacity may be implemented under the same form factor.

The controller 300 is electrically connected to the host interface 100 and the semiconductor memory device 200 to control data transmission / reception with an external host and data read / write operations with respect to the semiconductor memory device 200.

The controller 300 may be implemented as a one-chip device or a plurality of devices. The controller 300 is preferably a one-chip device in the form of a bare chip. When the controller 300 is a bare chip type one-chip device, the size of the SSD may be further reduced.

The resin sealing part 400 covers the semiconductor memory device 200 and the controller 300 to block the semiconductor memory device 200 and the controller 300 from the external environment. In the SSD of the present invention, the resin sealing unit 400 may allow only the host interface 100 to be exposed to the external environment. As such, the semiconductor memory device 200 and the controller 300 are completely blocked by the resin sealing part 400 from the external environment, so that the SSD of the present invention can exhibit high reliability even in a harsh environment of high temperature and high humidity. have. In particular, even when the bare chip type semiconductor memory device 200 or the bare chip type controller 300 is used, due to the resin sealing part 400, the SSD of the present invention can still exhibit a high degree of reliability.

In another embodiment of the present invention, the SSD of the present invention may further include an internal circuit test terminal. In this case, the terminal for internal circuit test is connected to the controller. The controller may further include a routine that responds to a test request signal input through an internal circuit test terminal, in addition to a data transmission / reception operation with an external host and a data read / write operation with respect to the semiconductor memory device 200.

2 is a block diagram of an embodiment of an SSD of the present invention further including an internal circuit test terminal. The internal circuit test terminal 500 is connected to the controller 300. The controller 300 may further include a routine for responding to a test request signal input through an internal circuit test terminal, in addition to a data transmission / reception operation with an external host and a data read / write operation with respect to the semiconductor memory device 200. .

For example, the internal circuit test terminal 500 may include an external GPIO pin, an external general purpose input / output pin, a terminal for a normal operation mode and a test mode, a terminal for system reset, and an external clock input. It may be provided with a terminal for. When a request signal for analysis and test is sent through the internal circuit test terminal 500, the recognition signal is received from the internal circuit block of the controller 300, and the abitration of the signal is performed. In addition, a data interface with each of the internal blocks of the controller 300 and the memory device 200 (for example, NAND flash) can be performed. In this state, when each prepared command is sent through the internal circuit test terminal 500, read / write is possible in the memory device 200, and the controller 300 state, the internal clock state, and the memory device 200 are transmitted. With respect to the state, etc., various tests that are not possible through the host interface 100 can be performed.

Thus, the terminal for internal circuit test makes it possible to determine the abnormality of the semiconductor memory element or the controller inside the SSD without passing through the host interface terminal. In addition, the internal circuit test terminal makes it possible to grasp the state of the semiconductor memory element or the state of the controller which cannot be discriminated through the host interface terminal. In addition, when an error occurs in the external host system equipped with the SSD of the present invention (accordingly, it is determined whether the normal connection function of the external host and the SSD does not work or the connection function of the external host and the SSD is normally operated. If not), it is possible to easily determine whether the error of the external host system is due to the SSD by grasping the state of the SSD by using the internal circuit test terminal. This determination cannot be performed via the host interface.

SSD of the present invention can be used as a general-purpose data storage device replacing the existing hard disk. In particular, it can be usefully applied to an ultra-mobile PC (UMPC) or mobile internet device (MID) system that requires a small form factor. It can also be applied to systems requiring extreme reliability in high temperature / high humidity thermal stress environments. It can also be applied to embedded systems.

1 is a cross-sectional view schematically showing an SSD in the form of a single package according to an embodiment of the present invention.

2 is a block diagram of one embodiment of an SSD of the present invention further including an internal circuit test terminal.

3 is a bottom view illustrating an example of an arrangement method of a host interface terminal of an SSD of the present invention.

Figure 4 is a bottom view showing another example of the arrangement of the host interface terminal of the SSD of the present invention.

Claims (8)

A host interface in the form of LGA or BGA for connection with an external host; At least one semiconductor memory device; And And a controller electrically connected to the host interface and the semiconductor memory device to control data transmission / reception with an external host and data read / write operations with respect to the semiconductor memory device. The SSD of claim 1, wherein the number of terminals of the host interface is determined according to a host interface communication protocol. 3. The SSD of claim 2, wherein the host interface communication protocol is IDE, EIDE, SATA, SCSI, SAS or CompactFlash. The SSD of claim 1, wherein the semiconductor memory device is a nonvolatile memory. The SSD of claim 1, wherein the semiconductor memory device is mounted in the form of a bare chip. The SSD of claim 1, wherein the semiconductor memory devices are mounted in a stacked arrangement. The SSD of claim 1, further comprising a resin sealing part to block the semiconductor memory device and the controller from an external environment. SSD of a single package form, characterized in that it further comprises an internal circuit test terminal.

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