KR20100114625A - Semiconductor memory apparatus with pseudo folded bit line structure and manufacturing method thereof - Google Patents

Abstract

PURPOSE: A semiconductor memory device with a will-folded bit-line structure and a method for manufacturing the same are provided to obtain the stabilized operation and the reliability of the semiconductor memory device by maintaining the potentials of upper electrodes in adjacent cell mats. CONSTITUTION: Local bit-lines(213) and local bit-line bars of memory cells which are formed in adjacent two cell-mats share one sense-amplifier. The memory cells sharing one sense-amplifier include an upper electrode(227) which is composed of one wiring without disconnection. The gate electrode of the memory cell is embedded into a semiconductor substrate. A global bit-line is formed on the lower wiring layer of the upper electrode.

Description

Semiconductor Memory Apparatus with Pseudo Folded Bit line Structure and Manufacturing Method Thereof}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor device having a pseudo folded bit line (PFBL) structure and a method of manufacturing the same.

The bit line structure of a semiconductor memory device may be classified into a folded bit line structure and an open bit line structure. The folded bitline structure is somewhat less integrated, but has excellent operational stability because it uses bitline signals and bitline-bar signals within the same cell mat.

The open bitline structure has a bit line connected to one memory cell and a bit line-bar connected to different sense amplifiers, and because of the high integration density, the bit line-bar is extended from another cell block. This exists. In addition, the open bit line structure has a disadvantage in that the number of sense amplifiers increases because adjacent cell mats share the bit line sense amplifiers.

In order to solve this disadvantage, a pseudo folded bit-line (PFBL) structure has recently been proposed.

The pseudo folded bit line structure combines the advantages of the open bit line structure with the advantages of the folded bit line structure, so that the cell mat configuration is the same as the open bit line, while the two cell mats combine one bit line sense amplifier block. Share it. The bit line and sense amplifier of each cell mat are controlled on and off by a switch.

1 is a schematic cross-sectional view of a semiconductor memory device having a general pseudo folded bit line structure.

The process of the semiconductor memory device illustrated in FIG. 1 will be briefly described. Cell regions A1 and A2 and a peripheral region B are defined in the semiconductor substrate 101 on which the device isolation layer 103 is formed. Then, the transistors 105 and 107 and the junction regions S and D are formed on the semiconductor substrate 101 in the cell regions A1 and A2 and the peripheral region B. FIG. Here, the first cell area A1 and the second cell area A2 operate as respective cell mats. In addition, the transistor 107 formed in the peripheral region B operates as a switch for electrically connecting or disconnecting the global bit line to which the local bit line is connected and the sense amplifier.

Next, the first interlayer insulating film 109 is formed over the entire structure, and the designated region is patterned to form bit line contacts 111 and 111A, while the designated region of the first interlayer insulating film 109 is patterned to form a junction region. (D in cell region A1, S) in cell region A2. A storage node contact 117 is formed. Subsequently, the local bit line 113 is connected to the junction region (S of the cell region A1, S, D of the peripheral region B, and D of the cell region A2) through the bit line contacts 111 and 111A. ).

Subsequently, the second interlayer insulating layer 115 is formed on the entire structure, and the second interlayer insulating layer 115 is patterned to expose the storage node contact 117 to form the storage node 119, and then the cell region A1. The upper electrode 121 is formed on A2.

Thereafter, the third interlayer insulating layer 123 is formed on the entire structure, and the metal contact 125 is formed to be connected to the local bit line 113 formed to be connected to the junction region S of the peripheral region B. The global bit line 127 is formed on the metal contact 125.

In this structure, each cell mat is connected to or separated from the sense amplifier through a switch formed in the global bit line 127 and the peripheral area B. FIG.

However, in the current pseudo folded bit line structure semiconductor memory device, since the global bit line 127 is formed after the upper electrode 121 is formed, the upper electrode 121 is manufactured to be separated between adjacent cell mats. .

Therefore, a potential difference between the upper electrodes 121 may occur between adjacent cell mats, and noise may occur to cause a malfunction of the memory device.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a semiconductor memory device having a pseudo folded bit line structure and a method of manufacturing the same, which can maintain the upper electrode potential between adjacent cell mats at the same level. have.

In the semiconductor memory device having a pseudo-folded bit line structure according to an embodiment of the present invention for achieving the above technical problem, the local bit line and the local bit line-bar of a memory cell formed on two adjacent cell mats have one sense amplifier. A semiconductor memory device having a pseudo folded bit line structure that shares a semiconductor memory device, wherein the memory cell sharing the sense amplifier includes an upper electrode formed of one wire without disconnection.

Meanwhile, a semiconductor memory device having a pseudo folded bit line structure according to another embodiment of the present invention may include a plurality of cell mats including unit memory cells connected between a word line and a local bit line; A sense amplifier block including a sense amplifier to which a local bit line and a local bit line-bar of each memory cell formed in two adjacent cell mats are commonly connected; A switch formed between two adjacent cell mats; At least one global bit line electrically connecting or disconnecting the local bit line and the sense amplifier by the switch, wherein the upper electrodes of the memory cells sharing the sense amplifier are connected by one wire without disconnection. do.

Meanwhile, a method of manufacturing a semiconductor memory device having a pseudo folded bit line structure according to an embodiment of the present invention may include providing a semiconductor substrate having a peripheral region defined between two adjacent cell regions; Forming a substructure including a transistor on the semiconductor substrate; And forming an upper electrode formed of one wiring layer on the lower structure without disconnection between two adjacent cell regions.

According to the present invention, in a semiconductor memory device having a pseudo folded bit line structure, the upper electrodes between adjacent cell mats are connected to each other, whereby generation of bit line noise can be suppressed.

Accordingly, stable operation and reliability of the semiconductor memory device can be secured.

In the present invention, since the upper electrode is formed and then the global bit line is formed, the upper electrode between adjacent cell mats is separated, so that a potential difference occurs. Therefore, the global bit line is first formed, and then the upper electrode is formed. present.

In this case, a wiring layer for forming the global bit line before the upper electrode is required. For this, a buried gate electrode is introduced. Hereinafter, a method of manufacturing a semiconductor memory device in which a gate electrode is buried and upper electrodes between adjacent cell mats are interconnected will be described. However, the present invention is not limited thereto, and the shape of the gate electrode may be adopted in a preferred form according to the form or use of the memory device.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a configuration diagram of a semiconductor memory device having a pseudo folded bit line structure according to the present invention.

As illustrated, a semiconductor memory device having a pseudo folded bit line structure according to the present invention includes a plurality of cell mats including a plurality of memory cells 12 formed between a word line WL and a local bit line LBL. 10-1, 10-2). The local bit line LBL of each memory cell 12 formed in each cell mat 10-1, 10-2 is connected to the global bit line GBL.

Although not shown, a switch may be formed between the local bit line LBL and the global bit line GBL to access the selected memory cell 12.

Meanwhile, in order for the local bit lines LBL formed on two adjacent cell mats 10-1 and 10-2 to share one sense amplifier SA, the global bit line GBL is formed by the switch 30. It has a structure that is connected to or separated from the sense amplifier SA.

3 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention. 3 to 5 illustrate two adjacent cell mats and one memory cell formed on each cell mat, and a switch for determining whether a memory cell and a sense amplifier are connected to each other.

First, as shown in FIG. 3, an element isolation film 203 is formed in a designated region on the semiconductor substrate 201 to distinguish between the cell region and the peripheral region. 3 illustrates a state in which the first cell region CM1 as the first cell mat, the second cell region CM2 as the second cell mat, and the peripheral region P are separated by the device isolation layer 203.

Subsequently, buried transistors 205 and 207 are formed in the semiconductor substrate 201 in the cell regions CM1 and CM2 and the peripheral region P. FIG. Here, although the transistors 205 and 207 are formed in a buried type, the present invention is not limited thereto.

Next, a first interlayer insulating film 209 is formed over the entire structure, and the designated region is patterned to form first bit line contacts 211 and 211A. The local bit line 213 is formed to be connected to the first bit line contacts 211 and 211A.

Next, referring to FIG. 4, the second interlayer insulating film 215 is formed on the entire structure in which the local bit line 213 is formed, and the transistor 207 formed in the peripheral region P, that is, the junction region of the switch is connected. The second bit line contact 217 is formed as much as possible.

In addition, a global bit line 219 is formed in a designated portion on the second interlayer insulating layer 219 to be electrically connected to the second bit line contact 217.

Subsequently, as illustrated in FIG. 5, the designated region of the second and first interlayer insulating layers 215 and 209 is patterned to form a storage node contact 221, and the third interlayer insulating layer 223 is formed on the entire structure. Form. After the designated portion of the third interlayer insulating layer 223 is removed to expose the surface of the storage node contact 221, the storage node 225 is formed. Next, an upper electrode 227 is formed on the third interlayer insulating layer 223 to be connected to the storage node 225.

Although the storage node 225 appears to penetrate the global bitline 219 in the drawing, this is merely expressed to overlap for convenience of description. That is, it is noted that the storage node 225 is actually disposed behind the global bitline 219 and the storage node 225 and the global bitline 219 are not electrically contacted.

As shown in FIG. 5, in the present invention, the upper electrode 227 is connected between adjacent cell mats. Therefore, the upper electrode 227 formed between the adjacent cell mats may maintain the same potential.

In addition, since the transistors acting as the memory cells and the switches are buried, it is possible to prevent the addition of the wiring layer while forming the global bit line 219 before forming the upper electrode 227.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

Recent semiconductor memory devices are configured in the form of pseudo-folded bit lines in consideration of the degree of integration and stability of operation. In this type of semiconductor memory device, the upper electrodes between adjacent cell mats have the same potential, so that noise can be reduced and stable operation can be ensured.

1 is a schematic cross-sectional view of a semiconductor memory device having a general pseudo folded bit line structure;

2 is a configuration diagram of a semiconductor memory device having a pseudo folded bit line structure according to the present invention;

3 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device in accordance with an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

201: semiconductor substrate 205, 207: transistor

213: local bit line 219: global bit line

225: storage node 227: top electrode

Claims (11)

A semiconductor memory device having a pseudo folded bit line structure in which a local bit line and a local bit line-bar of a memory cell formed in two adjacent cell mats share a sense amplifier. And the memory cell sharing the sense amplifier includes an upper electrode formed of one wire without disconnection. The method of claim 1, And a gate electrode of the memory cell is buried in a semiconductor substrate. The method according to claim 1 or 2, The semiconductor memory device may further include a global bit line formed in a lower wiring layer of an upper electrode. The method of claim 3, wherein And the global bit line is formed on an upper wiring layer of the local bit line. A plurality of cell mats including unit memory cells connected between a word line and a local bit line; A sense amplifier block including a sense amplifier to which a local bit line and a local bit line-bar of each memory cell formed in two adjacent cell mats are commonly connected; A switch formed between two adjacent cell mats; And at least one global bit line electrically connecting or disconnecting the local bit line and the sense amplifier by the switch. And an upper electrode of the memory cell sharing the sense amplifier is connected by one wire without disconnection. The method of claim 5, And the upper electrode is formed on a lower wiring layer of the global bit line. The method of claim 6, And the global bit line is formed on an upper wiring layer of the local bit line. The method of claim 7, wherein And a gate electrode of the memory cell is buried in a semiconductor substrate. Providing a semiconductor substrate having a peripheral region defined between two adjacent cell regions; Forming a substructure including a transistor on the semiconductor substrate; Forming an upper electrode formed of one wiring layer on the lower structure without disconnection between two adjacent cell regions; A method of manufacturing a semiconductor memory device having a pseudo folded bit line structure. The method of claim 9, The forming of the substructure may include forming a transistor in a semiconductor substrate in the cell region and a peripheral region; Forming a local bit line in communication with the transistor; Forming a global bit line on the local bit line, the global bit line being connected to a transistor formed in the peripheral region; And Forming storage nodes connected to transistors formed in the cell region, respectively; A method of manufacturing a semiconductor memory device having a pseudo folded bit line structure. The method of claim 10, And the transistor is formed in a semiconductor substrate buried type. A method of manufacturing a semiconductor memory device having a pseudo folded bit line structure.

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