KR20100111173A - Flash memory device - Google Patents

Flash memory device Download PDF

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Publication number
KR20100111173A
KR20100111173A KR1020090029601A KR20090029601A KR20100111173A KR 20100111173 A KR20100111173 A KR 20100111173A KR 1020090029601 A KR1020090029601 A KR 1020090029601A KR 20090029601 A KR20090029601 A KR 20090029601A KR 20100111173 A KR20100111173 A KR 20100111173A
Authority
KR
South Korea
Prior art keywords
data
page
logical value
constituting
flipped
Prior art date
Application number
KR1020090029601A
Other languages
Korean (ko)
Inventor
이준
Original Assignee
엘지전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지전자 주식회사 filed Critical 엘지전자 주식회사
Priority to KR1020090029601A priority Critical patent/KR20100111173A/en
Publication of KR20100111173A publication Critical patent/KR20100111173A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Abstract

The present invention discloses a flash memory device which generates an error correction code for a flipping flag and data, thereby minimizing an error of data to be stored.

Description

Flash memory device

The present invention relates to a flash memory device.

The flash memory device has a reduced lifespan in proportion to the number of programs of the memory module. The flash memory device deletes a block in which data is written in order to program the data, and programs the data in units of pages after the block is deleted.

In general, an SLC flash memory may be programmed 100,000 times, and an MLC flash memory device may be programmed about 10,000 times. Therefore, in order to increase the life of the flash memory device, all the blocks of the memory module constituting the flash memory device must be used equally, and wear is also generally equalized.

Flipping technology has been proposed as a method of increasing the life of a memory module from the viewpoint of wear leveling.

When a flash memory device is connected to a host (for example, a personal computer) and used as a storage device, the flipping technology inquires bit-by-bit data that the host requests recording, and if there is a large number of logical "1s", it writes the memory module as it is. Conversely, if there are many logic "0s", the data is inverted to minimize the number of programming of the cells constituting the memory module. Typically, a cell of a flash module has a logic "0" when writing data, has a state of logic "1" when not writing, and can increase the life of the cell itself, independent of wear leveling.

However, there is no guarantee of the integrity of the flipping flag indicating whether data is flipped or not when applying the flipping technique to increase the lifetime. If an error occurs in the data stored in the flipping flag, the controller of the flash memory device does not know whether the inverted data is normal data or the non-inverted data is normal data, so that the recorded data itself is meaningless.

SUMMARY OF THE INVENTION An object of the present invention is to generate and utilize an error correcting code for flipping data stored in a flash memory device independently of the flipping flag and the data or together with the flag and the data. The present invention provides a flash memory device that minimizes errors.

According to the present invention, a memory module for recording data in units of pages, and data constituting the page according to the logical value superiority of the data constituting the page, the flipped data and the This is achieved by a control unit that generates an error correction code for each flag indicating whether it is flipped and writes the same to the memory module.

According to the present invention, a memory module for recording data in page units, and data constituting the page according to a logical value superiority of data constituting the page, and a flag indicating whether data is flipped or not Is achieved by a control unit that generates an error correction code for and writes it to the memory module.

The present invention minimizes an error in data stored in a flash memory device by generating an error correction code for the flipping flag and the data when the data of the flash memory device is flipped.

The flash memory device described herein may be a flash memory device using a NAND gate or a NOR gate.

The present invention is not affected by the type of memory cell used. Therefore, since the memory cell mentioned in the present invention is applicable to a flash memory chip of a NAND gate or a NOR gate type, it will not be described separately.

In addition, in the following description, the controller for controlling the memory cell and the part driving in conjunction with the controller are referred to as a controller, and a "module" or a "unit" may be used as a suffix to components constituting the controller. Accordingly, the controller may be formed as a single chip or a plurality of chips may form one component.

Components used in the present specification, and suffixes thereof are given only in consideration of ease of preparation of the present specification, and the "module" and "unit" may be used interchangeably.

The "flash memory device" described herein may be implemented as a solid state disk (SSD) or may serve as a nonvolatile storage medium in an embedded device.

Various devices for storing personal computers, servers, notebook computers, personal digital assistants (PDAs), personal media players (PMPs), video game machines, mobile phones, and other data storage devices that can be connected to the flash memory device are described herein. Host ".

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram of a memory module constituting a flash memory device according to the present invention.

Referring to FIG. 1, a memory module includes a unit cell, in which unit cells are gathered to form one page, and a plurality of pages are gathered to form one block.

In the drawing, a page indicates that a plurality of cells are arranged in a horizontal direction, and corresponds to a basic unit in which the controller programs data. However, in order to record data on one page, the entire block must be erased, and the block to be erased is determined by leveling the wear.

Each cell has a state of logic "1" and, when writing data, has a state of logic "0". In other words, when writing data into a cell, the cell is changed to a logic " 0 ", otherwise the state of the logic " 1 " is maintained.

The flipping method of the present invention is performed in units of pages. When the number of logical values of each cell constituting one page is mainly "0", flipping is performed. On the contrary, when the number of logical values of each cell is "1", flipping is not performed.

For example, when there are 10 cells constituting the page, and the logical value of data to be written in seven cells among them is logical "0", flipping can be performed.

2 is a conceptual diagram illustrating a flipping method to be applied in the present invention.

Referring to FIG. 2, when the bit string of data to be written on page a (page-a) is 00010 and the bit string of data to be written on page b (page-b) is 01111, page a (page-a) Corresponds to a page performing flipping, and page b corresponds to a page not performing flipping.

Here, the illustrated page (page-a, page-b) represents only five cells for convenience of explanation and understanding, in practice, one page has a size of 16k bit to 32k bit, one block It consists of 64 pages.

3 is a conceptual diagram of a flash memory device according to the present invention.

Referring to FIG. 3, a flash memory device according to the present invention includes an interface unit 110, a buffer 120, a controller 130, and a memory module 140.

The interface unit 110 performs data communication with the host 50, provides data to which the host 50 requests recording to the buffer 120, and transmits data transmitted from the control unit 130 through the buffer 120. To the host 50. In addition, the interface unit 110 receives a command transmitted from the host 50 and applies it to the controller 130 through the buffer 120 so that the controller 130 processes in response to the command of the host 50. .

The interface unit 110 receives data from the host 50 in units of 512 bytes, and transmits data to be transmitted from the controller 130 to the host 50 in units of 512 bytes.

The controller 130 obtains data requested by the host 50 through the interface unit 110 in units of 512 bytes, and counts a logical value of each bit constituting the obtained data.

The controller 130 determines whether the logic value of each counted bit is mainly composed of logic "1" or logic "0". As a result of the determination, when the data acquired in units of 512 bytes is mainly composed of logic "0", the controller 130 flips 512 bytes of data and sets a flipping flag value indicating whether to flip 512 bytes of data. .

If 512 bytes of data consist of "00010010 ....., 0",

The form of the flipped data has a form of "11101101 ....., 1", and the flipping flag value may be set at the end of the data or the header of the block.

The controller 130 may generate an error correction code for the flipped data and the flipping flag, or generate an error correction code for the flipped data and the flipping flag. This will be described with reference to FIGS. 4 and 5 together.

4 conceptually illustrates how the controller of FIG. 3 performs flipping.

Referring to FIG. 4, the controller 130 analyzes data requested to be recorded from the host 50, and determines which logical value of logic “1” and logic “0” is more. When data is organized around logic "0", data is flipped.

After the data is flipped, the controller 130 generates an error correction code for the flipped data, and similarly generates an error correction code for the flipping flag.

Next, referring to FIG. 5, the controller 130 analyzes the data to determine whether there is more logic "1" or more logic "0", and when there are more logic "0", the data ( data). At this time, the controller 130 generates an error correction code for the flipped data and the flipping flag. Accordingly, the controller 130 performs a process of generating an error correction code separately for the data and the flipping flag at once, thereby reducing the time required for the flipping process and simplifying the flipping process. Can be.

In FIG. 3, when data requested for recording by the host 50 is provided to the buffer 120 through the interface unit 110, the data requested for recording is stored in the buffer 120. At this time, the controller 130 analyzes the logic values constituting the data stored in the buffer 120 and counts whether the number of logic "1" is large or the number of logic "0" is large. The controller 130 records the counted result in the data stored in the buffer 120. In FIG. 3, "1" or "0" is displayed as a flipping flag on one side of the data stored in the buffer 120.

Since the hexadecimal "0X1234567800000000" of the data stored in the buffer 120 has 13 logical values "1" and 51 logical values "0", the flipping flag is set to "1" and the data is inverted. Indicates that it should.

Among the data stored in the buffer 120, the hexadecimal number "0XFFFFFFFF4FFFFFFF" is set to "0" because the logical value "1 is 57 and the logical value" 0 "corresponds to seven. That is, the data" 0XFFFFFFFF4FFFFFFF " Does not need to invert the data.

The controller 130 determines data to be inverted, that is, data to be flipped, and displays the result in the data stored in the buffer 120. Thereafter, error correction coding is performed on the data stored in the buffer 120, and the data on which the coding is performed is stored in the memory module 140.

If the host 50 requests data stored in the memory module 140, the controller 130 reads the data stored in the memory module 140, performs error correction decoding, and then decodes the decoded flipping flag. With reference to the error correction, it is determined whether to inversion or non-inversion of the decoded data. If the error correction decoded data has a value of "1", the controller 130 inverts the error correction decoded data, otherwise, non-inverts and transmits the data to the buffer 120. The data temporarily buffered in the buffer 120 is transmitted to the host 50 in units of 512 bytes through the interface unit 110.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a conceptual diagram of a memory module constituting a flash memory device according to the present invention;

2 is a conceptual diagram illustrating a flipping method to be applied in the present invention;

3 is a conceptual diagram of a flash memory device according to the present invention, and

4 and 5 conceptually illustrate how the controller of FIG. 3 performs flipping.

Explanation of symbols on the main parts of the drawings

110: interface unit 120: buffer

130: control unit 140: memory module

Claims (8)

A memory module for recording data in page units; And The data constituting the page is flipped according to the logical value superiority of the data constituting the page, and an error correction code is generated for each of the flipped data and a flag indicating whether the data is flipped and written to the memory module. And a controller for controlling the flash memory device. The method of claim 1, The control unit, Counting the logical value of each bit constituting the page, And as a result of the counting, when the first logical value of each bit constituting the page is larger than the second logical value, data constituting the page is flipped. The method of claim 2, The control unit, And, when the first logical value of each bit constituting the page is less than the second logical value as a result of the counting, data constituting the page is flipped. The method of claim 3, The first logical value is, And a second logic value is a logic value " 1 ". A memory module for recording data in page units; And And a controller configured to generate an error correction code for the data constituting the page and a flag indicating whether to flip the data according to a logical value superiority of the data constituting the page, and to write the error correction code to the memory module. Characterized in that a flash memory device. The method of claim 5, The control unit, Counting the logical value of each bit constituting the page, And as a result of the counting, when the first logical value of each bit constituting the page is larger than the second logical value, data constituting the page is flipped. The method of claim 2, The control unit, And, when the first logical value of each bit constituting the page is less than the second logical value as a result of the counting, data constituting the page is flipped. The method of claim 7, wherein The first logical value is, And a second logic value is a logic value " 1 ".
KR1020090029601A 2009-04-06 2009-04-06 Flash memory device KR20100111173A (en)

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KR1020090029601A KR20100111173A (en) 2009-04-06 2009-04-06 Flash memory device

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