KR20100092230A - Static branch prediction method for pipeline processor and compile method therefor - Google Patents

Abstract

PURPOSE: A static branch prediction method for a pipeline processor and a compile method thereof are provided to properly process a small control unit having a small sized block by excluding the use of a delay slot. CONSTITUTION: A conditional branch code is predicted in a taken or not-taken format(S10). The codes within a block are scheduled by converting the conditional branch into a jump target address setup code and a test code, wherein the jump target address setup code includes target address information and branch timing information(S20). If the conditional code is predicted in the taken format, the target address indicated by the target address information is fetched to a cycle time indicated by thee branch timing information(S30).

Description

Static branch prediction method for pipeline processor and compile method therefor}

The present disclosure relates to a processor for executing instructions, and more particularly to a pipeline processor.

In a pipeline processor, one instruction is divided into several steps. For example, the instruction processing process may be divided into a fetch stage, a decode stage, an execute stage, a memory stage, and a write stage. In the pipeline processor, a plurality of instructions can be executed while sequentially passing each step of the pipeline in an overlapped form, thereby enabling high-speed processing of a program.

One of the factors affecting the performance of a pipeline processor is a 'branch hazard' or a 'pipeline control hazard'. Branch hazards indicate that branch instructions slow down the processing of a pipeline processor. In a pipeline processor, a branch instruction may degrade the performance of the pipeline processor because the address of the next instruction to be fetched is not known until the decode phase of the branch instruction is completed or the execution phase is performed. In order to eliminate the branch hazard of the pipeline processor, much research is being conducted, and techniques such as dynamic branch prediction, delayed branch, and static branch prediction have been proposed.

Meanwhile, the reconfigurable processor accelerates and computes loops with a lot of data operations in a coarse grained reconfigurable array (CGA) while the control part controls a VLIW (Very Long Instruction). Word) Run on the machine. The control part is generally characterized by a small basic block (BB) and a simple data flow. In a VLIW machine, the execution schedule of instructions is determined outside the processor by a compiler, which is software, and the execution schedule in the processor is fixed, thereby simplifying the hardware.

Among the methods for mitigating the aforementioned branch hazards, the dynamic branch prediction method takes predictions with take or not-taken for the conditional branch instruction in view of past history during execution of the program. It is a technique. This dynamic branch prediction method requires a lot of hardware to solve the branching problem, so it is not suitable as a method for eliminating the pipeline control hazard of the VLIW machine requiring a simple hardware configuration. The delayed branching method, which fills delayed slots with conditional branch operations and dependencies, also applies to VLIW machines that handle small numbers of instructions mainly because of the small size of the base block (BB). Not suitable for

The static branch prediction method is a method in which a branch prediction of a taken or not-taken for a conditional branch instruction is already determined before executing a program. According to the existing static branch prediction method, the delay slot is not used when predicting by sickle-taking, but the delay slot is included after the branch instruction when predicting by taken. Therefore, the existing static branch prediction method has some limitations to be applied to VLIW machines. In addition, according to the existing static branch prediction method, not only a lot of information (data) is required to perform a branch operation, but also a lot of work (such as a comparison process and a branch process) is performed, so that the encoding space ( may result in a lack of encoding space.

A static branch prediction method and apparatus for improving the performance by reducing or eliminating the control hazard of a pipeline processor and a compilation method thereof are proposed. In particular, a static branch prediction method and apparatus for a pipeline processor suitable for high-speed processing of a program having a small number of instructions included in a basic block BB, and a compilation method for the same are proposed.

In addition, we propose a static branch prediction method and apparatus and a compile method for the pipeline processor, which require less hardware addition and do not need to use delay slots even when predicted as a take. In particular, a static branch prediction method and apparatus and a compilation method therefor are proposed to prevent the occurrence of a lack of encoding space when processing a branch instruction.

In a static branch prediction method for a pipeline processor according to an embodiment, predicting a conditional branch code with a taken or sickle-taked, and setting the jump target address including the conditional branch code with target address information and branch timing information Converting the code and the test code to schedule codes in the block, wherein the test code is scheduled in the last slot of the block and the jump target address setting code is scheduled in an empty slot after all other codes in the block are scheduled; And fetching a target address indicated by the target address information at a cycle time indicated by the branch timing information when predicted by the take in the predicting step.

According to another exemplary embodiment, a code compilation method for static branch prediction may include converting a conditional branch code into a jump target address setting code and a test code including target address information and branch timing information, and the test code and the jump target. Scheduling all codes in a block that includes an addressing code, wherein the scheduling step schedules the test code to the last slot of the block and the jump target addressing code also schedules all other codes in the block. Then schedule it into an empty slot.

In another aspect, a code execution method for a pipeline processor includes converting a conditional branch code into a jump target address setting code including target address information and branch timing information, and after scheduling all other codes in the block. Scheduling the jump target address setting code in an empty slot, and fetching a target address indicated by the target address information at a cycle time indicated by the branch timing information.

According to one embodiment, there is no need to use delay slots while using a static branch prediction method that can reduce the burden of hardware addition. Therefore, it is suitable for the processing of control parts, etc., where the basic block size is small, and is suitable for application to a VLIW machine. In addition, since the cycle time required to process the basic block can be shortened compared to the conventional method, the processor can not only improve performance and speed, but also simplify the compiler. In addition, it is possible to schedule a jump target address setting (JTS) instruction in an empty slot after all other instructions in the basic block are scheduled, so that the schedule quality is high, and a large amount of encoding space is not required to process the conditional branch instruction.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; In describing the aspects of the present invention, if it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the embodiments of the present invention, which may vary according to intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

1 is a flowchart illustrating a static branch prediction method according to an embodiment. 1 illustrates a case in which a conditional branch instruction or code is included in a source code of an instruction register (IR).

Referring to FIG. 1, first, a conditional branch operation is predicted as taken or not-taken (S10). 1 shows a case of predicting with a take, which is merely exemplary. There is no restriction on the algorithm used when predicting to take or not-take. For example, the same algorithm as that used in the existing static branch prediction method may be used, such as predicting all with taken or not-taken or making profile based prediction. The result of step S10, the prediction information, that is, whether information predicted by take or not-taken is added to each conditional branch instruction in the scheduling step or the compilation process (S20), which will be described later.

Subsequently, the conditional branch instruction is converted into a jump target address setting (JTSc) code and a test code, and then the codes in the instruction register (IR) are scheduled (S20). ). Here, the names of the jump target address setting (JTSc) code and the test code are arbitrary, and other names that perform the same function and include the same information may be used instead. The scheduling process is a process of rearranging codes in each instruction register (IR) or each basic block (BB) in order of execution and may be part of a process of compiling the instructions. In the case of a processor having one pipeline, one instruction register IR may be compiled using one processing block, but in superscalar structures, it may be compiled into a plurality of processing blocks.

The JTSc code (where 'c' represents 'conditional') includes target address information and branch time information, and may also include prediction information. The names of the information used here are exemplary. The target address information may be address information of the target block to be executed when the take is selected in the conditional branch operation (that is, when the prediction is correct or when the prediction is correct or when the prediction is not correct when the prediction is the take). The branch timing information is information indicating when a branch occurs, and may be, for example, a value indicating how many cycles a test code comes after. The prediction information is information indicating whether or not predicted by taking or sickle-taking in step S10, and may be set to any value indicating the taken (t) or sickle-taken (n). Such prediction information may be a hint used when comparing test results in a test operation.

The test code or the test instruction is for checking whether the prediction in step S10 is correct, and may be, for example, an instruction having the same function as a compare instruction. In order to execute a test command, the execution result of another command is required, so the test command depends on the execution result of other commands. Thus test instructions are typically scheduled to be processed last in the block.

FIG. 2 is a flowchart illustrating an example of an instruction scheduling process or a process of compiling codes of an instruction register IR in operation S20 of FIG. 1.

Referring to FIG. 2, first, prediction information is added to a conditional branch instruction (S21). The prediction information is information representing a prediction result in step S10 of FIG. 1 and may be information indicating a taken t or a sickle-taken n. The conditional branch instruction including the prediction information is separated into a JTSc code and a test code (S22). As described above, among the information included in the conditional branch instruction, the information for the comparison operation is included in the test code, and the target address information and the like are included in the JTSc code. In addition to the target address information, the JTSc code may also include prediction information inserted in step S21 together with branch timing information (eg, a value indicating how many cycles a test code comes out).

The JTSc code, the test code, and other instructions included in the block are arranged in the order of execution (S23). In this case, other instructions except JTSc code can be scheduled first in a conventional manner. Here, the conventional scheme may be an instruction scheduling method when the conditional branch instruction is not divided into JTSc code and test code in the conventional static branch prediction method. For example, in the conventional manner (using delay slots), a branch instruction is inserted after a compare instruction. By inserting delay slots after the branch instruction, other instructions that are not dependent on the comparison instruction can be scheduled to be arranged in the delay slot.

However, in this embodiment where the conditional branch instruction is divided into JTSc code and test code, the test code that depends on other instructions in the block is executed last in the block. After all other commands have been scheduled, the execution order of the JTSc code is determined last. As mentioned above, since JTSc code is not dependent on other instructions, not only can it be scheduled at the latest, but also there are few restrictions on the arrangement position. The JTSc code includes general information on the address of the block to be fetched next to the current block when branching by a conditional branch instruction. This information, as early as possible, helps to eliminate or reduce branching hazards in pipeline processors. Therefore, in the present embodiment, the JTSc code can be scheduled so that the JTSc code can be executed from the front. For example, the JTSc code may be placed in the nop slot at the front of the slots allocated as the nop slot in the existing scheduling method (ie, step S22).

Subsequently, referring to FIG. 1, instructions are sequentially fetched and executed according to a scheduled order (S30). In the case of predicting the take in step S10, as shown in FIG. 1, after the page of the test code, the JTSc code is also added to the JTSc code in a cycle indicated by the branch timing information included in the JTSc code (for example, after the fetch of the test code). The address of the block indicated by the included target address information may be fetched. On the other hand, when predicted as sickle-taked in step S10, after fetching the test code, instructions of the next block of the current block (test code) may be sequentially fetched.

The fetch of instructions based on this prediction may be started immediately after fetching the test code until the decode phase of the test code is terminated or whether the prediction is correct by the execution step. According to this, even when predicted as a take in step S10, it is not necessary to use the delay slot after the test code or minimize the use of the delay slot. This is because, in the present embodiment, even if the test code is not decoded and executed, the target address and branch timing to be branched can be known in advance by first executing the JTSc code separated from the conditional branch instruction.

Then, the test code of the corresponding block is executed to process the fetched instructions as it is or according to the prediction in step S10, or to flush the fetched instructions after the test code (S40). That is, if the prediction in step S10 is correct, the instructions are executed as they are fetched in step S30, but if the prediction is not correct, all instructions fetched after the test code are flushed with other addresses (for example, in the corresponding block). Fetches the next block or target address contained in the JTSc code. In order to confirm whether the prediction is correct, prediction information included in the JTSc code may be used.

For example, assume that the prediction is taken in step S10 as shown in FIG. In this case, as a result of performing the execution step of the test code, if the prediction is confirmed to be correct, the instructions of the block indicated by the branch address information included in the JTSc code, that is, the instructions already fetched after the test code Treat it as it is. On the other hand, if the prediction does not match, then all subsequent fetched instructions after the test code are flushed and instead fetches instructions from the next block of the current block.

Hereinafter, the codes shown in FIG. 3 are taken as examples, and the difference between the conventional static branch prediction method and the static branch prediction method of the present embodiment will be described. 3 is an example of codes in an instruction register (IR) that may be executed in a VLIW machine.

FIG. 4A is a diagram of the scheduled, ie compiled, codes of FIG. 3 according to a conventional static branch prediction method, and FIG. 4B is a pipeline stage for some of the codes scheduled in FIG. 4A when the prediction is correct. The figure shows. And FIG. 5A is a diagram of the scheduled, ie compiled, codes of FIG. 3 according to the embodiment described above, and FIG. 5B is a pipeline stage for some of the codes scheduled in FIG. 5A if the prediction is correct. The figure shows. In FIGS. 4B and 5B, F, D, E, M, and W represent a fetch step, a decode step, an execute step, a memory step, and a write step, respectively. . The examples shown are for a superscalar structure that includes two processing blocks, but this hardware configuration is merely illustrative.

Referring to FIGS. 4A and 4B, according to the conventional method, the execution step E of the comparison instruction compare cmp determines whether to branch by comparing the given values r3 and r2. The decode phase (D) of the instruction is known so that the branch target address to be fetched later is known. Therefore, according to the conventional method, the delay slot should be added after the branch instruction. In FIG. 4A, nop is added because no suitable code is inserted into the delay slot. In the illustrated example, it can be seen that the addition of the delay slot takes a total of six cycles to execute the first basic block BB1 and fetches a new target address at cycle time 6.

On the other hand, referring to FIGS. 5A and 5B, the branch target address can be known at cycle time 2, which is the decoding step (D) of the JTSc code, and the third basic address which is the branch address at cycle time 4, which is two cycles later. It can also be seen that the instruction of the block BB3 is fetched. It decodes the test code and executes it so that if the branch prediction is correct, the pipeline processor continues to process the instructions without doing anything. Therefore, according to the illustrated example, it can be seen that it takes 4 cycles to execute the first basic block BB1 and fetches the target address at cycle time 4. This shows that the present embodiment can improve the processing speed and performance of the pipeline processor.

FIG. 5C shows a pipeline stage for some of the codes scheduled for FIG. 5A when the prediction is not correct. Referring to FIG. 5C, as in FIG. 5B, the JTSc code of the first basic block BB1 is decoded to calculate a target address at cycle time 2, and the third basic block BB3 is a new address at cycle time 4 that is two cycles later. Fetch). However, since it is confirmed that the prediction is wrong as a result of executing the test code, all operations fetched from the third basic block BB3 are flushed, and the second basic block BB2, which is a subsequent block, is fetched at cycle time 6.

FIG. 6 is a flowchart illustrating an instruction scheduling method or a compilation method according to another embodiment, in which a source code includes an unconditional branch instruction. The unconditional branch instruction may be, for example, the code 'jump' of the second basic block BB2 in the example shown in FIG. 3, which is merely illustrative.

Referring to FIG. 6, first, an unconditional branch instruction (jump) is converted into a jump target address setting (JTSu) code (S110). Here again, the Jump Target Address Setting (JTSu) code (where 'u' stands for 'unconditional') is arbitrary, and other names that perform the same function and contain the same information may be used instead. .

The JTSu code includes target address information and branch time information. The names of the information used here are exemplary. The target address information may be address information of a target block to be fetched when a branch operation or a jump operation is performed according to an unconditional branch operation. The branch timing information may be information indicating when a branch or a jump occurs. JTSu code differs from conventional jump code in that it includes branch timing information. Prediction information is not needed in executing an unconditional branch instruction.

Subsequently, a schedule for the corresponding block including the JTSu code is performed (S120). The scheduling process is a process of rearranging codes in each instruction register (IR) or each basic block (BB) in an order of execution, and may be part of a compilation process of instructions. In the case of a processor having one pipeline, one instruction register IR may be compiled into one processing block, but in superscalar structures, it may be compiled into a plurality of processing blocks. FIG. 4A shows an example of a result of scheduling according to the present embodiment (second basic block BB2 of FIG. 4A) for the block including the unconditional branch instruction of FIG. 3 (second basic block BB2 of FIG. 3). Is shown.

More specifically, first, other instructions except for the JTSu code are scheduled first (S121). That is, except the JTSu code, other instructions included in the block (eg, the second basic block BB2) are arranged in the order of execution. In this case, the instructions other than the JTSu code are not particularly limited in the scheduling method, and a conventional technique in this field may be applied.

After all other commands are scheduled, the execution order of the JTSu code is determined (S122). JTSu code has little dependence on scheduling because it has no dependencies on other commands. In addition, unlike jump codes, JTSu codes contain branch timing information, and thus have higher flexibility in scheduling than jump codes that should always be executed at the end of the block. That is, the JTSu code can be scheduled so that it can be executed as far in front of the block as possible. For example, the JTSu code may be placed in the nop slot that is the first of the slots allocated to the nop slot in the conventional scheduling method.

According to this present embodiment, it is not necessary to add a delay slot after the JTSu code. According to the conventional method illustrated in FIG. 4B, a delay slot is added even after performing a jump operation on the second basic block BB2 (total execution of the second basic block BB2 takes 5 cycles). . However, when scheduling using a JTSu code that includes branch timing information with target address information, the JTSu code can be arranged in front of the block so that there is no need to add a delay slot separately (second basic). 4 cycles are required to execute block (BB2). Therefore, according to this embodiment, the performance and speed of the pipeline processor can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be construed to include various embodiments within the scope of the claims.

1 is a flowchart illustrating a static branch prediction method according to an embodiment.

FIG. 2 is a flowchart showing an example of an instruction scheduling process in step S20 of FIG. 1.

3 is an example of codes in an instruction register (IR) that may be executed in a VLIW machine.

4A illustrates a result of compiling the codes of FIG. 3 according to a conventional static branch prediction method.

4B shows the pipeline stage for some of the codes scheduled in FIG. 4A when the prediction is correct.

5A illustrates a result of compiling the codes of FIG. 3 according to the static branch prediction method according to the present embodiment.

FIG. 5B shows a pipeline stage for some of the codes scheduled in FIG. 5A when the prediction is correct.

5C shows the pipeline stage for some of the codes scheduled in FIG. 5A when the prediction is not correct.

6 is a flowchart illustrating a command compilation method according to another exemplary embodiment.

Claims (10)

Predicting with taken or sickle-taken for conditional branch codes; The code in the block is scheduled by converting the conditional branch code into a jump target address setting code and a test code including target address information and branch timing information, wherein the test code is scheduled to the last slot of the block and the jump target address setting is also performed. The code schedules an empty slot after all other codes in the block have been scheduled; And And fetching a target address indicated by the target address information at a cycle time indicated by the branch timing information, when predicted by the take in the predicting step. The method of claim 1, If the prediction of the prediction step is correct as a result of the execution of the test code, the processes fetched in the fetching step are processed as it is, and if the prediction is not correct, the method further includes flushing all of the codes fetched in the fetching step. Static branch prediction method for pipeline processors. The method of claim 2, The cycle time indicated by the branch timing information is a cycle time immediately after fetching the test code. The method of claim 2, And a jump target address setting code further includes prediction information of the prediction step, and determining whether the prediction is correct uses the prediction information for a corrected branch prediction method for a pipeline processor. The method of claim 1, Fetching the next block address of the current block after fetching the test code when predicting with sickle-taked in the prediction step; And If the prediction of the prediction step is correct as a result of the execution of the test code, the codes fetched in the fetch step are processed as it is, and if the prediction is not correct, all the codes fetched in the fetch step are flushed and the target address information is And fetching the indicated target address. Converting the conditional branch code into a jump target address setting code and a test code including target address information and branch timing information; And Scheduling all codes in a block including the test code and the jump target address setting code; And in the scheduling step, the test code is scheduled in the last slot of the block, and the jump target address setting code is scheduled in an empty slot after all other codes in the block are scheduled. The method of claim 6, The jump target address setting code further includes prediction information indicating a take or sickle-taken, and the test code further uses the prediction information to predict the code branch. The method of claim 7, wherein Wherein the branch timing information indicates a cycle time for fetching a target block indicated by the target address information when the prediction information indicates a take. The method of claim 8, And a cycle time for fetching the target block is a next cycle time for fetching the test code. Converting the conditional branch code into a jump target address setting code including target address information and branch timing information; Scheduling the jump target address setting code to an empty slot that occurs after scheduling all other codes in the block; And Fetching a target address indicated by the target address information at a cycle time indicated by the branch timing information.

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