KR20100091416A

KR20100091416A - Multi chip packaging device

Info

Publication number: KR20100091416A
Application number: KR1020090010597A
Authority: KR
Inventors: 윤인석
Original assignee: 주식회사 하이닉스반도체
Priority date: 2009-02-10
Filing date: 2009-02-10
Publication date: 2010-08-19

Abstract

The present invention is a multi-layer first dual chip; A second dual chip disposed on the first dual chip and configured as a multilayer; A plurality of signal terminals for providing command and control signals to each of the first and second dual chips and enable signals for enabling the first and second dual chips, respectively, and being connected to each other; A pad for a chip to which an enable terminal is connected; And a plurality of pad signal terminal leads for providing comment and control signals to the first and second dual chips at the plurality of signal terminals of the chip pad, and first and second terminals at the first and second enable terminals. An enable terminal for first and second pads connected through a second enable terminal lead, respectively, and when it is determined that the quality of the first or second dual chip is deteriorated, the first or second enable Provided are a multi-chip package device including a packaging pad configured to block a terminal lead.

Description

Multi chip packaging device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package device, and more particularly, to a multi-chip package device capable of using a 2CE QD-DSP to rescue a top chip manufactured for a QDP-Dual Stack Package. .

With the recent development of the semiconductor industry and the demands of users, electronic devices are increasingly required to be smaller and lighter. One of the technologies applied to satisfy such a demand is a multi chip packaging technology. Multi-chip packaging technology is a technology that configures a plurality of semiconductor chips into one package, and using the multi-chip package to which the technology is applied is more compact, lighter, and more compact than using several packages including one semiconductor chip. It is advantageous.

Memory chips are manufactured in many ways. As mentioned above, as several memory chips are included in a package, a method of selecting chips is diversified.

With the development of memory and high capacity, fast processing speed is required. The proposed method is parallel processing. It is easy to parallelize multiple chips, but there are limitations to parallelizing the high-capacity memory in one package.

When there are multiple memory chips in a package, the chip enable pins are bonded to each other in order to parallelize the chips. The current method is 2CE.

In the case of QDP (Quarter Die Package), which includes four chips, two 2CE schemes are set by configuring a double side package (DSP) with two packages consisting of two chips. This package configuration is called 4CE QD-DSP (QDP-Dual Stack Package).

1 illustrates a pad connection configuration of a multi-chip package device.

Referring to FIG. 1, when constructing a pad for stack chips, the 4CE QD-DSP package uses two 2CE QDP packages, which are one of dual chips, in which several memory chips are configured in a multilayer structure. The chip connected to the chip enable signals CE1 and CE2 becomes the bottom chip, and the chip connected to the third and fourth chip enable signals CE3 and CE4 is the top chip. Top) Corresponds to the chip. More specific stack structure is shown in FIG.

2 shows a stack configuration of a QD-DSP.

The top chip is selected by the third and fourth chip enable signals 3CE and 4CE, and the bottom chip is selected and connected by the first and second chip enable signals 1CE and 2CE.

3 illustrates a pad configuration of the QD-DSP of FIG. 2.

As mentioned earlier, two 2CE QD-DSPs are packaged to create a 4CE QD-DSP. Therefore, the 2CE QD-DSP will be tested using a top chip and a bottom chip, respectively, and will package two 2CE QD-DSPs.

Referring to FIG. 3, the 2CE QD-DSP 200 connected to the top chip in the 4CE QD-DSP may include first and second chip selection pads CE0 # and CE1 # among the control pads PAD. , 350, first and second buffers 310 and 320, and a pad logic unit 330. The pads PAD are bonded to the lead portion 360 of the package.

Only one of the first and second buffers 310 and 320 is enabled. 3 shows a top chip, only the second buffer 320 is enabled, and the first buffer 310 is disabled.

The first buffer 310 buffers the chip enable signal CE1 # or CE2 # input from the first chip select pad 340 and transfers the buffer signal to the memory chip as the first input signal CE0_INT.

The second buffer 320 buffers the chip enable signal CE3 # or CE4 # input from the second chip select pad 350 and transfers the buffer signal to the memory chip as the second input signal CE1_INT.

In the lead portion 360 of the package, the first and second chip enable signal leads CE1 # _R and CE2 # _R are bonded to the first chip select pad 340 and the third and fourth chip enable signal leads. CE3 # _R and CE4 # _R are bonded to the second chip select pad 350.

As described above, when the 2CE QD-DSP 200 used as the top chip in the 4CE QD-DS is made to be used as the top chip, the package device cannot be used. When the bottom chip is deteriorated, the 4CE QD-DSP device cannot be used as a whole, but when the top chip is deteriorated, there is a method of enabling the top chip without the bottom chip to use the 2CE QD-DSP.

However, as mentioned above, in the case of the top chip, the second buffer 320 is enabled. In the case of using the 2CE QD-DSP, the use of the first and second chip enable signals CE1 # and CE2 # is set as a default.

Therefore, the top chip in which only the second buffer 320 is enabled cannot be used because there is no way to receive the first and second chip enable signals CE1 # and CE2 #.

Therefore, the technical problem to be achieved in the present invention is to use the 4CE QD-DSP as a 2CE QD-DSP with only the top chip when the quality of the relatively poor top chip in the 4CE QD-DSP (QDP-Dual Stack Package) is degraded. It is to provide a multi-package device.

Multi-chip package device according to a feature of the present invention,

A first dual chip composed of multiple layers; A second dual chip disposed on the first dual chip and configured as a multilayer; A plurality of signal terminals for providing command and control signals to each of the first and second dual chips and enable signals for enabling the first and second dual chips, respectively, and being connected to each other; A pad for a chip to which an enable terminal is connected; And a plurality of pad signal terminal leads for providing comment and control signals to the first and second dual chips at the plurality of signal terminals of the chip pad, and first and second terminals at the first and second enable terminals. An enable terminal for first and second pads connected through a second enable terminal lead, respectively, and when it is determined that the quality of the first or second dual chip is deteriorated, the first or second enable Packaging pads configured to block the terminal leads.

In the packaging pad, when it is determined that the quality of the first or second dual chip is inferior, the first or second enable terminal lead set by default is cut off to be used as the dual chip packaging device. It is done.

As described above, in the multi-package device according to the present invention, when the top chip is deteriorated in a 4CE QD-DSP (QDP-DSP) operated by four chip enable signals, the top chip is removed and the top chip is removed. Only the chip can be enabled and used like a 2CE QD-DSP, increasing the profitability of the packaging device.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

4 illustrates a pad connection structure of a package device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the chip pad 400 of the 4CE QD-DSP (QDP-Dual Stack Package) according to an embodiment of the present invention includes pads to which control signals or data are input, and includes first and second inputs. 2CE QD-DSP chips including a buffer 410 and 420, a plurality of pads PAD, and a pad logic unit 430, and connected by the chip pad unit 400, have a top and a bottom ( The lead portion 460 is included in the packaging pad connected to the bottom). The 4CE QD-DSP is a dual chip consisting of several layers of memory chips, and the 2CE QD-DSP is composed of a top and a bottom.

In FIG. 4, only the case of using the top chip is shown. Thus, only the second butter 420 is enabled and the first buffer 410 is disabled.

Among the pads are first and second chip select pads CE0 # and CE1 # 440 and 450 to which a chip select signal CE is input. In the lead unit 460, the first and second chip enable signal leads CE1 # _R and CE2 # _R are bonded to the first chip select pad 440, and the third and fourth chip enable signal leads ( CE3 # _R and CE4 # _R are bonded to the second chip select pad 450.

The chip enable signal CE1 # or CE2 # input from the first chip select pad 440 is input to the first internal bus CE0_INT through the first buffer 410, and the second chip select pad 450 is provided. The chip enable signal CE3 # or CE4 #, which is input from, is input to the second internal bus CE1_INT through the second buffer 420.

The 4CE QD-DSP 400 according to an embodiment of the present invention is connected between the first and second chip select pads 440 and 450. Therefore, the chip enable signals CE1 # to CE # 4 input from the first and second chip select pads 440 and 450 are simultaneously input to the first and second buffers 410 and 420. However, the top chip only enables the second buffer 420, and the bottom chip enables only the first buffer 410 to control data input.

According to an embodiment of the present invention, if the top chip is deteriorated, the 4CE QD-DSP is used like the 2CE QD-DSP without the bottom chip. For this purpose, the bonding of the third and fourth chip enable signal leads CE3 # _R and CE4 # _R is broken.

And it is used as 2CE QD-DSP. When used as a 2CE QD-DSP, the first chip select pad 440 is basically used. Therefore, the selection signal is input only to the first and second chip enable signal leads CE1 # _R and CE2 # _R. At this time, only the second buffer 420 is enabled in the top chip.

However, in the embodiment of the present invention, since the first and second chip select pads 440 and 450 are connected to each other, the chip enable signal CE1 # or CE2 # input to the first chip select pads 440 and 450. Is normally input to the second buffer 420, so that the memory device may normally operate as a 2CE QD-DSP.

5 illustrates some of the leads of the 4CE QD-DSP according to an exemplary embodiment of the present invention.

Referring to FIG. 5, in order to use a 2CE QD-DSP product using only a top chip according to an exemplary embodiment of the present disclosure, a lead portion to which the third and fourth chip enable signals CE3 # and CE4 # are input is cut off. In this case, the ready busy (R / B3, R / B4) lead wire is disconnected to enable use of a 2CE QD-DSP unit. As mentioned above, since the first chip select pad 440 and the second chip select pad 450 are internally, the first and second chip enable signals CE1 # and CE2 # are normally in the second buffer 420. Can be delivered.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments of the present invention are possible within the scope of the technical idea of the present invention.

1 illustrates a pad connection configuration of a multi-chip package device.

2 shows a stack configuration of a QD-DSP.

3 illustrates a pad configuration of the QD-DSP of FIG. 2.

* Brief description of the main parts of the drawings *

400: chip pad portion

410 and 420: first and second input buffers

430: pad logic section

440 and 450: first and second chip enable signal pads

460: lead portion

Claims

A first dual chip composed of multiple layers;

A second dual chip disposed on the first dual chip and configured as a multilayer;

A plurality of signal terminals for providing command and control signals to each of the first and second dual chips and enable signals for enabling the first and second dual chips, respectively, and being connected to each other; A pad for a chip to which an enable terminal is connected; And

A plurality of pad signal terminal leads for providing comment and control signals to the plurality of signal terminals of the chip pad to the first and second dual chips, and first and second terminals of the first and second enable terminals. An enable terminal for first and second pads connected through a second enable terminal lead, respectively, and when it is determined that the quality of the first or second dual chip is deteriorated, the first or second enable terminal A packaging pad configured to block a lead;

Multi chip package device comprising a.

The method of claim 1,

In the packaging pad,

If it is determined that the quality of the first or second dual chip is inferior, the multi-chip package apparatus characterized by blocking the first or second enable terminal lead set as a default, to use as a dual chip packaging device. .