KR20100090350A - Flash memory of having spiral channel and method of manufacturing the same - Google Patents

Abstract

PURPOSE: A flash memory and a method for manufacturing the same are provided to secure the length of a channel by forming the channel into a spiral shape between a source region and a drain region. CONSTITUTION: An oxide film(110) is formed on a semiconductor substrate. An insulating film trench(160) is formed on the oxide film. A gate is formed on the insulating film trench. A channel region surrounds the gate with a spiral shape. One end of the channel region is connected with the source region of the semiconductor substrate. The other end of channel region is exposed through the upper side of the insulating film trench.

Description

Flash memory of having a spiral channel and a method of manufacturing the same {Flash Memory of having Spiral Channel and Method of Manufacturing the same}

The present invention relates to a nonvolatile memory device, and more particularly, to a telephone capture flash memory device having a spiral structure.

Due to the miniaturization and integration of integrated circuits, the basic structure of MOSFETs has been scaled down. Miniaturization and high integration of integrated circuit devices have been realized through various technology developments. However, the operation of miniaturized devices cannot exceed the inherent limitations due to quantum mechanical properties.

In particular, as the size of the MOSFET device becomes smaller and the source and the drain become closer, the gate is no longer able to control the charge transfer between the source and the drain due to the short channel effect. That is, the transistor loses the switching function.

Since the current flash memory is based on the MOSFET structure, the problem that occurs in the MOSFET structure has a problem due to the short channel effect on the miniaturization and high integration. In order to solve the problems caused by the short channel effect, various transistor structures are proposed in MOSFETs and flash memories. In particular, flash memory with a fully-depleted SOI (FD-SOI) structure fabricated using a silicon on insulator (SOI) substrate solves the problem of reducing the threshold voltage by improving the short channel effect even for channel lengths of less than 50 nm. Can be. In addition, a flash memory having a Fin-FET structure incorporating a three-dimensional structure in a device can reduce the short channel effect and secure a stable threshold voltage by controlling the width of the fin.

As such, the miniaturization and high integration of the device proceeded in such a manner that the basic structure of the MOSFET is proportionally reduced, and the miniaturization and high integration of the device by the proportional reduction have reached a physical limit. Currently, the flash memory of a silicon substrate flat panel has a limitation in controlling the threshold voltage, and suffers from a lack of a margin of sensing current. In addition, although the size of the device can be reduced as desired through various technical developments, the operation of the miniaturized device does not overcome the limitations caused by the device physical characteristics. Due to the short channel effect described above, the transistor no longer performs the switching function, and also exposes another problem in the FinFET structure. That is, in the three-dimensional FinFET structure, there is a difficulty in performing the etching process by adjusting the thickness of the fin that affects the threshold voltage, and the disadvantage of trapping impurities in the channel region by etching the substrate to form the channel region. have.

SUMMARY OF THE INVENTION In order to solve the above problems, a first object of the present invention is to provide a flash memory having a sufficient channel length even if proportional reduction is performed.

In addition, a second object of the present invention is to provide a method of manufacturing a flash memory used for achieving the first object.

The present invention for achieving the first object, a semiconductor substrate; An oxide film formed on the semiconductor substrate; An insulating film trench formed on the oxide film; A gate formed on the insulating film trench; And a channel region helically wrapping the gate while rotating the gate, wherein one end of the channel region is connected to a source region of the semiconductor substrate, and the other end of the channel region is exposed to an upper portion of the insulating film trench. Provide memory.

The present invention for achieving the second object, forming an oxide film on a semiconductor substrate; Forming a semiconductor thin film layer over the oxide layer and the source region of the semiconductor substrate; Partially etching the semiconductor thin film layer to form a fin channel extending in a first direction, and forming a connection channel on the source region; Partially etching the fin channel to form a semiconductor channel in which two side channels are connected through a lower channel; Forming an insulation trench filling the semiconductor channel and the connection channel; Forming a gate extending in a second direction crossing the first direction on the insulating film trench; And forming an upper channel connecting between side channels of neighboring semiconductor channels or connecting a side channel and the connecting channel, wherein the upper channel is connected across the gate. It provides a method of manufacturing.

According to the present invention described above, the channel region is configured while rotating helically about the gate. In addition, one end portion of the channel region is connected to the source region, and the other end portion is connected to the drain region. This increases the channel length of a single device and prevents short channel effects due to the reduced channel length due to the miniaturization of flash memory.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 to 8 are perspective views and cross-sectional views showing a flash memory according to a preferred embodiment of the present invention.

2 is a cross-sectional view when the structure disclosed in FIG. 1 is cut in the AA ′ direction.

1 and 2, the oxide film 110 is formed on the semiconductor substrate 100, and the semiconductor thin film layer 120 is formed on the oxide film 110.

First, the source region 105 on the semiconductor substrate 100 is heavily doped, and then the upper portion of the semiconductor substrate 100 is coated with the oxide film 110. The oxide film 110 may be any material as long as it is an insulating material, but silicon oxide is preferably used. In addition, a portion of the oxide layer 110 is removed through selective etching of the formed oxide layer 110, and the heavily doped source region 105 is opened. Subsequently, the semiconductor thin film layer 120 is formed on the oxide film 110 in which the source region 105 is opened. The semiconductor thin film layer 120 preferably uses an epitaxial growth method.

In addition, the structure disclosed in FIGS. 1 and 2 may be formed through the following process.

That is, the oxide film 110 is formed on the semiconductor substrate 100. Subsequently, a portion of the semiconductor substrate 100 that becomes the source region 105 is exposed through selective etching of the formed oxide film 110, and then the source region 105 is formed through an ion implantation process for the opened region. . Thereafter, the semiconductor thin film layer 120 is formed on the source region 105 and the patterned oxide film 110. Through the above-described process, it is possible to form the structure disclosed in FIGS. 1 and 2.

3, at least one fin channel 130 and a connection channel 140 are formed through selective etching to etch a part of the semiconductor thin film layer 120 illustrated in FIG. 1.

First, a photoresist is coated on the semiconductor thin film layer 120 of FIG. 1, and a first photoresist pattern 135 is formed using a conventional photolithography process. The etching is performed using the formed first photoresist pattern 135 as an etching mask. The etching process is performed until the oxide film 110 under the semiconductor thin film layer 120 is exposed. Through the above-described process, the fin channel 130 extending in the first direction and having a predetermined spacing space in the second direction crossing the first direction is formed. In addition, the connection channel 140 on the source region 105 formed on the semiconductor substrate 100 has a columnar protrusion shape.

Subsequently, referring to FIG. 4, the bottom surface of the fin channel 130 is formed by forming a second photoresist pattern 145 on the structure of FIG. 3 and using the formed second photoresist pattern 145 as an etching mask. The partial etching is performed to leave the portions to form the semiconductor channel 140. Forming the second photoresist pattern 145 removes the first photoresist pattern previously formed through an ashing process, and applies photoresist on the fin channel 130 and the connection channel 140 illustrated in FIG. 3. And by leaving the photoresist on a portion of the fin channel 130 and on top of the connecting channel 140 through conventional lithography processes.

In addition, the etching process of FIG. 4 has a form in which a lower portion of the fin channel 130 is left. Accordingly, each fin channel 130 is composed of two side channels 150A facing each other in a first direction and a lower channel 150B connecting them to each other. In addition, the two side channels 150A and the lower channel 150B constituting the semiconductor channel 150 are formed by selective etching of the fin channel 130 of FIG. Has

In addition, the semiconductor channel 150 may be disposed in plural with a predetermined space in a second direction crossing the first direction.

Referring to FIG. 5, an insulating film trench 160 is formed on the structure of FIG. 4. The insulating layer trench 160 is formed to sufficiently cover the semiconductor channel 150 and the connection channel 140 formed on the oxide layer 110.

The formation of the insulating film trench 160 may be formed by applying an insulating film to the structure of FIG. 4 and through a conventional photolithography process and etching. That is, a photoresist pattern may be formed on the entire surface of the insulating layer, and the trench structure may be formed using the formed photoresist pattern as an etching mask. In this case, the lower channel 150B is embedded in the lower portion of the trench. Through the above-described process, the insulating film trench structure extended in the second direction can be obtained.

Referring to FIG. 6, the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190 are sequentially stacked on the insulating layer trench 160 illustrated in FIG. 5.

The control gate layer 160 may be made of polycrystalline silicon or metal, conductive metal nitride, or conductive oxide. In addition, the blocking insulating layer 180 is preferably a high dielectric constant oxide. In particular, silicon oxide or metal oxide may be used, which may be selected from the group consisting of hafnium oxide, titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide and zirconium oxide, and at least one selected from these groups It may be an additive of nitrogen or silicon, or a composite film thereof. In addition, the charge trap layer 190 is preferably made of silicon nitride.

Subsequently, the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190 are removed to expose the upper surface of the insulating layer trench 160, the semiconductor channel 150, and the connecting channel 140. . As a result, the control gate layer 170, the blocking insulating layer 180, and the charge trapping layer 190 are disposed in the trench, which is an internal space of the insulating layer trench 160, and the upper surface of the insulating layer trench 160 is exposed on both sides thereof. . In addition, the upper surface of the side channel of the semiconductor channel 150 buried by the insulating film trench 160 is exposed, and the upper surface of the connection channel 140 is also exposed.

Removal of the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190 on the insulating layer trench 160 may be performed through etch back or chemical mechanical polishing. In either case, the surface of the semiconductor channel 150, the surface of the connection channel 140, and the upper surface of the insulating layer trench 160 on the side surface thereof must be exposed.

In addition, although the control gate layer 170 and the blocking insulating layer 180 remain on the inner sidewall of the trench in FIG. 6, the film quality formed on the inner sidewall of the trench may be easily removed through a predetermined etching process. Will be apparent to those skilled in the art.

Referring to FIG. 7, a tunneling insulating layer 200 is formed on the exposed charge trap layer 190.

First, a tunneling insulating film is coated on the upper surface of the structure shown in FIG. A photoresist is applied on the coated tunneling insulating layer, and a photoresist is opened, except for the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190, which are exposed on the surface through a conventional lithography process. A resist pattern is formed. When etching is performed using the formed photoresist pattern as an etching mask, an upper portion of the trench insulating layer 160, an upper portion of the side channel and a connection channel 140 are exposed, and a tunneling insulating layer 200 is formed on the charge trap layer 180. Remaining. If the control gate layer 170 and the blocking insulating layer 180 remain on the inner sidewalls of the trench as shown in FIG. 7, the tunneling insulating layer 200 is exposed to the upper surface of the control gate layer 170 and the blocking insulating layer ( 180 and the charge trapping layer 190.

The tunneling insulating layer 200 is preferably made of silicon oxide, and may be formed using a thermal oxidation process, atomic layer deposition, or chemical vapor deposition.

As a result, the tunneling insulating layer 200, the charge trap layer 190, the blocking insulating layer 180, and the control gate layer 170 constitute a gate of the flash memory.

Referring to FIG. 8, the upper channel 210 is formed on the structure of FIG. 7. The upper channel 210 is formed of monocrystalline silicon or polycrystalline silicon. In particular, when the upper channel 210 is formed of single crystal silicon, the upper channel 210 is preferably formed through an epitaxial process.

First, a semiconductor layer is formed on the structure shown in FIG. 7 by deposition or epitaxial growth. This is formed into a patterned top channel 210 using conventional lithography and etching processes. That is, after the semiconductor layer is formed, the upper channel 210 illustrated in FIG. 8 may be generated by etching the patterned photoresist as an etching mask.

The upper channel 210 is connected to the upper portion of the connection channel 140 and the side channel of the semiconductor channel 150, and is connected across the upper portion of the tunneling insulating layer 200. That is, the side channels adjacent to each other in the second direction are not connected to each other, but are connected to opposite side channels, but are connected across the tunneling insulating layer 200.

In addition, the upper channel 210 may be connected between adjacent semiconductor channels 150. That is, as shown in FIG. 8, two different semiconductor channels 150 may be connected to each other, and may cross the tunneling insulating layer 200 extending in the second direction. Accordingly, the connection channel 140, the semiconductor channel 150, and the upper channel 210 are spirally connected to each other and form a channel region. That is, the channel region has a configuration in which the spiral rotates about the gate, and has a structure spirally connected between the source region and the drain region.

In this embodiment, the source region is formed on the semiconductor substrate. Further, the drain region is formed at the end of the channel region formed in a spiral shape. 8, a drain region is formed on the exposed upper surface of the rightmost semiconductor channel via two upper channels.

FIG. 9 is a cross-sectional view of the structure shown in FIG. 8 cut in the direction BB ′. FIG.

Referring to FIG. 9, an oxide film 110 is formed on the semiconductor substrate 100, and a trench insulating film 160 is formed on the oxide film 110. In addition, the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190 are sequentially stacked in the trench, which is an internal space of the trench insulating layer 160. The tunneling insulating layer 200 is formed on the control gate layer 170, the blocking insulating layer 180, and the charge trap layer 190. The control gate layer 170, the blocking insulating layer 180, the charge trap layer 190, and the tunneling insulating layer 200 described above constitute a gate.

In addition, an upper channel 210 is formed on the tunneling insulating layer 200 and the trench insulating layer 160. The upper channel 210 has a configuration that connects the upper portion of the connection channel 140 and the upper portion of the side channel 150A to each other.

The connection channel 150A is connected to a source region formed on the semiconductor substrate 100.

FIG. 10 is a cross-sectional view of the flash memory illustrated in FIG. 8 cut in the CC ′ direction.

Referring to FIG. 10, an integrated semiconductor channel 150 is provided on the oxide film 110. In addition, the insulating layer trench 160 is formed in the space between the side channels 150A constituting the semiconductor channel 150 and facing each other, and a gate is formed in the inner space of the insulating layer trench 160. The gate includes a control gate layer 170, a blocking insulating layer 180, a charge trap layer 190, and a tunneling insulating layer 200. In addition, the side channels 150A constituting one semiconductor channel 150 are connected through the lower channel 150B.

9 and 10, the side channels 150A of the same semiconductor channel 150 are connected through the lower channel 150B, and the upper channel 210 is connected to the connecting channel for the helical configuration of the channel region. It is connected between the 140 and the side channel 150A, or between connection channels of adjacent semiconductor channels. However, the upper channel 210 is formed across the gate extending in the second direction.

Through the above-described configuration, the operation of the flash memory can be implemented. That is, the program operation and the erase operation of the conventional flash memory may be performed through the upper channel layer, the tunneling insulating film, the charge trap layer, the blocking insulating film, and the control gate. That is, the normal operation can be performed through the erase and trap operation of the upper channel. In the turn-on operation of the transistor, the channel is realized as a spiral structure between the source region and the drain region, so that the length of the channel is sufficiently large. It can be secured.

1 to 8 are perspective views and cross-sectional views showing a flash memory according to a preferred embodiment of the present invention.

FIG. 9 is a cross-sectional view of the structure shown in FIG. 8 cut in the direction BB ′. FIG.

FIG. 10 is a cross-sectional view of the flash memory illustrated in FIG. 8 cut in the CC ′ direction.

Claims (13)

Semiconductor substrates; An oxide film formed on the semiconductor substrate; An insulating film trench formed on the oxide film; A gate formed on the insulating film trench; And A channel region spirally wrapping the gate while rotating; One end of the channel region is connected to a source region of the semiconductor substrate, and the other end of the channel region is exposed on the insulating film trench. The method of claim 1, wherein the channel region, A connection channel connected to the source region; A semiconductor channel extending in a first direction and integrally formed; And An upper channel connecting between the connection channel and an upper surface of the semiconductor channel; And the upper channel is formed across the gate, and the gate extends in a second direction crossing the first direction. The method of claim 2, wherein the semiconductor channel, Two side channels facing each other in the first direction; And And a lower channel connecting the side channels. The flash memory of claim 2, wherein the semiconductor channel is buried by the insulating film trench and formed on the oxide film. 5. The flash memory of claim 4, wherein the other end portion of the channel region is a heavily doped drain region. The method of claim 2, wherein the gate, A control gate layer formed in an inner space of the insulating film trench; A blocking insulating layer formed on the control gate; A charge trap layer formed on the blocking insulating layer; And And a tunneling insulating layer formed on the charge trap layer. 7. The flash memory of claim 6, wherein the upper channel is formed across the tunneling insulating layer. Forming an oxide film on the semiconductor substrate; Forming a semiconductor thin film layer over the oxide layer and the source region of the semiconductor substrate; Partially etching the semiconductor thin film layer to form a fin channel extending in a first direction, and forming a connection channel on the source region; Partially etching the fin channel to form a semiconductor channel in which two side channels are connected through a lower channel; Forming an insulation trench filling the semiconductor channel and the connection channel; Forming a gate extending in a second direction crossing the first direction on the insulating film trench; And Connecting between side channels of a neighboring semiconductor channel or forming an upper channel connecting the side channel and the connection channel, And the upper channel is connected across the gate. The method of claim 8, wherein forming an oxide film on the semiconductor substrate comprises: Forming the source region on the semiconductor substrate; Applying the oxide film on the semiconductor substrate; And Selectively etching the oxide film to expose an upper portion of the source region. The method of claim 8, wherein forming an oxide film on the semiconductor substrate comprises: Applying the oxide film on the semiconductor substrate; Partially etching the oxide film to expose a portion of the semiconductor substrate; And And ion implanting the exposed semiconductor substrate to form the source region. The method of claim 8, wherein the forming of the insulating film trench comprises: Forming an insulating layer covering the semiconductor channel and the connection channel; And And partially etching the insulating film to form the insulating film trench having the trench extended in the second direction. The method of claim 8, wherein the forming of the gate comprises: Forming a control gate layer on the insulating film trench; Forming a blocking insulating layer on the control gate layer; Forming a charge trap layer on the blocking insulating film; The control gate layer, the blocking insulating film, and the charge trap layer formed on the upper surface of the insulating film trench to expose the upper surface of the insulating film trench, the upper surface of the semiconductor channel, the charge trap layer, and the connection channel. Removing; And And forming a tunneling insulating layer on the exposed charge trap layer. The method of claim 12, wherein the upper channel is formed across the tunneling insulating layer.

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