KR20100083310A - Power supply circuit for semiconductor memory apparatus - Google Patents

Power supply circuit for semiconductor memory apparatus Download PDF

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Publication number
KR20100083310A
KR20100083310A KR1020090002632A KR20090002632A KR20100083310A KR 20100083310 A KR20100083310 A KR 20100083310A KR 1020090002632 A KR1020090002632 A KR 1020090002632A KR 20090002632 A KR20090002632 A KR 20090002632A KR 20100083310 A KR20100083310 A KR 20100083310A
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KR
South Korea
Prior art keywords
power supply
switching unit
semiconductor memory
memory device
internal circuit
Prior art date
Application number
KR1020090002632A
Other languages
Korean (ko)
Inventor
김대석
조진희
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020090002632A priority Critical patent/KR20100083310A/en
Publication of KR20100083310A publication Critical patent/KR20100083310A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A power supply circuit for a semiconductor memory apparatus is provided to supply an external power by a surplus power supply pad in a mode having a relative low bandwidth. CONSTITUTION: A first switching unit(120) is connected between a power source supply pad(110) and a first internal circuit(140). The first switching unit supplies an external power to the first internal circuit. A second switching unit(130) is connected between the power source supply pad and a second internal circuit(150). A second switching unit supplies an external power to the second internal circuit. The first switching unit and the second switching unit are selectively driven according bandwidth thereof. The power source supply pad is comprised of a data input/output power supply pad. The first switching unit is driven by a first control signal to operate the semiconductor memory device with a first bandwidth.

Description

Power Supply Circuit for Semiconductor Memory Device

The present invention relates to a semiconductor memory device, and more particularly, to a power supply circuit of a semiconductor memory device.

Recently, multi-bit I / O paths have been designed to increase data transfer rates. According to the multi-bit structure, the data bandwidth that can be continuously inputted and output by one data input / output signal may be 2 bits, 4 bits, 8 bits, 16 bits, 32 bits, or the like. 4, 8, 16, and the like refer to memory devices having 4, 8, and 16 bit structures, respectively.

The semiconductor memory device is designed to satisfy all 4, 8, and 16 bit modes, that is, to share the I / O configuration. It is configured to operate in any of the 16 bits.

Meanwhile, the semiconductor memory device includes a data input / output pad, an address pad, a control signal input pad, and a power supply pad.

The power applied from the outside through the power supply pad is used internally only as the same power supply.

However, when the power supply voltage VDD and the ground voltage VSS, which are the main power supplies of the semiconductor memory device, are not supplied at sufficient levels, the operation performance of the semiconductor memory device may be degraded, thereby causing an error.

For example, 8-bit mode and 16-bit mode semiconductor memory devices sharing an input / output environment use only a portion of the power supply pad when operating in low bandwidth, that is, 8-bit mode. In this case, if the main power is not properly supplied, the semiconductor memory device may malfunction.

Accordingly, an object of the present invention is to provide a power supply circuit of a semiconductor memory device capable of stabilizing a power supply level in a semiconductor memory device sharing an input / output environment.

The power supply circuit of the semiconductor memory device of the present invention for achieving the above object of the present invention is a power supply circuit of the semiconductor memory device having a variable data input and output bandwidth, is connected between the power supply pad and the first internal circuit is the first And a second switching unit configured to provide an external supply power to an internal circuit and a second switching unit connected between the power supply pad and a second internal circuit to provide the external supply power to the second internal circuit.

According to the present invention, when operating in a mode with a relatively low bandwidth in a semiconductor memory device sharing the input and output environment, the external power is supplied through an extra power supply pad. As a result, a stable power supply level can be maintained.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is an exemplary diagram of a power supply circuit of a semiconductor memory device according to an embodiment of the present invention.

As shown in FIG. 1, the power supply circuit 100 of the present invention includes a first switching unit 120 and a second switching unit 130. The external power VEXT is applied to the node A through the power supply pad 110, and the first switching unit 120 and the second switching unit 130 are connected between the node A and the internal circuits 140 and 150, respectively. Connected.

The first switching unit 120 is turned on by receiving the first control signal and supplies the external power VEXT applied to the common node A to the internal circuit 1 140.

The second switching unit 130 receives the second control signal and is turned on, and supplies the external power VEXT applied from the common node A to the internal circuit 2 150.

Herein, the power supply pad 110 may be a data input / output power supply pad VDDQ or VSSQ, and the first control signal and the second control signal may be bandwidth selection signals. In addition, the external power supply VEXT may be a power supply voltage VDD level or a ground voltage VSS level.

That is, in the semiconductor memory device operating in the 8-bit mode or the 16-bit mode by the bandwidth selection signal, the first control signal becomes a bandwidth selection signal for the 8-bit mode, the second control signal is a bandwidth selection signal for the 16-bit mode Can be

When operating in a low bandwidth, that is, an 8-bit mode, the external power supply VEXT supplied through the first switching unit 120 is supplied to the internal circuit 140 using the power supply voltage VDD or the ground voltage VSS. .

On the other hand, when operating in a high bandwidth, that is, 16-bit mode, the external power supply VEXT supplied through the second switching unit 130 may supply a data input / output power voltage VDDQ or a ground voltage VSSQ, such as a data input / output driver. It is supplied to the internal circuit 150 to be used.

FIG. 2 is an exemplary diagram of the first switching unit illustrated in FIG. 1, and FIG. 3 is an exemplary diagram of the second switching unit illustrated in FIG. 1.

As shown in FIG. 2, the first switching unit 120 is driven by the first control signal applied to the gate terminal, and the source terminal is connected to the common node A to connect the external power supply VEXT to the internal circuit 1. The first transistor P1 supplied to 140 can be configured.

As shown in FIG. 3, the second switching unit 130 is driven by the second control signal applied to the gate terminal, and the source terminal is connected to the common node A so that the external power source VEXT is connected to the internal circuit 2. 2nd transistor P2 supplied to 150 can be comprised.

Here, the first and second transistors P1 and P2 may be PMOS transistors.

Therefore, the present invention can supply external power through an extra power supply pad when operating in a mode with low bandwidth in a semiconductor memory device sharing an input / output environment. As a result, power supply characteristics of the semiconductor memory may be improved, thereby lowering the probability of failure due to an operation.

In the above, the present invention has been described with reference to preferred embodiments thereof, but the present invention is not limited thereto, and a person of ordinary skill in the art to which the present invention pertains should have the present invention without departing from the essential characteristics of the present invention. It will be appreciated that it may be configured in a modified form.

1 is an exemplary diagram of a power supply circuit of a semiconductor memory device according to an embodiment of the present invention;

2 is an exemplary view of the first switching unit shown in FIG. 1, and

3 is a diagram illustrating an example of the second switching unit illustrated in FIG. 1.

<Detailed Description of Main Reference Signs>

120: first switching unit 130: second switching unit

Claims (4)

A power supply circuit of a semiconductor memory device having a variable data input / output bandwidth, A first switching unit connected between a power supply pad and a first internal circuit to provide an external supply power to the first internal circuit; And And a second switching unit connected between the power supply pad and a second internal circuit to provide the external supply power to the second internal circuit, wherein the first switching unit and the second switching unit are selectively selected according to the bandwidth. A power supply circuit of a semiconductor memory device, characterized in that driven. The method of claim 1, The power supply pad is a power supply circuit of the semiconductor memory device, characterized in that the power supply pad for data input and output. The method of claim 1, And the first switching unit is driven by a first control signal for operating the semiconductor memory device at a first bandwidth. The method of claim 1, And the second switching unit is driven by a second control signal for operating the semiconductor memory device at a second bandwidth.
KR1020090002632A 2009-01-13 2009-01-13 Power supply circuit for semiconductor memory apparatus KR20100083310A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020090002632A KR20100083310A (en) 2009-01-13 2009-01-13 Power supply circuit for semiconductor memory apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090002632A KR20100083310A (en) 2009-01-13 2009-01-13 Power supply circuit for semiconductor memory apparatus

Publications (1)

Publication Number Publication Date
KR20100083310A true KR20100083310A (en) 2010-07-22

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020090002632A KR20100083310A (en) 2009-01-13 2009-01-13 Power supply circuit for semiconductor memory apparatus

Country Status (1)

Country Link
KR (1) KR20100083310A (en)

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