KR20100081863A - Substrate for semiconductor package - Google Patents

Substrate for semiconductor package Download PDF

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Publication number
KR20100081863A
KR20100081863A KR1020090001284A KR20090001284A KR20100081863A KR 20100081863 A KR20100081863 A KR 20100081863A KR 1020090001284 A KR1020090001284 A KR 1020090001284A KR 20090001284 A KR20090001284 A KR 20090001284A KR 20100081863 A KR20100081863 A KR 20100081863A
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South Korea
Prior art keywords
substrate
layer
core
pattern layer
thermal expansion
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KR1020090001284A
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Korean (ko)
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원동관
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삼성테크윈 주식회사
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Priority to KR1020090001284A priority Critical patent/KR20100081863A/en
Publication of KR20100081863A publication Critical patent/KR20100081863A/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)

Abstract

PURPOSE: A semiconductor package substrate is provided to minimize flexural deformation due to thermal expansion coefficient between a core, a pattern layer, and a solder resistor layer by controlling the flexural deformation of a substrate. CONSTITUTION: A substrate is divided into an upper side part and a lower side part which have same thickness. A first pattern layer(103), a first photo solder resistor layer(106) are formed in the upper part. A second pattern layer(105), a second photo solder resistor layer(107) are formed in the lower part(101). The first pattern layer and the second pattern layer are closely related to the electrical performance of a semiconductor package. A substrate is twisted and deformed as the length of the upper part and the lower part is changed during a thermal processing process.

Description

Substrate for semiconductor package

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate, and more particularly, to a substrate for a semiconductor package having an improved structure in order to minimize bending deformation of the substrate due to a difference in thermal expansion coefficient between the photo solder resistor layer, the pattern layer, and the core. will be.

In general, a board on chip package (BOC) of a semiconductor package is a structure in which a semiconductor chip is mounted on a circuit board having an area approximately equal to that of a semiconductor chip.

The conventional board-on-chip package uses a circuit board having a core of FR-4 (falme retardent-4). When using FR-4 as a core circuit board, warpage deformation is not a problem during the process of forming a photo solder resistor layer coated on the pattern layer.

However, when the core is changed from FR-4 series to epoxy series such as BT resin (bismaleimid triazine resin), warpage will increase during the coating process of the photo solder resistor layer, which will affect other semiconductor package processes. Is going crazy.

That is, a typical process of manufacturing a board-on-chip package includes a process of forming a circuit pattern layer using a metal thin film such as copper on a core and a photo solder resistor layer on the circuit pattern layer. As the photo solder resistor layer hardens at high temperature and passes through a temperature cycle that is cooled to room temperature again, bending deformation occurs due to the difference in coefficient of thermal expansion (CTE) between the core, the pattern layer, and the photo solder resistor layer. do.

When the bending deformation is generated in this way, it is difficult to secure the coplanarity of the solder ball attached to the solder ball land part, and a precise coupling between the semiconductor package and the external circuit board is not achieved, but rather poor contact occurs. Many difficulties are encountered in the handling of flexurally deformed substrates.

The present invention is to solve the above problems, in order to minimize the bending deformation due to the thermal expansion coefficient between the core, the pattern layer, and the solder resistor layer by adjusting the thickness of the solder resistor layer to a specific range to adjust the bending deformation of the substrate. It is a main problem to provide the controlled semiconductor package substrate.

Another object of the present invention relates to a semiconductor package substrate in which the bending deformation of the substrate is controlled according to the shape and formation of the dummy pattern layer at the edge of the substrate.

In order to achieve the above object, the semiconductor package substrate according to an aspect of the present invention,

A substrate comprising a core, a plurality of pattern layers formed on upper and lower surfaces thereof, and a unit substrate on which a plurality of photoresist layers filling the plurality of pattern layers are formed are continuously disposed.

Divide the upper portion and the lower portion of the core so as to have the same thickness with respect to the entire thickness of the substrate,

The ratio of the equivalent thermal expansion coefficient (α upper ) of the upper portion and the equivalent thermal expansion coefficient (α lower ) of the lower portion is the ratio of the equivalent thermal expansion coefficient (

Figure 112009000918988-PAT00002
) Satisfies Equation 1 below.

&Quot; (1) "

0.8≤ α ratio ≤ 1.2

In addition, the plurality of pattern layers include first and second pattern layers respectively formed on the first surface of the core and the second surface opposite thereto,

The plurality of photo solder resistor layers includes first and second photo solder resistor layers respectively filling the first and second pattern layers.

Furthermore, the upper portion includes an upper core, a first pattern layer, and a first photo solder resistor layer,

The lower portion is divided into a lower portion having a lower core, a second pattern layer, and a second photo solder resistor layer,

The relative ratio between the equivalent thermal expansion coefficient of the upper portion and the equivalent thermal expansion coefficient of the lower portion is formed by adjusting the thicknesses of the first photo solder resistor layer and the second photo solder resistor layer.

In addition, the equivalent thermal expansion coefficient α upper of the upper portion satisfies Equation 2 below, and the equivalent thermal expansion coefficient α lower of the lower portion satisfies Equation 3 below.

<Equation 2>

Figure 112009000918988-PAT00003

Herein, the coefficient of thermal expansion, the modulus of elasticity, and the volume ratio of each of the upper core, the first pattern layer, the first photo solder resistor layer, and (α cor1 , α pa1 , α ps1 ), (E co1 , E pa1 , E ps1 ) and (V co1 , V pa1 , V ps1 ).

<Equation 3>

Figure 112009000918988-PAT00004

Here, the lower core and the second pattern layer, and a second with each of the thermal expansion coefficient of photo solder resist layer, the modulus of elasticity, and the volume ratio (α co2, α pa2, α ps2) and (E co2, E pa2, E ps2 ) and (V co2 , V pa2 , V ps2 ).

As described above, in the semiconductor package substrate of the present invention, the bending deformation of the substrate can be minimized by adjusting the thickness of the photo solder resistor layer on the upper and lower portions of the substrate. In addition, the bending deformation of the substrate can be reduced by adjusting the presence or absence of the formation of the dummy pattern and the shape.

Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings.

1 illustrates a semiconductor package substrate 100 according to an embodiment of the present invention.

Referring to the drawings, the substrate 100 is provided with a core 101 made of a polymer resin such as BT resin. The first pattern layer 103 is patterned on the surface of the first surface 102 of the core 101, and the second pattern layer is formed on the surface of the second surface 104 opposite to the first surface 102. 105 is patterned. The first pattern layer 103 and the second pattern layer 105 may be formed of a metal thin film having excellent conductivity such as copper.

A first photo solder resistor layer 106 is optionally embedded in the first pattern layer 103 except for a bonding pad portion and a region such as a solder ball land portion, and in the second pattern layer 105. The second photo solder resistor layer 107 is formed.

FIG. 2 illustrates the substrate 100 of FIG. 1 in which each unit substrate 200 is continuously disposed.

Referring to the drawings, the plurality of unit substrates 200 are arranged in a matrix arrangement on the substrate 100, and a plurality of semiconductor packages are simultaneously manufactured. The substrate 100 is subjected to a sawing process in order to be separated into individual semiconductor packages after the semiconductor chip is mounted on the unit substrate 200.

Each of the unit substrates 200 of the substrate 100 has a first pattern layer 103 formed on one surface (ie, 102 of FIG. 1) of the core 101 as described above, for transmitting an electrical signal. The first pattern layer 103 is circuit patterned with a metal foil having excellent conductivity such as copper. The first pattern layer 103 is formed by laminating a copper thin film on the first surface 102 of the core 101 and patterning the copper thin film to a predetermined shape, and a photolithography process is applied as a patterning process. can do.

The dummy pattern layer 201 may be selectively formed outside the group of the unit substrates 200, which are peripheral portions of the substrate 100. The second pattern layer (105 in FIG. 1) may be formed on the other surface (104 in FIG. 1) of the core 101 over the entire area of the substrate 100. Since the second surface 104 of the core 101 is not required to serve as a circuit pattern, the second pattern layer 105 serves as a dummy pattern layer.

As such, the dummy pattern layer 201 may be selectively formed at the periphery of the substrate 100 or formed on the second surface 105 of the core 101 to increase the overall strength of the substrate 100 and to warp thereof. To reduce deformation.

That is, the first pattern layer 103 having the circuit pattern layer may not have the periphery of the substrate 100 or the circuit pattern layer with respect to the first surface 102 of the core 101 formed for each unit substrate 200. The purpose of the present invention is to reduce bending deformation of the substrate 100 caused by different degrees of thermal deformation at the second surface 104 of the core 101 on which the second pattern layer 105 is formed.

Meanwhile, a first photo solder resistor layer 106 is coated on the first pattern layer 103 to cover an area except for a bonding pad part or a solder ball land part. The two photo solder resistor layer 107 is applied. The first photo solder resistor layer 106 may simultaneously cover the dummy pattern layer 201.

Here, the first pattern layer 103 formed on the surface of the first surface 102 of the core 101 and the second pattern layer formed on the surface of the second surface 104 opposite to the first surface 102. The pattern shapes of 105 are different from each other.

Accordingly, the copper content constituting the first pattern layer 103 and the second pattern layer 105 are different from each other. This difference in copper content causes bending deformation of the substrate 100 during a heat treatment process, such as a hardening process of the first photo solder resistor layer 106 and the second photo solder resistor layer 107.

In order to prevent the above phenomenon, after dividing the substrate 200 into two layers having the same thickness, the first and second pattern layers 103 and 105 and the dummy pattern layer 201 corresponding to the portions where copper is present are provided. By calculating the effective coefficient of thermal expansion considering the copper content in the c), it is possible to obtain a condition that prevents warpage by controlling the thickness of the photo solder resistor layer having a small warpage deformation by comparing the values between the two layers.

3 illustrates a state in which the substrate 100 of FIG. 1 is bent and deformed.

1 and 3, the total thickness T tot of the substrate 100 is divided into an upper portion 110 and a lower portion 120, each having the same thickness T tot / 2 . In the upper portion 110, a first pattern layer 103 is formed on the core 101, and a first photo solder resistor layer 106 selectively filling the lower portion 120, and the core 101 is formed in the lower portion 120. The second pattern layer 105 and the second photo solder resistor layer 107 filling the second pattern layer 105 are formed.

In the upper portion 110 and the lower portion 120 having different thermal expansion rates, the length of the upper portion 110 and the length of the lower portion 120 are different from each other during the heat treatment process, such that the substrate 100 is warped and deformed. Will bring. At this time, the bending strain (d / L) means a length reduction (d) for the bending deformation with respect to the length (L) of the substrate 100, the substrate 100 is bent downward. In order to minimize such bending deformation, the coefficient of thermal expansion between the upper portion 110 and the lower portion 120 each made of different materials should be the same.

The area of the first pattern layer 103, the second pattern layer 105, the first photo solder resistor layer 106, or the second photo solder resistor layer 107 is controlled by the semiconductor package. Since design changes are required, it is easier to adjust the thickness of each component. In addition, since the first pattern layer 103 and the second pattern layer 105 are closely related to the electrical performance of the semiconductor package, it is not easy to adjust the thickness thereof.

Therefore, controlling the thickness (T PSR-lower) of the thickness of the first photo solder resist layer 106 that do not directly alter the performance of the semiconductor package (T PSR-upper), a second photo solder resist layer 107 By doing so, it is preferable that the equivalent thermal expansion coefficient (CTE) ratio α ratio is within a specific range.

This will be described in more detail as follows.

The thermal expansion coefficients α cor1 , α pa1 , α ps1 of the upper core 108, the first pattern layer 103, the first photo solder resistor layer 106 formed on the upper portion 110, and the elastic modulus ( E co1 , E pa1 , E ps1 ) and the equivalent thermal expansion coefficient α upeer of the upper portion 110 from the volume ratios V co1 , V pa1 , V ps1 may be defined by Equation 1 below.

&Quot; (1) &quot;

Figure 112009000918988-PAT00005

The volume ratios V co1 , V pa1 , V ps1 are the upper cores 108 formed in the upper portion 110, the first pattern layer 103, when the volume of the entire upper portion 110 is 1; The relative fraction of the volume occupied by the first photo solder resistor layer 106 is referred to. For example, the volume ratio V ps1 of the first photo solder resistor layer 106 may be defined by Equation 2 below.

<Equation 2>

Figure 112009000918988-PAT00006

Thermal expansion coefficients α co2 , α pa2 , α ps2 of the lower core 109, the second pattern layer 105, the second photo solder resist layer 107, and the elastic modulus ( E co2 , E pa2 , E ps2 ) and the equivalent thermal expansion coefficient α lower of the lower portion 120 from the volume ratios V co2 , V pa2 , V ps2 may be defined by Equation 3 below.

<Equation 3>

Figure 112009000918988-PAT00007

The volume ratios V co2 , V pa2 , V ps2 are the lower core 109 formed in the lower portion 120, the second pattern layer 105, when the volume of the entire lower portion 120 is 1; The relative fraction of the volume occupied by the second photo solder resistor layer 107 is referred to. For example, the volume ratio V ps2 of the second photo solder register layer 107 may be defined by Equation 4 below.

<Equation 4>

Figure 112009000918988-PAT00008

In this case, the thermal expansion coefficients α co1 , α pa1 , α ps1 of the upper core 108, the first pattern layer 103, the first photo solder resistor layer 106 formed on the upper portion 110, Modulus of elasticity (E co1 , E pa1 , E ps1 ), the lower core 109 formed on the lower portion 120, the second pattern layer 105, and the coefficient of thermal expansion of the second photo solder resistor layer 107 ( α co2 , α pa2 , α ps2 ) and the elastic modulus (E co2 , E pa2 , E ps2 ) correspond to intrinsic constants.

Accordingly, the bending deformation of the substrate 100 is to, as Equation (5), defined as the relative ratio of the equivalent thermal expansion coefficient (α upper) and, the equivalent thermal expansion coefficient (α lower) of the lower part 120 of the upper portion 110, It is predictable by the ratio (α ratio ) of equivalent thermal expansion coefficients.

<Equation 5>

Figure 112009000918988-PAT00009

Assuming that the thickness of one photo solder resistor layer is fixed when the copper content (ie, area ratio) in the first pattern layer 103 and the second pattern layer 105 changes, by adjusting the thickness of the layer, and can not seem to find the ratio (α ratio) is 1, the point of the equivalent coefficient of thermal expansion, even if it changes as the thickness of each side of the photo solder resist layer ratio of the equivalent thermal expansion coefficient (α ratio) is 1 Of course it is possible to obtain a point. In addition, the bending strain d / L increases or decreases in proportion to each other as the ratio (α ratio ) of the equivalent thermal expansion coefficient increases.

Thus, the ratio of the equivalent thermal expansion coefficient (α ratio) is as in equation (5), the relative ratio of the equivalent thermal expansion coefficient (α lower) of the lower part 120 of the equivalent thermal expansion coefficient (α upper) of the upper part 110 Each of the equivalent coefficients of thermal expansion α upper and α lower is obtained from Equations 1 and 3, respectively.

At this time, the coefficient of thermal expansion (α co1 , α pa1 , α ps1 , α co2 , α pa2 , α ps2 ) for each component, and the modulus of elasticity (E co1 , E pa1 , E ps1 , E co2 , E pa2 , E ps2 ) Since is a material-specific value, by adjusting the volume ratio (V co1 , V pa1 , V ps1 , V co2 , V pa2 , V ps2 ) of each component, the desired equivalent coefficient of thermal expansion (α ratio ) can be obtained. have.

Accordingly, the ratio (α ratio ) of the equivalent thermal expansion coefficients obtained by the above Equations 1 to 5 is preferably set within a range of 0.8 ≦ α ratio ≦ 1.2. The thicknesses of the first photo solder resistor layer 106 and the second photo solder resistor layer 107 are set so as to be set within the above ranges.

In the case where the entire substrate 100 is considered, or only a necessary area is taken into consideration, or when another sub material is added to the substrate 100 in addition to the core 101, copper, or a photo solder resistor layer. It is a matter of course to be set within the above range. In addition, the thickness of the photo solder resistor layer should be adjusted according to the material of the core and copper or the thickness and copper content in the substrate.

Table 1 summarizes the amount of deflection by performing a finite element method (FEM) and a product test on the substrate 100 having different thicknesses of the first photo solder resistor layer 106 according to the applicant's experiment. This is the result shown.

TABLE 1

Upper part
PSR layer thickness Lower part
PSR layer thickness Cu content
(Top / bottom) Equivalent CTE Ratio
(Top / bottom) Flexural Contrast Bridge by FEM Comparison of bending phase by product test result Example 1 40 μm 30 μm 45% / 36% 1.0885 One One Example 2 25 μm 30 μm 45% / 36% 1.0045 0.24 0.34

Referring to Table 1, when the amount of bending deformation obtained in Example 1 is 1, Example 2 shows a relative degree of bending deformation. In Example 2, the results obtained from the finite element analysis and the test results of the actual product are shown. As a result, the amount of warpage deformation is lower than that of Example 1, for example, 76% from the finite element analysis result and 64% from the actual product test result. In this manner, by adjusting the thickness of the photo solder resistor layer 106, it is possible to minimize the warpage deformation of the substrate.

4A to 4D illustrate a modified embodiment according to whether a dummy pattern layer 201 is formed and a shape change, and FIG. 5 illustrates a bending deformation of the substrate 100 according to the embodiment of FIGS. 4A to 4D. The results are shown.

4A is a blank type in which a dummy pattern layer is not formed on the left and right side portions 401 of the substrate 100, and a dummy pattern layer made of copper in the rail portions 402 corresponding to upper and lower portions of the substrate 100. Is formed (hereinafter, A). 4B illustrates a case in which a dummy pattern layer made of copper is formed on the left and right side portions 403 of the substrate 100 and a dummy pattern layer made of copper is formed in the rail portions 404 corresponding to the upper and lower portions of the substrate 100 (hereinafter, referred to as FIG. , B). FIG. 4C illustrates a case in which a dummy pattern layer having an independent type is formed on the left and right side portions 405 of the substrate 100, and a dummy pattern made of copper in the rail portions 406 corresponding to upper and lower portions of the substrate 100. (D) (hereinafter, C) In FIG. 4D, the dummy pattern layer is not formed on the left and right side portions 407 of the substrate 100, and the dummy pattern is formed on the rail portions 408 corresponding to the upper and lower portions of the substrate 100. This is the case when no layer is formed (hereinafter, D).

As shown in FIG. 5, the bending deformation after the first firing after removing the moisture of the substrate and the second after the second firing performed before packaging, as shown in FIG. The flexural deformation and the amount of flexural deformation after 24 hours of aging are measured.

Looking at the amount of deflection after the first firing, the deflection of 0.67 mm for B, the deflection of 0.75 mm for B, the deflection of 0.63 mm for C, and the 0.30 mm for D Flexural deformation was shown.

In the flexural deformation after the second firing, the flexural deformation of A is 1.05 millimeters, the B is 0.88 millimeters, the C is 0.81 millimeters, and the D is 0.61 millimeters. Flexural deformation was shown.

Looking at the amount of deflection after 24 hours of aging, for A, 1.76 millimeters, for B, 2.22 millimeters, for C, 1.90 millimeters, and for D, 0.51 millimeters The bending deformation of was shown.

That is, when the dummy pattern layer is not formed on the left and right side portions 407 of the substrate 100, and the dummy pattern layer is not formed on the rail portions 408 corresponding to the upper and lower portions of the substrate 100, the first case is different from the first case. It can be seen that the least deformation occurs after firing, after the second firing, or after aging for 24 hours.

Looking at the photograph of the bending deformation, in Figures 6a to 6c corresponding to the case of A, B, C, the edge 601 where the left and right side portions of the substrate 100 and the rail portion meet by the bending deformation on the jig 602 While the gaps E, F, and G occur, the edge 601 where the left and right side portions of the substrate 100 and the rail portion meet in FIG. 6D, corresponding to the case of D, minimizes the bending deformation on the jig 602. It can be seen that H) hardly occurs.

As such, it can be seen that the bending deformation is minimized when the dummy pattern layer is not formed in both the left and right side portions of the substrate and the rail portions corresponding to the upper and lower portions of the substrate. Therefore, in order to minimize the bending deformation occurring after the substrate is manufactured, it is preferable not to form the dummy pattern layer on the left and right side portions of the substrate and the rail portions corresponding to the upper and lower portions of the substrate.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a cross-sectional view showing a substrate according to a first embodiment of the present invention;

2 is a plan view showing the substrate of FIG.

3 is a cross-sectional view showing a state in which the substrate of FIG. 1 is bent;

4A is a plan view showing the shape of a dummy pattern layer according to the first embodiment of the present invention;

4B is a plan view showing the shape of the dummy pattern layer according to the second embodiment of the present invention;

4C is a plan view showing the shape of the dummy pattern layer according to the third embodiment of the present invention;

4D is a plan view showing the shape of the dummy pattern layer according to the fourth embodiment of the present invention;

5 is a graph showing the bending state of the substrate of the present invention,

Figure 6a is a photograph showing the bending state of the case A of Figure 5,

FIG. 6B is a photograph showing a state of warpage in case B of FIG. 5;

Figure 6c is a photograph showing the bending state of the case C of Figure 5,

Figure 6d is a photograph showing the bending state of the case D of FIG.

<Brief description of the major symbols in the drawings>

100 ... substrate 101 ... core

103 ... first pattern layer 105 ... second pattern layer

106.First Photo Solder Resistor Layer

107 ... second photo solder resistor layer

108 ... upper core 109 ... lower core

110 ... upper part 120 ... lower part

200 ... unit board

Claims (8)

A substrate comprising a core, a plurality of pattern layers formed on upper and lower surfaces thereof, and a unit substrate on which a plurality of photoresist layers filling the plurality of pattern layers are formed are continuously disposed. Divide the upper portion and the lower portion of the core so as to have the same thickness with respect to the entire thickness of the substrate, The ratio of the equivalent thermal expansion coefficient (α upper ) of the upper portion and the equivalent thermal expansion coefficient (α lower ) of the lower portion is the ratio of the equivalent thermal expansion coefficient (
Figure 112009000918988-PAT00010
) Is a semiconductor package substrate that satisfies the following equation (1). &Quot; (1) &quot; 0.8≤ α ratio ≤ 1.2 The method of claim 1, The plurality of pattern layers includes first and second pattern layers respectively formed on a first side of the core and a second side opposite thereto, The plurality of photo solder resistor layers may include first and second photo solder resistor layers respectively filling the first and second pattern layers. The method of claim 2, The upper portion includes an upper core, a first pattern layer, and a first photo solder resistor layer; The lower portion is divided into a lower portion having a lower core, a second pattern layer, and a second photo solder resistor layer, A relative ratio between the equivalent thermal expansion coefficient of the upper portion and the equivalent thermal expansion coefficient of the lower portion is formed by adjusting the thicknesses of the first photo solder resistor layer and the second photo solder resistor layer. The method of claim 3, wherein An equivalent thermal expansion coefficient (α upper ) of an upper portion satisfies Equation 2 below, and an equivalent thermal expansion coefficient (α lower ) of a lower portion satisfies Equation 3 below. <Equation 2>
Figure 112009000918988-PAT00011
 Here, the coefficient of thermal expansion, the modulus of elasticity, and the volume ratio of each of the upper core, the first pattern layer, the first photo solder resistor layer, and (a cor1 , α pa1 , α ps1 ), (E co1 , E pa1 , E ps1 ) and (V co1 , V pa1 , V ps1 ). <Equation 3>
Figure 112009000918988-PAT00012
 Here, the lower core and the second pattern layer, and a second with each of the thermal expansion coefficient of photo solder resist layer, the modulus of elasticity, and the volume ratio (α co2, α pa2, α ps2) and (E co2, E pa2, E ps2 ) and (V co2 , V pa2 , V ps2 ). The method of claim 2, The first pattern layer formed on the first surface of the core forms a circuit pattern, The second pattern layer formed on the second surface of the core forms a dummy pattern, The semiconductor package substrate, characterized in that a dummy pattern layer is formed along the periphery of the substrate. The method of claim 5, In the part where the dummy pattern layer is formed, the left and right side portions of the substrate, which are outside the plurality of unit substrate groups, are divided into rail portions corresponding to upper and lower portions, The semiconductor package substrate, characterized in that the left and right side portions of the substrate, and the rail portion are both dummy pattern layers. The method of claim 1, The core is a semiconductor package substrate comprising a polymer resin of BT resin. The method of claim 1, The plurality of pattern layers is a semiconductor package substrate, characterized in that the thin film made of copper.
KR1020090001284A 2009-01-07 2009-01-07 Substrate for semiconductor package KR20100081863A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130120952A1 (en) * 2011-11-10 2013-05-16 Samsung Electronics Co., Ltd. Substrate and electronic device including the substrate
US9508699B2 (en) 2014-04-17 2016-11-29 SK Hynix Inc. Semiconductor package and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130120952A1 (en) * 2011-11-10 2013-05-16 Samsung Electronics Co., Ltd. Substrate and electronic device including the substrate
US8988892B2 (en) 2011-11-10 2015-03-24 Samsung Electronics Co., Ltd. Substrate and electronic device including the substrate
US9508699B2 (en) 2014-04-17 2016-11-29 SK Hynix Inc. Semiconductor package and method for manufacturing the same

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