KR20100079333A - Method for fabricating of bipolar junction transistor - Google Patents

Method for fabricating of bipolar junction transistor Download PDF

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Publication number
KR20100079333A
KR20100079333A KR1020080137773A KR20080137773A KR20100079333A KR 20100079333 A KR20100079333 A KR 20100079333A KR 1020080137773 A KR1020080137773 A KR 1020080137773A KR 20080137773 A KR20080137773 A KR 20080137773A KR 20100079333 A KR20100079333 A KR 20100079333A
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South Korea
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conductivity type
emitter
well
base
forming
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KR1020080137773A
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Korean (ko)
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송종규
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주식회사 동부하이텍
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Publication of KR20100079333A publication Critical patent/KR20100079333A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0821—Collector regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The present invention relates to a method of manufacturing a bipolar transistor that can improve the efficiency of the emitter,

The method of manufacturing a bipolar transistor according to the present invention includes the steps of forming a first conductivity type deep well and a second conductivity type deep well by injecting a first conductivity type impurity and a second conductivity type impurity into a first conductivity type semiconductor substrate; Forming a second conductivity type well in the first conductivity type deep well, forming an emitter in the second conductivity type well, and forming a second conductivity type well in the first conductivity type deep well and the second conductivity type deep well. Forming a device isolation film to define a base region and a collector region, and implanting impurities into the base region and the collector region to form a base and a collector, respectively.

Description

Method for fabricating of Bipolar Junction Transistor

The present invention relates to a method for manufacturing a bipolar transistor, and more particularly, to a method for manufacturing a bipolar transistor that can improve the efficiency of the emitter.

Bipolar junction transistors (BJTs) offer superior performance in terms of current performance, speed, and grain compared to metal oxide semiconductor transistors (MOS TRs). It is widely used in RF IC design.

Bipolar transistors composed of an emitter, a base, and a collector may be classified into a vertical bipolar transistor and a horizontal bipolar transistor according to a moving direction of charges emitted from the emitter.

Such bipolar transistors can be used to fabricate electrostatic devices to protect internal IC circuits.

Such an electrostatic element should be composed of I / O (input or output) when designing a circuit, and an electrostatic element should be configured according to the internal circuit operating voltage. In order to use a bipolar transistor as an electrostatic element, a collector ( The collector is connected, the emitter is connected to ground, and the base is connected to the ground terminal through a resistor. In addition, since the role of the electrostatic element is to be instantaneously pulled out to the ground terminal when the instantaneous voltage exceeds 2000V, the triggering voltage (Vt1), the holding voltage (Vh), the breakdown in order to use the bipolar as an electrostatic element. The same parameter as the voltage lt2 must be satisfied.

In the parameters of the electrostatic device, the triggering voltage should be lower than the triggering voltage of the internal circuit device being bitten at the input / output, and the holding voltage should be higher than the operating voltage of the internal circuit device. In addition, the breakdown voltage should be between the operating voltage and the triggering voltage of the circuit device, which can be seen in FIG.

In order to develop an electrostatic device that satisfies these parameters, suitable bipolar transistors are also being studied.

Accordingly, in order to solve the above problems, an object of the present invention is to provide a method of manufacturing a bipolar transistor that can improve the efficiency of the emitter.

The method of manufacturing a bipolar transistor according to the present invention includes the steps of forming a first conductivity type deep well and a second conductivity type deep well by injecting a first conductivity type impurity and a second conductivity type impurity into a first conductivity type semiconductor substrate; Forming a second conductivity type well in the first conductivity type deep well, forming an emitter in the second conductivity type well, and forming a second conductivity type well in the first conductivity type deep well and the second conductivity type deep well. Forming a device isolation film to define a base region and a collector region, and implanting impurities into the base region and the collector region to form a base and a collector, respectively.

As described above, the method of manufacturing the bipolar transistor according to the present invention can improve the emitter efficiency and the triggering characteristics of the electrostatic device by additionally applying the N well to the emitter region.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

In addition, the terminology used in the present invention is a general term that is currently widely used as much as possible, but in certain cases, the term is arbitrarily selected by the applicant. In this case, since the meaning is described in detail in the description of the present invention, It is to be understood that the present invention is to be understood as the meaning of the term rather than the name.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments.

Hereinafter, a method of manufacturing a bipolar transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D illustrate a method of manufacturing a bipolar transistor according to the present invention.

First, as shown in FIG. 1A, a deep P-type well 12a is formed by deeply injecting P-type impurity ions into the P-type semiconductor substrate 10, and N-type impurities on both sides of the deep P-type well 12a. Ions are deeply implanted to form a deep N-type well 12b.

Thereafter, as shown in FIG. 1B, an N-type impurity ion is implanted into the emitter region where the emitter is to be formed in the deep P-type well 12a in a subsequent process to form the N-type well 14. In this case, the N-type well 14 may be formed shallower than the deep P-type well 12a and may be formed to have a larger width than the emitter region.

As such, by forming the N-type well 14 under the emitter region, it is possible to increase the doping concentration of the emitter without adding an existing process.

Subsequently, as shown in FIG. 1C, the N-type impurity ions are implanted into the emitter region in the N-type well 14 to form the emitter 16. In the device isolation film forming process, the device isolation film 18 for separating the collector region, the base region and the collector region is formed. In this case, the device isolation layer is formed between the emitter-base and the base-collector so that no lateral punch through is generated between the electrodes of the bipolar transistor, that is, the emitter, the base, and the collector, in the surface portion of the semiconductor substrate 10. It acts as a guard ring in between.

At this time, the distance between the device isolation film 18 formed between the emitter and the base is larger than the N-type well 14, it is preferable to be formed shallower than the depth of the N-type well 14.

Next, as shown in FIG. 1D, the base 20 is formed by implanting P-type impurity ions into the base region, and the collector 22 is formed by implanting N-type impurity ions into the collector region.

Subsequently, although not shown, a plug may be formed after forming an interlayer insulating film including contact holes in the emitter 16, the collector 22, and the base 20.

That is, the total emitter current IE is the sum of the current InE formed by the electrons of the emitter moving to the base and the current IpE by holes entering the emitter from the base.

Figure 112008090840700-PAT00001

The ratio between this total current and the actual useful current is called the emitter efficiency, which can be found by dividing the current (InE) formed by moving the emitter electrons to the base divided by the total current (IE). have.

Therefore, to increase the emitter efficiency, the actual current InE should be as large as possible and IpE should be as small as possible.

Here, the two currents (IpE, InE) depend on the majority carrier concentration of electrons in the emitter region and holes in the base region, even though they are exponentially dependent on forward bias, to maximize InE and minimize IpE. The doping concentration of the emitter should be high and the doping concentration of the base should be as low as possible.

That is, the present invention may have an effect of maximizing InE and minimizing IpE by increasing the doping concentration of the emitter by forming an N-type well under the emitter region. Due to this effect, the emitter efficiency can be increased without adding a process.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A to 1D illustrate a method of manufacturing a bipolar transistor according to the present invention.

Explanation of symbols on the main parts of the drawings

10: semiconductor substrate 12a: deep P-type well

12b: Dip N well 14: N well

16: emitter 18: device isolation film

20: base 22: collector

Claims (6)

Forming a first conductivity type deep well and a second conductivity type deep well by implanting a first conductivity type impurity and a second conductivity type impurity into the first conductivity type semiconductor substrate; Forming a second conductivity well in the first conductivity type deep well; Forming an emitter in the second conductivity type well, Defining a base region and a collector region by forming an isolation layer in the first conductivity type deep well and the second conductivity type deep well; And forming a base and a collector by injecting impurities into the base region and the collector region, respectively. The method of claim 1, And the second conductivity type well is wider than the emitter. The method of claim 1, And the device isolation film is formed to define respective regions between emitter-base and base-collector. The method of claim 3, wherein And a distance between the device isolation layers formed between the emitter and the base is greater than the size of the second conductivity type well. The method of claim 1, And the device isolation layer is formed to be shallower than the depth of the second conductivity type well. The method of claim 1, And the emitter and collector are formed by injecting a second conductivity type impurity, and the base is formed by injecting a first conductivity type impurity.
KR1020080137773A 2008-12-31 2008-12-31 Method for fabricating of bipolar junction transistor KR20100079333A (en)

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