KR20100079041A

KR20100079041A - Layout for semiconductor device

Info

Publication number: KR20100079041A
Application number: KR1020080137448A
Authority: KR
Inventors: 서광유
Original assignee: 주식회사 동부하이텍
Priority date: 2008-12-30
Filing date: 2008-12-30
Publication date: 2010-07-08

Abstract

PURPOSE: In the layout of the semiconductor device is one miss matching pattern, the parallel type, and the mirror type and vertical horizontal type are embodied. The whole test pattern area is reduced to 1/2 level. CONSTITUTION: The layout of the fourth transistor it scores the first of the semiconductor device comprises the gate region(140), the drift layer, and the drain region(144) within the drift layer and area-source(142). The first and second transistors(100, 102) are arranged the respective vertically in order to be each other opposite the gate region. The third and fourth transistors(104, 106) are arranged the respective vertically in order to be each other opposite the gate region. It is horizontal, the first and 3rd transistor and the second and fourth transistor are arranged.

Description

Layout of Semiconductor Device {LAYOUT FOR SEMICONDUCTOR DEVICE}

The present invention relates to a semiconductor device, and more particularly, to a layout of a semiconductor device capable of reducing the area of the layout.

Common structures used to analyze transistor mismatching characteristics include parallel type, mirror type, shared type, x-couple type, and fingers. Type (Finger Type) and the like are commonly used.

1 is a layout illustrating a matching structure of a general parallel type.

Referring to FIG. 1, a parallel type matching structure arrays two transistors 90 and 95 in parallel to connect a gate, a source, and a drain to each pad through metal routing to implement a circuit.

The two transistors 90 and 95 each have a gate region 40, a drain region 44 and a source region 42, each of which has at least one contact 12, based on a design rule. And metals connected to the circuit via 14, 16.

The first transistor 90 and the second transistor 95 are commonly connected to the gate pad 82 through one gate connection 80 through the gate contact hole 16 of each gate region 40, and each source The source contact hole 12 is connected to the source pad 52 through the source contact hole 12 of the region 42 in common.

Each drain region 44 of the first and second transistors 90 and 95 may have first and second drain pads 62 through the first and second drain terminals 60 and 70 through the drain contact hole 14. , 72).

2 is a layout illustrating a matching structure of a general mirror type.

Referring to FIG. 2, similar to a parallel type matching structure, the drain regions 44 are arranged to face each other between the first and second transistors 90 and 95.

The connection between each area and the pad is the same as the parallel type matching structure.

As described above, the parallel type or mirror type matching structure has a limit in reducing the area of a test pattern in which two transistors 90 and 95 are used as one circuit unit. In other words, as the device becomes more and more integrated, more unit cells are integrated in a limited area, and the layout area is gradually decreasing.

An object of the present invention is to provide a layout of a semiconductor device that can reduce the layout area.

The layout of the semiconductor device according to the embodiment of the present invention for achieving the above object is in the layout of the first and second transistors of the semiconductor device including a gate region, a drift region, a drain region and a source region in the drift region. The first and second transistors may be arranged in a vertical matching structure in a vertical direction so as to face each other with respect to the gate region.

The layout of a semiconductor device according to an embodiment of the present invention has the following effects.

Parallel, Mirror, and Vertical-Parallel Types can be implemented in one mismatching pattern, and the overall test pattern area is 1/2 compared to the conventional mismatching pattern. It is reduced to a level, which is advantageous for high integration of the device. In addition, not only a high voltage transistor structure but also a low voltage transistor structure is applicable.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

3 is a diagram showing the layout of a transistor in a symmetric structure according to the present invention.

3 is a structure in which parallel type and mirror type structures of a transistor mismatching structure are simultaneously implemented in one module.

Here, the first to fourth transistors 100, 102, 104, and 106, that is, four transistors are configured in one circuit unit. In the symmetrical transistor, source and drain regions 142 and 144 are formed on the left and right sides of the gate region 140. Since the source and drain regions 142 and 144 are processed in the same process, either side is formed. If the source region, the other side may be a drain region.

Each transistor can also be configured in a vertical-parallel type, which is advantageous for high voltage transistor mismatching characteristics.

The first and second transistors 100 and 102 and the third and fourth transistors 104 and 106 are vertically arranged so that the gate regions 140 face each other.

The first and second transistors 100 and 102 are vertically arranged in a mirror type such that the gate regions 140 face each other, and the first and third transistors 100 and 104 are horizontally parallel type ( Parallel type), and the second and fourth transistors 102 and 106 are horizontally arranged in a mirror type so that the source region 142 faces each other.

Each transistor 100, 102, 104, 106 includes a drain region 144, a gate region 140, and a source region 142.

The drain region 144 of the first transistor 100 is connected to the first drain connection part 120 through the drain contact hole 114, and the drain contact hole 114 is connected to the drain region 144 of the second transistor 102. Is connected to the second drain connector 122 through the drain contact hole 114 in the drain region 144 of the third transistor 104, and is connected to the third drain connector 124 through the drain contact hole 114. The drain region 144 of the 106 is connected to the fourth drain terminal 126 through the drain contact hole 114.

The first to fourth drain connectors 120, 122, 124, and 126 are connected to the first to fourth drain pads 201, 203, 205, and 207, respectively, and thus the first to fourth transistors 100 and 102. , 104 and 106 are driven respectively.

It is common with the first source connector 130 through the source contact hole 112 of the source region 142 of the first transistor 100 and the source contact hole 112 of the source region 142 of the second transistor 102. Connected to the second source connection part 132 through the source contact hole 112 of the source region 142 of the third transistor 104, and the source of the source region 142 of the fourth transistor 106. The third source connection part 134 is connected through the contact hole 112.

The first to third source connectors 130, 132, and 134 are commonly connected to the horizontal source connector 136, and the horizontal source connector 136 is connected to one source pad 211 through the vertical source connector 138. Connected.

The gate contact hole 116 of the gate region 140 of the first transistor 100 and the gate contact hole 116 of the gate region 140 of the second transistor 102 are common to the first gate connection 150. And a second gate connection portion 116 through the gate contact hole 116 of the gate region 140 of the third transistor 104 and the gate contact hole 116 of the gate region 140 of the fourth transistor 106. 152 is commonly connected.

The first and second gate connectors 150 and 152 are commonly connected to the horizontal gate connector 154, and the horizontal gate connector 154 is connected to one gate pad 209 through the vertical gate connector 156. .

The horizontal source connector 136 and the horizontal gate connector 154 are formed to overlap at different layers.

Here, a bias is applied to the first drain pad 201 connected to the first transistor 100 and the third drain pad 205 connected to the third transistor 104 to operate in parallel type ( Parallel type matching characteristics can be obtained, and a bias is applied to the second drain pad 203 connected to the second transistor 102 and the fourth drain pad 207 connected to the fourth transistor 106. When the operation is applied, the matching characteristic of the mirror type can be obtained.

In addition, a vertical-parallel type that may improve high voltage transistor mismatching characteristics may include a first drain pad 201 connected to the first transistor 100 and a second transistor 102. It can be obtained by connecting the second drain pad 203.

As such, the parallel type, mirror type, and vertical-parallel type may be implemented in one mismatching pattern, and the entire test pattern area may be smaller than the conventional mismatching pattern. It is reduced to 1/2 level, which is advantageous for high integration of the element. In addition, not only a high voltage transistor structure but also a low voltage transistor structure is applicable.

As described above, the structure for reducing the test pattern region for the mismatching characteristic is also possible in the symmetric structure as shown in FIG. 4. Referring to FIG. 4, the first to fourth transistors 100, 102, 104, and 106, that is, four transistors are configured in one circuit unit. Since the arrangement of the transistors 100, 102, 104, and 106 of FIG. 4 is overlapped with that of FIG. 3, a redundant configuration will be omitted.

In the symmetrical transistor, source and drain regions 142 and 144 are formed on the left and right sides of the gate region 140, and the shapes of the source and drain regions 142 and 144 are determined differently. It is formed.

When the high voltage transistor structure is formed, an N-drift or P-drift process may be performed according to the type of the transistor to increase the operating voltage. ) Or P-type impurities are implanted to form the P-drift region (D). In the high voltage transistor matching structure having an associative structure, only one of the N-drift region and the P-drift region exists.

As such, the parallel type, mirror type, and vertical-parallel type may be implemented in one mismatching pattern, and the entire test pattern area may be smaller than the conventional mismatching pattern. It is reduced to 1/2 level, which is advantageous for high integration of the device. In addition, it can be applied not only to the high voltage transistor structure but also to the low voltage transistor structure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a layout illustrating a matching structure of a general parallel type.

2 is a layout illustrating a matching structure of a general mirror type.

4 is a diagram showing the layout of a transistor in an symmetric structure according to the present invention.

100, 102, 104, 106: transistor 112, 114, 116: contact hole

140: gate region 142: source region

144: drain region P: pad

D: drift area

Claims

In the layout of the first to fourth transistors of the semiconductor device including a gate region, a drift region, a drain region and a source region in the drift region,

The first and second transistors are vertically arranged to face the gate area to each other, and the third and fourth transistors are respectively vertically arranged to face the gate area to each other. And the second and fourth transistors are arranged horizontally.

The method of claim 1,

The first and second transistors are arranged in a mirror type vertically such that the gate regions face each other, the first and third transistors are arranged in a horizontal parallel type, and the second and fourth transistors are arranged in the source region. The semiconductor device layout, characterized in that arranged in a mirror type horizontally facing each other.

The method of claim 1,

A gate contact hole formed in the gate region;

A drain contact hole formed in the drain region;

And a source contact hole formed in the source region.

The method of claim 3, wherein

A first drain connection part connected to the drain region of the first transistor through the drain contact hole of the first transistor;

A second drain connection portion connected to the drain region of the second transistor through the drain contact hole of the second transistor;

A third drain connection part connected to the drain region of the third transistor through the drain contact hole of the third transistor;

A fourth drain connection portion connected to the drain region of the fourth transistor through the drain contact hole of the fourth transistor;

And first to fourth drain pads connected to the first to fourth drain connection portions, respectively.

The method of claim 3, wherein

A first source connection portion for connecting the source contact hole of the source region of the first transistor and the source contact hole of the source region of the second transistor in common;

A second source connection part connected to the source region of the third transistor through the source contact hole of the third transistor;

A third source connection part connected to the source region of the fourth transistor through the source contact hole of the fourth transistor;

And a source pad connected to the first to third source connection parts in common.

The method of claim 3, wherein

A first gate connection portion for commonly connecting the gate contact hole in the gate region of the first transistor and the gate contact hole in the gate region of the second transistor;

A second gate connection portion for commonly connecting the gate contact hole in the gate region of the third transistor and the gate contact hole in the gate region of the fourth transistor;

And a gate pad connected in common with the first and second gate connectors.