KR20100078222A - Voltage generation circuit - Google Patents

Abstract

PURPOSE: A voltage generation circuit is provided to change an element characteristic change into a proper level, thereby preventing yield drop. CONSTITUTION: A voltage detection unit detects level of threshold voltage. A threshold voltage detection unit output a detection signal. A voltage(140) selects one among a plurality of distribution voltages. A voltage selection unit output a selection voltage. A inside voltage generation unit(150) generation inside voltage by using selection voltage. A voltage distribution unit(120) distributes a standard voltages into different resistance ratio.

Description

Voltage Generation Circuitry {VOLTAGE GENERATION CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor circuits, and more particularly to voltage generating circuits.

As shown in FIG. 1, the voltage generation circuit according to the related art includes a band gap reference generator (BGR) 11, a first level shifter 12, a distribution resistor 13, and a second level. The shifter 14 is provided.

The band gap reference circuit 11 generates a reference voltage VERF.

The first level shifter 12 generates a voltage having a level corresponding to twice the reference voltage VERF.

The distribution resistor 13 divides the voltage output from the first level shifter 12 and outputs distribution voltages of various levels.

The second level shifter 14 selects a divided voltage corresponding to half of a target internal voltage (eg, VPERI) level among the divided voltages distributed through the distribution resistor 13, and doubles the divided voltage. A voltage of a corresponding level is generated and output as an internal voltage VPERI.

In the conventional voltage generation circuit configured as described above, when the circuit configuration is completed such that a desired level of the internal voltage VPERI is generated, the level of the internal voltage VPERI remains constant regardless of the characteristics of the device, that is, the transistor.

Therefore, when the characteristic change of the device occurs according to the change of operating environment, that is, when the threshold voltage of the transistor is lowered, the consumption current increases, and conversely, when the threshold voltage is increased, the operating speed is lowered. There is a problem of deterioration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage generation circuit capable of preventing a decrease in yield due to changes in device characteristics.

A voltage generation circuit according to the present invention includes: a threshold voltage detector configured to detect a level of a threshold voltage and output a detection signal; A voltage selector configured to select one of a plurality of divided voltages and output a selection voltage in response to the detection signal; And an internal voltage generator configured to generate an internal voltage using the selection voltage.

The voltage generation circuit according to the present invention includes: a threshold voltage detector configured to decode signals comparing a first threshold voltage and a second threshold voltage with respective target voltages, and output a detection signal; A voltage selector configured to select one of a plurality of divided voltages and output a selection voltage in response to the detection signal; And an internal voltage generator configured to generate an internal voltage using the selection voltage.

The voltage generation circuit according to the present invention can vary the internal voltage to a level suitable for the change in device characteristics, thereby preventing a decrease in yield.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram of a voltage generation circuit according to the present invention.

As shown in FIG. 2, the voltage generation circuit according to the present invention includes a band gap reference generator (BGR) 110, a voltage divider 120, a threshold voltage detector 130, and a voltage selector ( 140 and an internal voltage generator 150.

The band gap reference generator (BGR) 110 is configured to compensate for temperature variations to produce a constant reference voltage (VERF).

The voltage divider 120 divides the reference voltage VERF with a different resistance ratio to generate a plurality of divided voltages V <A: G>.

The threshold voltage detector 130 decodes signals obtained by comparing internally generated first and second threshold voltages with a plurality of target voltages to detect detection signals S <1: 3> and Sb <1: 3>. It is configured to output. At this time, the detection signal Sb <1: 3> is a signal having a logic value opposite to that of the detection signal S <1: 3>.

The first threshold voltage is a threshold voltage of a PMOS transistor, and the second threshold voltage is a threshold voltage of an NMOS transistor.

The voltage selector 140 selects one of the plurality of divided voltages V <A: G> in response to the detection signals S <1: 3> and Sb <1: 3> to select a selection voltage ( VSEL).

The internal voltage generator 150 is configured to level shift the selection voltage VSEL by a predetermined multiple (for example, 2 times) to output the internal voltage VPERI.

3 is a circuit diagram of the voltage divider, the voltage selector, and the internal voltage generator of FIG. 2.

As shown in FIG. 3, the voltage divider 120 includes a level shifter 121 and a divider resistor 122.

The level shifter 121 includes a differential amplifier OP1, a transistor M1, and active resistors RM1 and RM2. The level shifter 121 is configured to generate a voltage NO at a level corresponding to twice the reference voltage VERF regardless of a change in the external voltage VDD.

The distribution resistor 122 includes a plurality of resistor elements connected between the drain of the transistor M1 and the ground terminal VSS, and divides the voltage N0 through the plurality of resistor elements to divide the plurality of distribution voltages. And generate (V <A: G>).

The voltage selector 140 includes a plurality of pass gates PG1 to PG3. The plurality of pass gates PG1 to PG3 select one of a plurality of divided voltages VE, VD, and VC according to the detection signals S <1: 3> and Sb <1: 3> to select a selected voltage ( VSEL).

The internal voltage generator 150 includes a level shifter 151. The level shifter 151 includes a differential amplifier OP2, a transistor M2, and active resistors RM3 and RM4. The level shifter 151 is configured to generate an internal voltage VPERI of a level corresponding to twice the selection voltage VSEL regardless of a change in the external voltage VDD.

4 is a circuit diagram of the threshold voltage detector of FIG. 2.

As shown in FIG. 4, the threshold voltage detector 130 includes a threshold voltage generator 131, a comparator 132, and a decoder 133.

The threshold voltage generator 131 has a PMOS transistor MP1 and a source connected to the power terminal VINT and connected to the ground terminal VSS through a drain resistance, and a source connected to the ground terminal VSS. An NMOS transistor MN1 is connected to the power supply terminal VINT through a resistor. The first threshold voltage N1 is output through the node connected to the drain and gate of the PMOS transistor MP1, and the second threshold voltage N2 is output from the node connected to the drain and gate of the NMOS transistor. The PMOS transistor MP1 and the NMOS transistor MN1 are manufactured by the same process as the transistor manufacturing process of the semiconductor device to which the voltage generation circuit according to the present invention is applied.

The comparison unit 132 includes a plurality of differential amplifiers OP11 to OP14 and a plurality of resistors R11 to R18 connected between the power supply terminal VINT and the ground terminal VSS. The comparison unit 132 is configured to compare the first and second threshold voltages N1 and N2 with a plurality of range determination reference voltages N3 to N9 to output a plurality of comparison signals O to R. . The power source VINT is a power source that maintains a constant level independent of the internal voltage VPERI regardless of the external voltage VDD. Resistance values of the plurality of resistors R11 to R18 are set such that the plurality of range determination reference voltages N3 to N9 have voltage levels VINT-Vtp0 + B to Vtn-0. The voltage fluctuation values A and B of the plurality of range determination reference voltages N3 to N9 may cause a decrease in yield due to a change in the consumption current or the operating speed generated due to the voltage fluctuation values A and B. It is a value set through simulation within a range that does not affect.

The decoder 133 includes a plurality of inverters IV11 to IV13, a NOR gate NR11, and a plurality of NAND gates ND11 and ND12. The decoder 133 is configured to decode the plurality of comparison signals O to R to output the detection signals S <1: 3> and Sb <1: 3>.

TABLE 1

Vtp Vtn N1 area N2 area O P Q R S1 S2 S3 High High PNH PNH L L L L H L L Low Low PL NL H H H H L L H Med Med PM NM L H H L L H L High Low PNH NL L L H H L H L Low High PL PNH H H L L L H L

At this time, PNH is when the threshold voltage (Vtp) of the PMOS transistor and the threshold voltage (Vtn) of the NMOS transistor are both higher than the target value by a certain level or more, PM is when Vtp does not differ from the target value by a certain level or more. PL denotes a case where Vtp is lower than the target value by a certain level or more. NM means that the Vtn is not different from the target value by a certain level or more, and NL means that Vtn is lower than the target value by a certain level or more.

The operation of the voltage generation circuit according to the present invention configured as described above will be described with reference to Table 1.

First, a threshold voltage detection operation will be described with reference to FIG. 4.

The PMOS transistor MP1 and the NMOS transistor MN1 of the threshold voltage generator 131, that is, the first threshold voltage N1 and the second threshold voltage N2 are generated through the active element.

The first threshold voltage N1 and the second threshold voltage N2 generated by the active element may change to a level different from a target value to reflect a change in an operating environment.

On the other hand, a plurality of resistors (R11 ~ R18), that is, a plurality of range determination reference voltages (N3 ~ N9) generated through the passive element is the variation range of the first threshold voltage (N1) and the second threshold voltage (N2) It varies within a much smaller range. That is, it can be seen that it is kept constant.

The differential amplifiers OP11 and OP12 compare the second threshold voltage N2 and the reference voltages N9 and N7 for range determination, and the differential amplifiers OP13 and OP14 compare the first threshold voltage N1 and the range determination reference. The voltage (N5, N3) is compared to output a high (H) or low (L) value.

As shown in Table 1, the ranges to which N1 and N2, that is, Vtp and Vtn belong, can be known through the output values O to R of the differential amplifiers OP11 to OP14. That is, it is possible to detect whether the threshold voltage of the transistor used in the semiconductor device is within the target value and within a predetermined level or whether the threshold voltage is higher or lower than the target value by a predetermined level or more.

As described above, after the threshold voltage detection is completed, an operation of adjusting the level of the internal voltage VPERI according to the detected result will be described with reference to Table 1.

For example, if Vtp and Vtn are both above or below a certain level (excluding Vtp = Vtn = High and Vtp = Vtn = Low), then the output values of the differential amplifiers (OP11 to OP14) (O to R) are high (H) and low (L) mixed. Therefore, the decoder 133 decodes the signal and outputs a detection signal S1 = L, S2 = H, and S3 = L.

The pass gates PG2 of the voltage selector 140 of FIG. 3 are turned on according to the detection signals S1 = L, S2 = H, and S3 = L, and the remaining pass gates PG1 and PG3 are turned off.

Accordingly, the internal voltage generator 150 generates an internal voltage VPERI having a level corresponding to twice the division voltage VD, that is, an internal voltage VPERI having a normal level.

On the other hand, when both Vtp and Vtn are higher than the target value by a certain level (Vtp = High, Vtn = High), the output values O to R of the differential amplifiers OP11 to OP14 are all low (L). Therefore, the decoder 133 decodes the signal and outputs a detection signal S1 = H, S2 = L, and S3 = L.

The pass gates PG1 of the voltage selector 140 of FIG. 3 are turned on according to the detection signals S1 = H, S2 = L, and S3 = L, and the other pass gates PG2 and PG3 are turned off.

Accordingly, the internal voltage generator 150 generates an internal voltage VPERI having a level corresponding to twice the division voltage VE. That is, the internal voltage VPERI having a higher level than the internal voltage VPERI of the normal level is generated.

On the other hand, when both Vtp and Vtn are lower than the target value by a certain level (Vtp = Low, Vtn = Low), the output values (O to R) of the differential amplifiers (OP11 to OP14) are all high (H). Therefore, the decoder 133 decodes the signal and outputs a detection signal S1 = L, S2 = L, S3 = H.

The pass gates PG3 of the voltage selector 140 of FIG. 3 are turned on according to the detection signals S1 = L, S2 = L, and S3 = H, and the other pass gates PG1 and PG2 are turned off.

Accordingly, the internal voltage generator 150 generates an internal voltage VPERI having a level corresponding to twice the division voltage VC. That is, an internal voltage VPERI having a level lower than that of the normal level VPERI is generated.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a voltage generation circuit according to the prior art,

2 is a block diagram of a voltage generation circuit according to the present invention;

3 is a circuit diagram of a voltage divider, a voltage selector, and an internal voltage generator of FIG. 2;

4 is a circuit diagram of the threshold voltage detector of FIG. 2.

<Description of the symbols for the main parts of the drawings>

110: band gap reference generator 120: voltage divider

130: threshold voltage detector 140: voltage selector

150: internal voltage generator

Claims (15)

A threshold voltage detector configured to detect a level of the threshold voltage and output a detection signal; A voltage selector configured to select one of a plurality of divided voltages and output a selection voltage in response to the detection signal; And And an internal voltage generator configured to generate an internal voltage using the selection voltage. The method of claim 1, And a voltage divider configured to divide the reference voltages with different resistance ratios to generate the plurality of divided voltages. The method of claim 1, The threshold voltage detector A voltage generation configured to generate the detection signal by detecting whether the level of the threshold voltage is higher than or equal to a target level by a predetermined level, higher than or equal to a target level, or lower than or equal to the target level by a predetermined level Circuit. The method of claim 2, The threshold voltage detector A threshold voltage generator configured to generate the threshold voltage; A comparison unit configured to output the plurality of comparison signals by comparing the threshold voltage with a plurality of range determination reference voltages; And a decoder configured to decode the plurality of comparison signals to output the detection signal. The method of claim 4, wherein The threshold voltage generator PMOS transistors whose source is connected to the power stage, A first resistance element connected between the drain of the PMOS transistor and a ground terminal; An NMOS transistor whose source is connected to the ground terminal, and A second resistance element connected between the drain and the power terminal of the NMOS transistor, And a first threshold voltage is output through a node connected to the drain and gate of the PMOS transistor, and a second threshold voltage is output to a node connected to the drain and gate of the NMOS transistor. The method of claim 4, wherein The comparison unit And a plurality of differential amplifiers for comparing the threshold voltage and the plurality of range determination reference voltages, respectively. The method of claim 1, The detection signal is composed of a plurality of bits, The voltage selector And a plurality of switching elements for passing one of the plurality of distribution voltages as the selection voltage in accordance with each of the plurality of bits of the detection signal. The method of claim 1, The internal voltage generator And a level shifter for outputting a voltage of a level corresponding to a predetermined multiple of the level of the selected voltage as the internal voltage. A threshold voltage detector configured to decode signals comparing the first threshold voltage and the second threshold voltage with respective target voltages and output a detection signal; A voltage selector configured to select one of a plurality of divided voltages and output a selection voltage in response to the detection signal; And And an internal voltage generator configured to generate an internal voltage using the selection voltage. The method of claim 9, And a voltage divider configured to divide the reference voltages with different resistance ratios to generate the plurality of divided voltages. The method of claim 9, The threshold voltage detector A threshold voltage generator configured to generate the first threshold voltage using a PMOS transistor and to generate the second threshold voltage using an NMOS transistor; A comparator configured to compare the first threshold voltage and the plurality of first target voltages, and compare the second threshold voltage and the plurality of second target voltages to output a plurality of comparison signals; and And a decoder configured to decode the plurality of comparison signals to output the detection signal. The method of claim 11, The threshold voltage generator A first resistance element connected between the drain and the ground terminal of the PMOS transistor, And A second resistance element connected between the drain and the power terminal of the NMOS transistor, And the first threshold voltage is output through the node connected to the drain and gate of the PMOS transistor, and the second threshold voltage is output from the node connected to the drain and gate of the NMOS transistor. The method of claim 11, The comparison unit A plurality of first differential amplifiers for comparing the first threshold voltage with the plurality of first target voltages, and And a plurality of second differential amplifiers for comparing the second threshold voltage and the plurality of second target voltages. The method of claim 9, The detection signal is composed of a plurality of bits, The voltage selector And a plurality of switching elements for passing one of the plurality of distribution voltages as the selection voltage in accordance with each of the plurality of bits of the detection signal. The method of claim 9, The internal voltage generator And a level shifter for outputting a voltage of a level corresponding to a predetermined multiple of the level of the selected voltage as the internal voltage.

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