KR20100076749A - Metal array in flash memory device - Google Patents

Abstract

PURPOSE: A wiring array of a flash memory device is provided to reduce the area resistance by increasing an area of a real line as much as the area of the dummy line by connecting a real line and a dummy line in parallel to form a parallel current path. CONSTITUTION: A wiring array comprises one or more of dummy line(DL) among a plurality of real lines(RL). A first connecting unit(CT1) and a second connecting unit(CT2) connect the dummy line and the real line, respectively. The dummy line comprises a starting part and an ending part. The dummy line is formed with the same pitch as the real line.

Description

Wiring array of flash memory device {METAL ARRAY IN FLASH MEMORY DEVICE}

A wiring structure of a nonvolatile memory device, and more particularly, an array of wirings connected to a page buffer end of a NAND type flash memory device is disclosed.

In recent years, as the device is highly integrated, the line width of the wiring also decreases, increasing the sheet resistance of the wiring. Increasing the sheet resistance of the wiring has adverse effects on the device characteristics, one of which is malfunction of the device due to signal delay.

In particular, in a flash memory device, the page buffer includes metal wires for data transfer between the input / output pads and the memory cells. When the resistance Rs of the wires is increased, the chip buffer cannot transmit signals properly during data input and output. The problem itself is happening.

Accordingly, an object of the present invention is to provide a wiring array capable of reducing sheet resistance of a metal wiring of a page buffer in a flash memory.

A wiring array of an improved flash memory device for achieving the above object includes a wiring connected with a page buffer, the wiring extending in a direction parallel to the actual wiring, and its starting end branched from the actual wiring. And a dummy part and a connection part for connecting the dummy wire and the actual wire at an end of the dummy wire.

According to the present invention including the above configuration, by connecting the actual wiring and the dummy wiring in parallel to form a parallel current path to increase the area of the actual wiring by the area of the dummy wiring to reduce the sheet resistance, thereby through the page buffer Signal delay and fail in the data input / output process can be reduced.

1 is a plan view schematically illustrating a wiring array of an improved page buffer.

Referring to FIG. 1, a wiring array includes one or a plurality of dummy wirings DL between a plurality of actual wirings RL. The apparatus further includes first and second connection parts CT1 and CT2 for connecting the dummy wiring DL and the actual wiring RL, respectively.

The dummy wiring DL has a start end and an end, and is formed at the same pitch as the actual wiring RL. That is, the line width W and the interval S (the gap between the dummy wiring and the actual wiring or the gap between the dummy wiring) are the same. In addition, the dummy wiring DL has a shorter length than the actual wiring RL. In addition, a plurality of dummy wires DL may be formed in the long axis length direction of the actual wires RL. In addition, the dummy wiring DL is formed to have different long axis lengths.

An end (or start) of the dummy wiring DL is formed at a point (around) in contact with the pad portion (not shown). Here, the pad portion is formed in a part of the actual wiring RL to interconnect the actual wiring RL disposed on the upper and lower layers through a conductive layer such as a contact plug. The pad portion is formed to have a large line width within the same pitch as neighboring wirings (including dummy wirings and actual wirings). For this reason, the distance between the pad portion and the adjacent wiring is reduced, which may cause an electrical short with the adjacent wiring. Therefore, the end of the dummy wiring DL is positioned at a point adjacent to the pad part, thereby preventing an electrical short circuit with the adjacent wiring.

The first connection part CT1 connects the start end of the dummy wiring DL and the actual wiring RL, and the second connection part CT2 connects the end end of the dummy wiring DL and the actual wiring RL. The first and second connectors CT1 and CT2 are formed integrally with the actual wiring RL and the dummy wiring DL, or after forming the actual wiring RL and the dummy wiring DL, a separate conductive material is formed. It can be formed by depositing. In the case of the integrated type, it is formed at the same time during the actual wiring RL and the dummy wiring DL.

Meanwhile, when another dummy wiring DL (hereinafter referred to as a second dummy wiring) exists between the dummy wiring DL (hereinafter referred to as a first dummy wiring) and the actual wiring RL, the first and the second The two dummy wirings DL may be connected to each other, or the actual wiring RL may be directly connected to the first dummy wiring DL.

As described above, the wiring array of the semiconductor device according to the present invention substantially connects the actual wiring RL and the dummy wiring DL to form a parallel current path, thereby substantially reducing the area of the actual wiring RL to the dummy wiring DL. It is possible to obtain an effect of reducing the sheet resistance by increasing the area by.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, parts denoted by the same reference numerals (or reference numerals) throughout the specification represent the same components.

Example

2 is a plan view illustrating a wiring array of a semiconductor device in accordance with an embodiment of the present invention. 2 illustrates wirings connected to the page buffer stage of a nonvolatile memory device as an example. Here, the wiring connected to the page buffer terminal may be a wiring (bit line) connecting the page buffer and the memory cell or a wiring connecting the page buffer and the input / output pad.

As shown in FIG. 2, in the wiring array of the semiconductor device according to the exemplary embodiment of the present invention, the actual wiring RL and the dummy wiring DL branch from each other at the end of the page buffer PB. That is, at the point where the end of the page buffer PB and the actual wiring RL are connected, the dummy wiring DL branches from the actual wiring RL and extends in parallel with the actual wiring RL. In addition, the end of the dummy wiring DL is connected to the actual wiring RL through the connecting portion CT (see circular section).

Hereinafter, the operating characteristics of the wiring array of the semiconductor device according to the present invention will be described.

3 is a circuit diagram illustrating a page buffer stage as an example. 4 and 5 are diagrams illustrating the resistance value Rmax of the wiring resistance R in the pull-down current path PD of the page buffer stage shown in FIG. 3. 4 is a view measured before connecting the dummy wiring DL to the actual wiring RL, and FIG. 5 is a view measured after connecting the dummy wiring DL to the actual wiring RL. At this time, the wiring has a 48 nm line width. In addition, the measurement was performed at normal temperature (25 degreeC).

Referring to FIG. 4, it can be seen that in the wiring array structure in which the dummy wiring DL is not connected, the maximum resistance value Rmax of the resistor R is about 7.5KΩ when the power supply voltage VDD is around 3.7V. In contrast, referring to FIG. 5, in the wiring array structure in which the dummy wiring DL is connected, the maximum resistance value Rmax of the resistor R is approximately 6.8 KΩ when the power supply voltage VDD is around 3.7V. have. That is, in the wiring array structure in which the dummy wiring DL is connected to the actual wiring RL, the maximum resistance value of the resistor R is 7.5 compared to the wiring array structure in which the dummy wiring DL is not connected to the actual wiring RL. We can see that it decreased from KΩ to 6.8KΩ (approximately 0.7KΩ).

Meanwhile, in FIG. 3, 'PM' means PMOS transistor and 'NM' means NMOS transistor.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, although the embodiment of the present invention has been described using the page buffer stage as an example, this is for convenience of description, and it can be applied to the wiring array structure in which the dummy wiring is arranged in parallel with the actual wiring. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a plan view schematically illustrating a wiring array of an improved page buffer.

2 is a photo showing a wiring array structure of a page buffer stage of a flash memory according to an embodiment of the present invention.

3 is a circuit diagram illustrating a page buffer stage of a nonvolatile memory device as an example.

FIG. 4 shows the resistance value Rmax of the wiring resistance R before connecting the dummy wiring DL to the actual wiring RL in the pull-down current path PD of the page buffer stage shown in FIG. 3. ).

FIG. 5 shows the resistance value Rmax of the wiring resistance R after connecting the dummy wiring DL to the actual wiring RL in the pull-down current path PD of the page buffer stage shown in FIG. 3. ).

Description of the Related Art

RL: actual wiring

DL: Dummy Wiring

CT, CT1, CT2: Connection

PB: page buffer

Claims (8)

A wiring connected to the page buffer, The wiring, A dummy wiring extending in a direction parallel to the actual wiring and whose starting end is branched from the actual wiring; And A connection part connecting the dummy wire and the actual wire at an end of the dummy wire; Wiring array of flash memory devices. The method of claim 1, The wiring line is a bit line connected between the page buffer and the memory cell. Wiring array of flash memory devices. The method of claim 1, The wiring is a wiring connected between the page buffer and the input / output pad. Wiring array of flash memory devices. The method according to any one of claims 1 to 3, The dummy wiring is composed of a plurality Wiring array of flash memory devices. The method of claim 4, wherein The plurality of dummy wires may have different long axis lengths, and the gaps between the plurality of dummy wires may be equal to each other. Wiring array of flash memory devices. The method according to any one of claims 1 to 3, And the actual wiring and the dummy wiring are formed to have the same line width with each other. The method according to any one of claims 1 to 3, The long axis length of the actual wiring is formed longer than the long axis length of the dummy wiring Wiring array of flash memory devices. The method according to any one of claims 1 to 3, An end of the dummy wire is connected to a pad having a line width larger than that of the dummy wire. Wiring array of flash memory devices.

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