KR20100076523A - Unit pixel in image sensor and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A unit pixel of an image sensor and a manufacturing method thereof are provided to optimize the potential barrier of the channel area formed at the lower part of a gate by differently forming the doped concentration of a gate adjacent to a floating diffusion part and a gate adjacent to a photo diode. CONSTITUTION: A doped region is formed in a gate(140) and one side and the other side from the center of a channel region(120) have different impurity distribution. A photo diode(160) is formed in a semiconductor substrate(100) in order to be aligned with one side of the gate. A floating diffusion part(170) is formed in the semiconductor substrate in order to be aligned with the other side of the gate. The doped region contiguous to the photo diode is formed with wholly uniform impurity distribution and the doped region contiguous to the floating diffusion part is formed only in the shallow region of the gate.

Description

Unit pixel in image sensor and method for manufacturing thereof

An embodiment relates to a unit pixel of an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is largely a charge coupled device (CCD) and a CMOS (Complementary Metal Oxide Silicon) image sensor. Sensor (CIS).

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel in a switching method of forming a photodiode and a MOS transistor in the unit pixel.

The unit pixels of the CMOS image sensor are classified into 3T type, 4T type, 5T type, and the like according to the number of transistors. The 3T type consists of three transistors of one photodiode, and the 4T type consists of one photodiode and four transistors.

FIG. 1 is a circuit diagram of a general 4T type pixel, and FIG. 2 is a diagram illustrating a layout of a unit pixel illustrated in FIG. 1.

1 and 2, a unit pixel of an image sensor includes one photodiode (PD) and four NMOSs. Specifically, a photodiode PD that receives light to generate photocharges, a transfer transistor for transferring the photocharges collected from the photodiode PD to the floating diffusion region FD, a desired A reset transistor (ResetTr), a source follower buffer amplifier (Source Follower Buffer Amplifier) for setting the potential of the floating diffusion region to a value and discharging the charge Cpd to reset the floating diffusion region FD. A drive transistor (Drive Tr), which plays a role, and a select transistor (Select Tr), which allows addressing as a switching role. Outside the unit pixel, a load transistor is formed to read an output signal.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

Referring to FIG. 3, a channel region 30 is formed in a semiconductor substrate 10 on which a field oxide film 20 for device isolation is formed, and a gate insulating film 40 and a polygate 50 are formed on the semiconductor substrate 10. ) Is stacked and aligned on one side of the polygate 50 to form a photodiode 60 on the semiconductor substrate 10, and aligned on the other side of the polygate 50 to the semiconductor substrate 10. Floating diffusion portion 70 is formed.

In operation of the image sensor, when light is incident on the photodiode 60 and photocharge occurs, the gate 50 of the transfer transistor is turned on. Then, the threshold voltage controlled by the channel is lowered so that the photocharge generated by the photodiode 60 can be transferred to the floating diffusion 70 through the channel. The photoelectric charge goes to the output signal through the voltage buffer of the drive transistor Dx together with the reset signal generated by the turn-on of the reset transistor Rx, and then the difference signal between the two signals is quantized in the CDS circuit. Processing is done.

Meanwhile, the channel region 30 of the transfer transistor is formed by uniformly injecting ions into the entire active region of the semiconductor substrate 10 to determine the turn-on voltage of the gate 50. In addition, the gate 50 for operating the channel region 30 is formed by patterning a conductive material such as polysilicon. Accordingly, the same turn-on voltage is applied to the gate 50, and the entire channel region 30 under the gate 50 can be turned on at the same time.

In this case, a potential barrier that may affect the charge transfer characteristics is formed at the boundary between the photodiode 60 and the gate 50 to tune for photodiode capacity adjustment. Photodiode Implant Can be shaken greatly depending on the dose and energy conditions. For example, when the n-type dose is increased, the barrier becomes too low and the dark signal may increase. Alternatively, when a p-type dose is increased to reduce dark signals, an image lag may increase.

In an embodiment, an image sensor capable of optimizing the potential barrier of a channel region formed under the gate by differently forming a doping concentration of a gate adjacent to the photodiode and a gate adjacent to the floating diffusion based on the center of the gate of the transfer transistor. Provides unit pixels of.

The unit pixel of the image sensor according to the embodiment may include a semiconductor substrate in which a transistor predetermined region is defined; A channel region formed in the semiconductor substrate corresponding to the transistor predetermined region; A gate insulating film formed on the channel region; A gate formed on the gate insulating film; A doped region formed inside the gate and having an impurity distribution different from one side and the other region with respect to the center of the channel region; A photodiode formed inside the semiconductor substrate to be aligned with one side of the gate; And a floating diffusion formed in the semiconductor substrate to be aligned to the other side of the gate, wherein the doped region adjacent to the photodiode is formed with a uniform impurity distribution as a whole, and the doped region adjacent to the floating diffusion is It includes only formed in the shallow region of the gate.

A method of manufacturing a unit pixel of an image sensor according to an embodiment includes preparing a semiconductor substrate in which a transistor predetermined region is defined; Forming a channel region on the semiconductor substrate corresponding to the transistor predetermined region; Forming a gate insulating film and a gate on the channel region; Forming a first doped layer to have a first depth inside the gate corresponding to one side with respect to the center of the channel region; Forming a second doped layer in the gate to have a second depth deeper than a first depth in contact with the first doped layer; Forming a third doped layer to have a first depth inside the gate corresponding to the other side with respect to the center of the channel region; Forming a photodiode in the semiconductor substrate to be aligned with one side of the gate; And forming a floating diffusion in the semiconductor substrate to be aligned with the other side of the gate.

According to the embodiment, the doping distribution of the gate of the transfer transistor is adjusted to move the potential barrier to the center of the channel region to optimize the gate voltage.

A unit pixel of the image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

8 is a cross-sectional view illustrating a unit pixel of an image sensor according to an exemplary embodiment.

The image sensor according to the embodiment includes a semiconductor substrate 100 in which a transistor predetermined region TA is defined, a channel region 120 formed in the semiconductor substrate 100 corresponding to the transistor predetermined region TA, A gate insulating layer 130 formed on the channel region 120, a gate 140 formed on the gate insulating layer 130, and formed in the gate 140 and based on a center of the channel region 120. The doped region having different impurity distributions on one side and the other side, and the photodiode 160 formed inside the semiconductor substrate 100 so as to be aligned on one side of the gate 140, and the other side of the gate 140. And a floating diffusion unit 170 formed in the semiconductor substrate 100.

For example, the gate 140 may be formed of polysilicon. The doped region may be formed of n-type impurities.

The doped region adjacent to the photodiode 160 may be formed with a uniform impurity distribution. In addition, the doped region adjacent to the floating diffusion 170 may be formed only in the shallow region of the gate 140, and the doped regions formed on one side and the other side of the gate 140 may have different impurity distributions. .

In more detail, the doped region includes a first doped layer 151 formed to have a first depth T1 in the gate 140 corresponding to one side of the channel region 120, and the first doped region 151. And a second doped layer 152 formed below the first doped layer 151 to be adjacent to the first doped layer 151 and having a second depth T2 that is deeper than the first depth T1. do. One side of the gate 140 may have a uniform doping concentration by the first and second doping layers 151 and 152.

The doped region includes a third doped layer 153 formed to have a first depth T1 in the gate 140 corresponding to the other side of the channel region 120. . The third doped layer 153 may be selectively formed only in a shallow region inside the gate 140.

The first doped layer 151 and the second doped layer 152 are formed to have a uniform concentration and distribution on the gate 140 corresponding to one side of the channel region 120 with respect to the center of the voltage. As the drop decreases, it may be turned on by the low voltage (Low Vth). In addition, the third doped layer 153 may be selectively formed only in a shallow region of the gate 140 corresponding to the other side of the channel region 120 so as to form a first region with the channel region 120. It may be spaced apart with the width D1. That is, the third doped layer 153 may be formed to have a non-uniform concentration and distribution so that a voltage drop is generated and turned on by a high voltage (High Vth).

Therefore, in the embodiment, the turn-on Vth of the gate 140 may be applied with the high voltage High Vth based on the channel region 120 corresponding to the third doped layer 153. . In addition, since the third doped layer 153 is formed on the other side with respect to the center of the channel region 120, a potential barrier is spaced apart from the photodiode 160 to the center of the channel region 120. Can be moved.

A potential barrier, which is difficult to adjust at the entrance of the gate 140 of the transfer transistor, due to an implant dose for forming a capacitor of the photodiode 160, is formed in the first gate of the gate 140. The first to third dopant layers 151, 152, and 153 may be moved to a central region to improve signal transfer efficiency of photocharges by optimizing the gate voltage Vth.

Unexplained reference numerals among the reference numerals of FIG. 8 will be described in the following manufacturing method.

4 to 8, a method of manufacturing a unit pixel of an image sensor according to an exemplary embodiment will be described.

Referring to FIG. 4, a channel region 120 is formed in the semiconductor substrate 100.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. For example, the semiconductor substrate 100 may be a p-type (p ++) substrate, and a low concentration p-type epitaxial layer may be formed by performing an epitaxial process on the semiconductor substrate 100.

An isolation layer 110 is formed on the semiconductor substrate 100 to define an active region. The device isolation layer 110 may be formed by an STI process. In addition, the semiconductor substrate 100 may define a transistor predetermined region TA, a photodiode predetermined region, and a floating diffusion predetermined region in the semiconductor substrate 100 by the device isolation layer 110. Although not shown in FIG. 4, one side of the transistor predetermined region TA may be a photodiode predetermined region, and the other side may be a floating diffusion predetermined region.

In addition, a channel region 120 is formed on the surface of the semiconductor substrate 100 to adjust the threshold voltage and move charges. The channel region 120 may be formed by performing an ion implantation process in a shallow region of the semiconductor substrate 100 corresponding to an active region. The channel region 120 may be formed of p-type impurity p0.

The channel region 120 may be selectively formed only on the semiconductor substrate 100 corresponding to the transistor predetermined area TA.

Referring to FIG. 5, a gate insulating layer 130 and a gate 140 are formed on the semiconductor substrate 100 corresponding to the transistor predetermined area TA. The gate insulating layer 130 and the gate 140 may be formed by depositing and patterning a gate oxide layer and a polysilicon layer on the semiconductor substrate 100.

The gate insulating layer 130 and the gate 140 may be formed on the semiconductor substrate 100 corresponding to the transistor predetermined area TA to define the channel region 120. Accordingly, the channel region 120 may operate by the turn-on Vth of the gate 140.

Referring to FIG. 6, a first photoresist pattern 210 is formed on the semiconductor substrate 100 to selectively expose the gate 140. The first photoresist pattern 210 may selectively expose an upper surface of the gate 140 corresponding to one side thereof with respect to the center of the channel region 120.

Next, a first doped layer 151 is formed in a shallow region of the gate 140 corresponding to one side with respect to the center of the channel region 120. The first doped layer 151 may be formed by performing a first ion implantation process using the first photoresist pattern 210 as an ion implantation mask.

The first doped layer 151 may be formed to have a first depth T1 by implanting ions into a shallow region of the gate 140. For example, the first doped layer 151 may be formed by ion implantation into the gate 140 using ion implantation energy of 5-15 keV using n-type impurities as a dopant. Therefore, the first doped layer 151 may be selectively formed only on one side of the gate 140.

Next, a second doped layer 152 is formed in a deep region of the gate 140 to contact the first doped layer 151. The second doped layer 152 may be formed by performing a second ion implantation process using the first photoresist pattern 210 as an ion implantation mask.

The second doped layer 152 may be formed to have a second depth T2 by ion implantation into a deep region of the gate 140 corresponding to a lower portion of the first doped layer 151. For example, the second doped layer 152 may be formed by ion implantation into the gate 140 using an ion implantation energy of 20 to 100 keV using n-type impurities as a dopant. Therefore, the second doped layer 152 may be selectively formed only under the first doped layer 151 corresponding to one side of the gate 140.

Accordingly, the inside of the gate 140 corresponding to one side of the channel region 120 may be formed to have a uniform impurity concentration and distribution by the first and second doping layers 151 and 152. Can be.

Thereafter, the first photoresist pattern 210 may be removed.

Referring to FIG. 7, a second photoresist pattern 220 is formed on the semiconductor substrate 100 to selectively expose the gate 140. The second photoresist pattern 220 may selectively expose an upper surface of the gate 140 corresponding to the other side of the second photoresist pattern 220 with respect to the center of the channel region 120.

Next, a third doped layer 153 is formed in a shallow region of the gate 140 corresponding to the other side with respect to the center of the channel region 120. The third doped layer 153 may be formed by performing a third ion implantation process using the second photoresist pattern 220 as an ion implantation mask.

The third doped layer 153 may be implanted into a shallow region of the gate 140 to have the same first depth T1 as the first doped layer 151. For example, the third doped layer 153 may be formed by ion implantation into the gate 140 using ion implantation energy of 5-15 keV using n-type impurities as a dopant. Therefore, the third doped layer 153 may be selectively formed only on the other side of the gate 140.

Therefore, since the third doped layer 153 is formed only in the shallow region of the gate 140 corresponding to the other side of the channel region 120, the third doped layer 153 and the channel Regions 120 may be spaced apart to have a first width D1.

Thereafter, the second photoresist pattern 220 may be removed. In addition, a thermal diffusion process may be performed on the first, second and third doped layers 151, 152 and 153.

As described above, a first doped layer 151, a second doped layer 152, and a third doped layer 153 are formed in the gate 140 to operate the channel region 120. The turn-on Vth of can be optimized. Since a potential barrier is formed under the gate 140, the height of the barrier can be adjusted by a turn-on voltage applied to the gate 140. That is, the voltage drop occurs in the gate 140 region corresponding to the third doped layer 153 more than the gate 140 region in which the first and second doped layers 151 and 152 are formed. In order to operate the channel region 120 corresponding to 153, since a high voltage is applied, a potential barrier may be moved to the center of the channel region 120.

Referring to FIG. 8, a photodiode 160 is formed inside the semiconductor substrate 100 to be aligned with one side of the gate 140. The photodiode 160 may be formed on the semiconductor substrate 100 to be adjacent to the first and second doped layers 151 and 152 of the gate 140.

For example, the photodiode 160 may form a mask pattern (not shown) that exposes the semiconductor substrate 100 corresponding to one side of the gate 140, and then may be formed in a deep region of the semiconductor substrate 100. It may be formed by ion implantation of one impurity (n−) and ion implantation of a second impurity p0 in a shallow region of the semiconductor substrate 100. Thus, the photodiode may have a PNP junction.

Since a potential barrier of the channel region 120 is formed at the center of the channel region 120, the capacities of the photodiode 160 are increased by increasing the dose during ion implantation for forming the photodiode 160. It is possible to increase the capacity.

Next, the floating diffusion 170 is formed in the semiconductor substrate 100 to be aligned with the other side of the gate 140. The floating diffusion 170 may be formed to be adjacent to the third doped layer 153 of the gate 140.

For example, the floating diffusion unit 170 may form a mask pattern (not shown) exposing the semiconductor substrate 100 corresponding to the other side of the gate 140, and then, the floating diffusion unit 170 may have a high concentration on the semiconductor substrate 100. It may be formed by ion implantation of one impurity (n +). For reference, the floating diffusion unit 170 forms an LDD region in the semiconductor substrate 100 corresponding to the other side of the gate 140, and forms a spacer on the other side wall of the gate 140, and then first impurity. May be formed by ion implantation.

As described above, the embodiment has differently formed doping distributions in the gate 140 of the transfer transistor in order to improve the photocharge transfer characteristics of the transfer transistor.

In detail, the first doped layer 151 and the second doped layer 152 are formed in the entire length direction of the gate 140 corresponding to one side of the channel region 120 based on the center of the channel region 120. 120). In addition, a third doped layer 153 having the same depth as the first doped layer 151 is formed in the remaining area of the gate 140 to be spaced apart from the channel region 120 by the first width D1. It was formed to have a distance.

The region adjacent to the photodiode 160 has a structure in which the first and second doping layers 151 and 152 are stacked so as to be turned on by a voltage (Low Vth), and the region spaced apart from the photodiode 160 is Only the third doped layer 153 is formed to be turned on by the high voltage (High Vth). Since the doping concentration becomes uniform in the gate 140 in which the first and second doping layers 151 and 152 are formed, the depletion area is reduced, thereby reducing the voltage drop. On the other hand, a relatively large voltage drop may occur in the gate 140 in which the third doped layer 153 is formed. Accordingly, the first and second doped layers 151 and 152 of the gate 140 adjacent to the photodiode 160 are turned on so that the photocharge signal is moved to the center of the channel region 120. When the high voltage (High Vth) is applied to turn on the third doped layer 153 of the gate 140, the channel region 120 may be completely connected. At this time, the current amount increases as the voltage of the gate 140 increases, so that the gate applied voltage condition having the best optical characteristic of the image sensor can be found.

Accordingly, the voltage applied to the gate 140 may be a high voltage for operating the channel region 120 corresponding to the third doped layer 153.

In general, the barrier at the channel inlet of a transfer transistor is a trade-off because it can easily be changed depending on the amount of dose implanted to form a photodiode capacitor. Although it is difficult to simultaneously reduce the image lag and the dark signal, in the embodiment, the potential barrier is moved to the center of the channel region 120 spaced apart from the photodiode 160 so that the gate ( 140) The optimization of the voltage can improve the photocharge transfer characteristics.

In addition, the potential barrier may move to the center of the channel region 120 to increase the doping concentration of the photodiode 160 to improve the capacity.

The above-described embodiments are not limited to the above-described embodiments and drawings, and various substitutions, modifications, and changes can be made without departing from the spirit and scope of the present invention. It will be clear to those who have it.

1 is a circuit diagram illustrating a unit pixel of a general image sensor.

FIG. 2 is a diagram illustrating a layout of FIG. 1.

3 is a cross-sectional view taken along the line AA ′ of FIG. 2.

4 to 8 are views illustrating a process of manufacturing a unit pixel of an image sensor according to an embodiment.

Claims (11)

A semiconductor substrate in which transistor predetermined regions are defined; A channel region formed in the semiconductor substrate corresponding to the transistor predetermined region; A gate insulating film formed on the channel region; A gate formed on the gate insulating film; A doped region formed inside the gate and having an impurity distribution different from one side and the other region with respect to the center of the channel region; A photodiode formed inside the semiconductor substrate to be aligned with one side of the gate; And A floating diffusion formed in the semiconductor substrate to be aligned with the other side of the gate, Wherein the doped region adjacent to the photodiode is formed with a uniform distribution of impurities entirely, and the doped region adjacent to the floating diffusion is formed only in a shallow region of the gate. The method of claim 1, Wherein the doped region is formed of n-type impurities. The method of claim 1, The doped region is, A first doping layer formed to have a first depth inside the gate corresponding to one side of the center of the channel region; A second doped layer formed under the first doped layer to be adjacent to the first doped layer and formed to have a second depth deeper than the first depth; And And a third doping layer formed to have a first depth inside the gate corresponding to the other side with respect to the center of the channel region. The method of claim 1, And a turn-on voltage of the gate is applied based on the channel region corresponding to the doped region adjacent to the floating diffusion. The method of claim 1, And a potential barrier of the doped region adjacent to the photodiode is lower than a potential barrier adjacent to the floating diffusion. Preparing a semiconductor substrate in which a transistor predetermined region is defined; Forming a channel region on the semiconductor substrate corresponding to the transistor predetermined region; Forming a gate insulating film and a gate on the channel region; Forming a first doped layer to have a first depth inside the gate corresponding to one side with respect to the center of the channel region; Forming a second doped layer in the gate to have a second depth deeper than a first depth in contact with the first doped layer; Forming a third doped layer to have a first depth inside the gate corresponding to the other side with respect to the center of the channel region; Forming a photodiode in the semiconductor substrate to be aligned with one side of the gate; And And forming a floating diffusion in the semiconductor substrate so as to be aligned with the other side of the gate. The method of claim 6, Wherein the first doped layer, the second doped layer, and the third doped layer are made of n-type impurities. The method of claim 6, Forming the first doped layer and the second doped layer, Forming a first photoresist pattern such that the gate corresponding to one side thereof is selectively exposed based on the center of the channel region; Performing a first ion implantation process using the first photoresist pattern as an ion implantation mask to form a first doped layer having a first depth in a shallow region of the gate; And And forming a second doped layer having a second depth in a deep region of the gate by performing a second ion implantation process using the first photoresist pattern as an ion implantation mask. The method of claim 6, Forming the third doped layer, Forming a second photoresist pattern to selectively expose the gate corresponding to the other side with respect to the center of the channel region; And a third ion implantation process using the second photoresist pattern as an ion implantation mask to form a third doped layer having a first depth in a shallow region of the gate. The method of claim 6, The gate is a unit pixel manufacturing method of the image sensor, characterized in that formed of polysilicon. The method of claim 6, And a turn-on voltage of the gate is applied based on the channel region corresponding to the third doped layer.

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