KR20100074718A - Semiconductor having buried wordline and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device including a buried word-line is provided to improve a process margin by preventing the buried word-line from being etched during a contact-hole formation process. CONSTITUTION: A word-line trench is etched to a pre-set depth in order to form an active region. A buried word-line(114) is buried in a part of the active region. A capping nitride layer(118) is formed on the upper side of the buried word-line. A source/drain region is formed on both sides of the buried word-line. The height of the source/drain region is higher than that of the buried word-line. The height of the capping nitride layer is higher than that of the source/drain region.

Description

Semiconductor device having buried word line and method for manufacturing thereof {Semiconductor having buried wordline and method for manufacturing the same}

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device having a buried word line and a method for manufacturing the same.

In order to reduce the area required for transistors according to the need for high integration of semiconductor devices, researches are being actively conducted.

To reduce the transistor size, the length and width of the channel region must be reduced. However, the reduction of the effective channel width causes a decrease in the channel current, and the decrease in the channel current lowers the current driving capability of the transistor.

In addition, the reduction of the effective channel length has an effect of increasing the channel current, but the reduction of the effective channel length causes a short channel effect. Recess channel MOSFETs have been proposed as a way to reduce transistors while overcoming these short channel effects.

However, since the recess channel MOSFET arranges the gate electrode to protrude above the semiconductor substrate, it has a problem of making subsequent processes such as contact plug formation and planarization process difficult. In addition, the upper edge portion of the channel region may provide a cause of leakage current caused by a field crowding effect. Moreover, forming the protruding gate electrode requires a high level patterning process.

In order to overcome these problems, researches on semiconductor devices having buried word lines have recently been conducted.

In the buried semiconductor device according to the related art, the word line of the cell transistor is buried and the gate layer of the peripheral circuit region transistor is formed in a planar structure. In this case, a metal layer other than polysilicon is used as a word line of the cell transistor formed as a buried type.

However, when the word line of the cell region is buried and the gate of the peripheral circuit region is formed in a planar structure, the word line of the cell region and the gate of the peripheral circuit region are sequentially formed in the gate of the peripheral circuit region. In the high temperature gate oxidation process, there is a problem that a complicated process is performed to prevent the word line of the cell region formed of the metal layer from being oxidized.

The present invention seeks to improve process margins by simplifying the manufacturing process by improving the manufacturing process of semiconductor devices having buried word lines.

The semiconductor device of the present invention includes a buried word line embedded in a portion of a word line trench in which an active region is etched to a predetermined depth, a capping nitride layer formed on the buried word line, and a source / drain formed in the active regions on both sides of the buried word line. It includes an area.

In the semiconductor device of the present invention, an upper surface of the source / drain region is formed higher than the buried word line, and an upper surface of the capping nitride layer is formed higher than the source / drain region. The word line trench is etched to the predetermined depth in the active region and the isolation layer in a direction crossing the long axis direction of the active region.

In the method of manufacturing a semiconductor device of the present invention, forming a gate oxide layer on the etched layer of the cell region and the peripheral circuit region, forming a word line trench by etching the gate oxide layer and the etched layer of the cell region to a predetermined depth; Embedding a conductive material in a portion of the word line trench to form a buried word line, forming a gate conductive layer and a hard mask layer on the gate oxide layer in the peripheral circuit region, and the gate oxide layer and the gate conductive layer And patterning the hard mask layer to form a gate.

A method of manufacturing a semiconductor device according to an embodiment of the present invention may include forming a first gate conductive layer on the gate oxide layer, removing a first gate conductive layer of the cell region from among the first gate conductive layer, the cell region and the peripheral circuit region. Forming a hard mask layer on the substrate, and planarizing the hard mask layer; and forming a hard mask layer pattern defining the word line trench by etching the hard mask layer.

In the semiconductor device manufacturing method of the present invention, the gate conductive layer is formed by depositing a second gate conductive layer on the first gate conductive layer.

The forming of the buried word line may include forming a word line oxide layer on an inner wall of the word line trench, forming a conductive layer on the word line oxide layer to fill the word line trench, and forming the word line oxide layer and the word line oxide layer. Etching the conductive layer to a predetermined depth.

The method of manufacturing a semiconductor device of the present invention further includes forming a capping nitride film over the buried word line in the word line trench, wherein the capping nitride film has a top surface higher than that of the etched layer.

In the semiconductor device manufacturing method of the present invention, the buried word line is formed below the word line trench lower than the upper surface of the etched layer.

In the present invention, the gate oxide film for the gate of the peripheral circuit region is first formed before forming the buried word line in the cell region, thereby preventing the buried word line from being oxidized during the gate oxide film forming process of the peripheral circuit region.

In addition, the present invention improves process margin by preventing the contact hole from being etched to the buried word line even when a misalignment occurs when forming the contact hole for forming the contact plug in the cell region by forming a nitride film on the buried word line.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view illustrating a structure of a semiconductor device according to the present invention. In the following description of the invention, like reference numerals refer to like elements.

An isolation layer 104 defining an active region 102 is formed on the silicon substrate 100 having a cell region and a peripheral circuit region, and the active region 102 in a direction crossing the long axis direction of the active region 102. And a buried word line 114 that crosses the device isolation layer 104. Source / drain regions (not shown) are formed in the active regions 102 at both sides of the buried word line 114. In this case, an upper surface of the source / drain region is formed at a level higher than the buried word line 114.

A word line oxide layer 112 is formed on the bottom surface of the buried word line 114, and an optional oxide layer 116 and a capping nitride layer 118 are formed on the buried word line 114. In this case, the upper surface of the capping nitride layer 118 is formed at an upper level than the source / drain region (not shown).

As such, in the present invention, when the contact hole for forming the contact plug 130 is formed by forming the nitride film 118 having a low etching selectivity on the buried word line 114, the contact hole is etched up to the buried word line 114. Prevent it.

In the peripheral circuit region, a gate 124 having a planar structure in which the gate oxide layer 106, the gate conductive layers 108 and 120, and the hard mask layer 122 are stacked is formed on the active region 102, and the gate 124 is formed. Spacers 126 are formed on the sidewalls of the substrate.

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2, after a pad oxide layer (not shown) and a pad nitride layer (not shown) are sequentially formed on a silicon substrate 100 having a cell region and a peripheral circuit region, etching is performed using a shallow trench isolation (STI) mask. A device isolation trench (not shown) for forming the device isolation layer 104 defining the active region 102 is formed in the substrate 100 through the process. At this time, the etching process is performed by a dry etching process.

Next, a field oxide film is formed so that the inside of the device isolation trench is completely filled to form the device isolation film 104. In this case, a SOD (Spin On Dielectric) oxide film or an HDP (High Density Plasma) oxide film may be used as the field oxide film.

Next, a gate oxide film 106 and a first gate conductive film 108 are formed over the active region 102 and the device isolation film 104. The gate oxide film 106 and the first gate conductive film 108 are for forming a gate of a transistor to be formed in the peripheral circuit region, and the first gate conductive film 108 is made of polysilicon, tungsten, or a combination thereof. Can be. As such, in the present invention, the buried word line 114 is oxidized by the gate oxide film 106 forming process by first forming the gate oxide film 106 of the gate to be formed in the peripheral circuit region before forming the buried word line. It can be prevented.

Referring to FIG. 3, after forming a photoresist pattern defining a peripheral circuit region on the first gate conductive layer 108, only the first gate conductive layer 108 formed in the cell region is removed using the photoresist pattern.

Next, the hard mask layer 110 is formed on the first gate oxide layer 106 of the cell region and the first gate conductive layer 108 of the peripheral circuit region, and then planarized by performing a CMP process. Accordingly, the hard mask layer of the cell region is formed to be relatively thicker than the hard mask layer of the peripheral circuit region.

The reason why the hard mask layer of the cell region is formed relatively thicker than the hard mask layer of the peripheral circuit region is that the hard mask layer of the cell region is used as an etching mask of a word line trench for forming a buried word line.

Referring to FIG. 4, after forming a photoresist pattern (not shown) defining a buried word line region on the hard mask layer 110, the hard mask layer 110 is etched using an etching mask, thereby hard mask layer 110. Form a pattern. Subsequently, the cell region is etched with a predetermined depth using the hard mask layer 110 pattern to form a word line trench (not shown). That is, the word line trench is formed by etching the active region 102 and the device isolation layer 104 to a predetermined depth in a direction crossing the long axis direction of the active region 102 in the cell region.

Next, the word line oxide layer 112 and the buried word line conductive layer (not shown) are sequentially formed on the entire surface of the substrate including the inner side of the word line trench, and then, until the hard mask layer 110 is exposed. Etch and flatten. In this case, the conductive material for the buried word line may be a polysilicon film, a metal silicide film, a metal (alunium, copper, etc.) film, or a combination thereof.

Next, the word line oxide layer 112 and the buried word line conductive layer are etched to a predetermined depth by using a dry etching etchback method, so that the buried word line conductive layer remains only a predetermined height under the word line trench. Line 114 is formed. At this time, the upper surface of the buried word line 114 is formed lower than the upper surface of the silicon substrate of the active region 102.

Next, an oxide film 116 is formed on the entire surface of the resultant film including the top surface of the buried word line 114.

Referring to FIG. 5, after the capping nitride layer 118 is formed on the oxide layer 116 to fill the word line trench, the capping nitride layer 118 is exposed until the first gate conductive layer 108 of the peripheral circuit region is exposed. The oxide film 116 and the hard mask layer 110 are etched and planarized. In this case, the upper surface of the capping nitride layer 118 is formed at an upper level than the active region 102 at both sides of the buried word line 114, that is, the region where the source / drain is formed in a subsequent process.

As such, the reason why the nitride film 118 is formed on the buried word line 114 in the present invention is that even if a misalignment occurs when forming a contact hole in a subsequent process of forming a contact plug, the contact hole is buried in the buried word line. This is to prevent the formation up to 114.

Referring to FIG. 6, the second gate conductive layer 120 and the gate hard mask layer 122 are sequentially formed on the resultant of FIG. 5. In this case, the second gate conductive layer 120 may be formed of the same material as the first gate conductive layer 108. That is, the gate conductive film in the peripheral circuit region is formed in a stacked structure in which the second gate conductive film 120 is deposited on the first gate conductive film 108.

Referring to FIG. 7, after forming a photoresist film (not shown) on the gate hard mask layer 122, a photoresist pattern (not shown) is formed using a mask defining a gate of a peripheral circuit region.

Next, the gate hard mask layer 122, the second gate conductive film 120, the first gate conductive film 108, and the gate oxide film 106 are etched by using the photoresist pattern as an etch mask. Pattern 124).

Referring to FIG. 8, a gate spacer layer (not shown) is formed on the resultant of FIG. 7 and then etched to form a spacer 126 on the sidewall of the gate 124.

Next, the interlayer insulating film 128 is formed on the entire resultant and then etched to planarize it. Subsequently, a photoresist pattern (not shown) defining a bit line contact and a storage node contact is formed on the interlayer insulating layer 128, and then, as an etching mask, the interlayer insulating layer 128 is exposed until the silicon substrate 102 of the active region 102 is exposed. The insulating layer 128, the hard mask layer 110, and the gate oxide layer 106 are selectively etched to form a contact hole (not shown).

Next, a high concentration of impurity ions are implanted into the active region 102 exposed by the contact hole to form a source / drain region (not shown). In this case, an upper surface of the source / drain region is formed at an upper level than the buried word line 114.

Next, the conductive film is formed to fill the contact hole (not shown), and then the planarization etching is performed to form the contact plug 130. As the conductive film for contact plugs, a polysilicon film or a metal film may be used.

Thereafter, a bit line (not shown) and a storage node (not shown) connected to the contact plug 130 are formed in a subsequent process, and the same method as the conventional bit line forming process and the storage node forming process may be used. .

FIG. 9 is a diagram illustrating a case in which a misalignment occurs when the contact plug 130 is formed, as shown in FIG. 8.

In the present invention, since the nitride film 118 having a low etching selectivity is formed on the buried word line 114, even if a misalignment occurs when forming a contact hole for forming the contact plug 130, the contact hole may be buried in the buried word line 114. Improves process margins by preventing etch down to

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a process cross-sectional view showing the configuration of a semiconductor device according to the present invention.

2 to 8 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (11)

A buried word line buried in a portion of the word line trench in which the active region is etched to a predetermined depth; A capping nitride layer formed on the buried word line; And And a source / drain region formed in the active region on both sides of the buried word line. The method of claim 1, wherein the top surface of the source / drain region is And formed higher than the buried word line. The upper surface of the capping nitride film of claim 1, wherein And formed higher than the source / drain regions. The word line trench of claim 1, wherein the word line trench is formed. And the active region and the device isolation layer are etched to the predetermined depth in a direction crossing the long axis direction of the active region. Forming a gate oxide layer over the etched layer in the cell region and the peripheral circuit region; Etching the gate oxide layer and the etched layer in the cell region to a predetermined depth to form a word line trench; Embedding a conductive material in a portion of the word line trench to form a buried word line; Forming a gate conductive layer and a hard mask layer on the gate oxide layer in the peripheral circuit region; And And forming a gate by patterning the gate oxide layer, the gate conductive layer, and the hard mask layer. The method of claim 5, Forming a first gate conductive layer on the gate oxide layer; Removing the first gate conductive film of the cell region from the first gate conductive film; Forming a hard mask layer on the cell region and the peripheral circuit region and then planarizing the hard mask layer; And And etching the hard mask layer to form a hard mask layer pattern defining the word line trenches. The method of claim 6, wherein the gate conductive film And forming a second gate conductive film on the first gate conductive film. The method of claim 5, wherein the forming of the buried word line Forming a word line oxide layer on the inner wall of the word line trench; Forming a conductive layer on the word line oxide layer to fill the word line trenches; And And etching the word line oxide layer and the conductive layer to a predetermined depth. The method of claim 5, And forming a capping nitride film over the buried word line in the word line trench. The method of claim 9, The capping nitride film is a semiconductor device manufacturing method, characterized in that the upper surface is formed higher than the etched layer. The method of claim 5, The buried word line is formed on the lower portion of the word line wrench lower than the upper surface of the etched layer.

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