KR20100073903A - Reference voltage trimming circuit - Google Patents

Reference voltage trimming circuit Download PDF

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Publication number
KR20100073903A
KR20100073903A KR1020080132693A KR20080132693A KR20100073903A KR 20100073903 A KR20100073903 A KR 20100073903A KR 1020080132693 A KR1020080132693 A KR 1020080132693A KR 20080132693 A KR20080132693 A KR 20080132693A KR 20100073903 A KR20100073903 A KR 20100073903A
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KR
South Korea
Prior art keywords
signal
voltage
fuse
node
enable signal
Prior art date
Application number
KR1020080132693A
Other languages
Korean (ko)
Inventor
안선모
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080132693A priority Critical patent/KR20100073903A/en
Publication of KR20100073903A publication Critical patent/KR20100073903A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/027—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in fuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory

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  • Semiconductor Integrated Circuits (AREA)

Abstract

The present invention provides an enable signal generation unit for generating second and third enable signals from a first enable signal applied to perform BIST trimming; And an antifuse, and a fuse signal generation unit configured to receive the second enable signal and a temperature code and determine whether the antifuse is cut to generate a fuse signal.

Description

Reference voltage trimming circuit {REFERENCE VOLTAGE TRIMMING CIRCUIT}

The present invention relates to a semiconductor memory device, and more particularly, to a reference voltage trimming circuit which can reduce a test time for trimming a reference voltage.

The amount of leakage current generated in the DRAM has an increasing characteristic at a high temperature and a decreasing characteristic at a low temperature. Due to such leakage current, the data retention time of the DRAM memory cell is short at high temperature and long at low temperature. Therefore, the DRAM uses a TCSR circuit to form a short refresh cycle at high temperatures and a long refresh cycle at low temperatures.

Among the various TCSR circuits, the DTCSR circuit, which is applied to 66nm 1G mobile DRAM, controls the refresh cycle according to the temperature code detected by the temperature sensor. More specifically, the DTCSR circuit generates and generates a reference voltage generated from a bandgap reference circuit into a low temperature reference voltage and a high temperature reference voltage, and senses an external temperature according to a bipolar BJT voltage inversely proportional to temperature. This circuit converts it into digital code. At this time, since the low temperature reference voltage and the high temperature reference voltage may be different for each DRAM, trimming of the reference voltage may improve mass productivity. Accordingly, most DRAMs include a reference voltage trimming circuit for trimming BIST (Built In Self TEST) so that a low temperature reference voltage and a high temperature reference voltage have a predetermined level.

However, in the conventional reference voltage trimming circuit, only the BIST trimming test is performed in the wafer test step, and only the reference voltage of a high temperature is tested to reduce the test time. In addition, according to the test result after the test, the tester (tester) needs to additionally perform the work of cutting the fuse included in the reference voltage trimming circuit.

The present invention discloses a reference voltage trimming circuit that can reduce the test time for BIST trimming of a reference voltage by using an anti-fuse in which cutting is automatically determined according to an internal temperature.

The present invention discloses a reference voltage trimming circuit capable of trimming BIST (Built In Self TEST) for a low temperature reference voltage and a high temperature reference voltage in a package test as well as a wafer test.

To this end, the present invention includes an enable signal generator for generating second and third enable signals from the first enable signal applied to perform BIST trimming; And an antifuse, and a fuse signal generation unit configured to receive the second enable signal and a temperature code and determine whether the antifuse is cut to generate a fuse signal.

The enable signal generator may include a first buffer configured to generate the second enable signal by buffering the first enable signal; And a second buffer configured to buffer the second enable signal to generate the third enable signal.

The method may further include a voltage pumping unit configured to pump a back bias voltage to a predetermined level in response to the third enable signal, and supply the pumped back bias voltage to the fuse signal generation unit.

In an embodiment of the present invention, the fuse signal generation unit may include an initialization unit configured to initialize a first node in response to a power-up signal; A signal input unit configured to receive the temperature code and the second enable signal and drive the first node; An antifuse connected between the first node and a back bias voltage supplied from the voltage pump; And a level shifter for level shifting and outputting the signal of the first node.

In the present invention, the initialization unit includes a buffer for buffering the power-up signal; And a pull-up device configured to pull-up the first node in response to an output signal of the buffer.

In the present invention, the signal input unit is a logic element for receiving the temperature code and the second enable signal to perform a logic operation; And a driving unit driving the first node in response to an output signal of the logic element.

In the present invention, the driving unit pull-up element for driving the first node in response to the output signal of the logic element; And a pull down device configured to pull down the first node in response to an output signal of the logic device.

In the present invention, the anti-fuse is short-circuited when the voltage difference between the first node and the back bias voltage is more than a predetermined level.

The present invention includes a multiplexer for transmitting the fuse signal or the temperature code to a control voltage in response to a test signal; And a decoder for generating a trimming voltage by decoding the control voltage.

In an embodiment, the multiplexer may include: a first transfer device configured to transfer the fuse signal to a control voltage in response to the test signal; And a second transfer element transferring the temperature code as a control voltage in response to the test signal.

Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

1 is a block diagram showing a configuration of a reference voltage trimming circuit according to an embodiment of the present invention.

As shown, the reference voltage trimming circuit according to the present embodiment includes an enable signal generation unit 1, a voltage pumping unit 2, a fuse signal generation unit 3, a multiplexer 4, and a decoder 5. do.

As shown in FIG. 2, the enable signal generation unit 1 includes an inverter IV10 that inverts and buffers the first enable signal BISTENB to generate a second enable signal ANTIEN, and a second enable signal generator. Inverter IV11 generates the third enable signal VBBENB by inverting and buffering the enable signal ANTIEN. Here, the first enable signal BISTENB is a signal enabled at a low level in order to perform BIST trimming. Therefore, when the BIST trimming is performed, the enable signal generation unit 1 generates a high enable level second enable signal ANTIEN and a low enable level third enable signal VBBENB.

The voltage pumping unit 2 is implemented with a general voltage pumping circuit, and when the low level third enable signal VBBENB is input, the voltage pumping unit 2 pumps the back bias voltage VBBA to -3.5 (V). Here, the level of the back bias voltage VBBA pumped by the voltage pumping unit 2 when the low level third enable signal VBBENB is input may be variously set according to embodiments.

As shown in FIG. 3, the fuse signal generation unit 3 includes a signal input unit 30, an initialization unit 31, an antifuse ANT, and a level shifter 32. The fuse signal generation unit 3 is preferably implemented as a separate circuit for each of the temperature codes T <1: N> and the fuse signals FUSE <1: N>. However, since the fuse signal generation unit 3 has the same circuit configuration as each circuit, As shown in FIG. 3, it is represented by one circuit.

The signal input unit 30 receives the temperature code T <1: N> and the second enable signal ANTIEN and performs an NOR gate operation ND30 and an output signal of the NAND gate ND30. In response to the output signals of the PMOS transistor P30 and the NAND gate ND30, which operate as pull-up devices that pull up the node nd10 to the high voltage VPP level 3.5 (V), the node nd10 The driver 300 includes an NMOS transistor N30 that operates as a pull-down device for driving pull-down. Here, the temperature code T <1: N> is a digital signal including information about the external temperature sensed by the temperature sensor, and is an output signal of an analog / digital converter (not shown). This signal is input to generate the trimming voltage.

The initialization part 31 is comprised with the PMOS transistor P31 which acts as a pullup element which pulls-up the node nd10 in response to the output signal of the inverter IV30.

The antifuse ANT is connected between the node nd10 and the back bias voltage VBBA, and shorted when the voltage difference between the voltage of the node nd10 and the back bias voltage VBBA is 7 (V) or more. The antifuse ANT is a structure in which an ONO structure is formed between a signal of the node nd10 and a poly layer to which the back bias voltage VBBA is applied. When the voltage difference between both ends is greater than 7 V, the ONO structure is destroyed. There is no voltage difference across the poly layer.

The level shifter 32 receives the signal of the node nd10 and level shifts the signal to generate a fuse signal FUSE <1: N> that swings between the power supply voltage VDD and the ground voltage VSS.

As shown in FIG. 4, the multiplexer 4 transmits a fuse signal FUSE <1: N> to a control voltage CV <1: N> in response to a test signal TM. T40 and a second transfer element T41 which transfers the temperature code T <1: N> to the control voltage CV <1: N> in response to the test signal TM. Here, the test signal TM is a signal that is enabled at a high level to perform a test mode for generating the trimming voltage VTRIM <1: M> from the temperature codes T <1: N>.

The decoder 5 decodes the control voltages CV <1: N> to generate trimming voltages VTRIM <1: M> for trimming the low temperature reference voltage or the high temperature reference voltage. The trimming voltage VTRIM <1: M> is input to a temperature sensor (not shown) formed of a bandgap reference circuit to adjust the level of the low temperature reference voltage or the high temperature reference voltage.

The BIST trimming test operation performed using the reference voltage trimming circuit configured as described above will be described below.

First, when a test for BIST trimming is started, the first enable signal BISTENB is applied at a low level, and the test signal TM is applied at a high level. By the high level test signal TM, the multiplexer 4 transmits the temperature code T <1: N> to the control voltage CV <1: N>, and the decoder 5 transmits the control voltage CV < 1: N>) to generate a trimming voltage VTRIM <1: M> for trimming the low temperature reference voltage or the high temperature reference voltage. The enable signal generator 1 receiving the low level first enable signal BISTENB generates the high level second enable signal ANTINN and the low level third enable signal VBBENB. The fuse signal generator 3 receiving the second enable signal ANTIEN of the high level determines whether to cut the anti-fuse ANT according to the temperature code T <1: N>. Looking at the operation of the fuse signal generation unit 3 in more detail as follows.

When the temperature code T <1: N> is input at a high level, the node nd10 is pulled up to a high voltage VPP level, that is, 3,5 (V). The voltage pumping unit 2 receives the low enable third enable signal VBBENB and pumps the back bias voltage VBBA to -3.5 (V), and thus, between the node nd10 and the back bias voltage VBBA. The potential difference is 7 (V). Thus, the antifuse ANT is cut.

On the other hand, when the temperature code T <1: N> is input at the low level, the node nd10 is pulled down to the ground voltage VSS level, and thus the anti-fuse ANT is not cut.

In summary, the reference voltage trimming circuit of the present embodiment determines whether to cut the anti-fuse ANT according to the temperature code T <1: N> in a test for BIST trimming. In the conventional reference voltage trimming circuit, the test result according to the temperature code T <1: N> was examined, and the tester had to cut the fuse. However, in the reference voltage trimming circuit according to the present embodiment, the temperature code T <1: ANT is cut automatically according to: N>). As such, when the reference voltage trimming circuit according to the present exemplary embodiment is used, an additional fuse cutting operation may be omitted, thereby reducing test time.

The reference voltage trimming circuit having the above-described test generates the trimming voltage VTRIM <1: M> according to the cutting state of the anti-fuse ANT. That is, since the test signal TM transitions to the low level when the test is finished, the multiplexer 4 controls the generated fuse signal FUSE <1: N> according to the cutting state of the anti-fuse ANT. CV <1: N>, and the decoder 5 decodes the control voltage CV <1: N> to trim the low temperature reference voltage or the high temperature reference voltage (VTRIM <1: M). Create>).

1 is a block diagram showing a configuration of a reference voltage trimming circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an enable signal generator included in the reference voltage trimming circuit shown in FIG. 1.

FIG. 3 is a circuit diagram of a fuse signal generation unit included in the reference voltage trimming circuit shown in FIG. 1.

FIG. 4 is a circuit diagram of a multiplexer included in the reference voltage trimming circuit shown in FIG. 1.

<Description of the symbols for the main parts of the drawings>

1: Enable signal generation unit 2: Voltage pumping unit

3: fuse signal generator 4: multiplexer

5: decoder

Claims (10)

An enable signal generator configured to generate second and third enable signals from the first enable signal applied to perform BIST trimming; And And a fuse signal generation unit configured to receive an anti-fuse and determine whether the anti-fuse is cut by receiving the second enable signal and a temperature code to generate a fuse signal. The method of claim 1, wherein the enable signal generator A first buffer configured to generate the second enable signal by buffering the first enable signal; And And a second buffer configured to buffer the second enable signal to generate the third enable signal. The reference voltage trimming circuit of claim 1, further comprising a voltage pumping unit configured to pump a back bias voltage to a predetermined level in response to the third enable signal, and supply the back bias voltage to the fuse signal generation unit. The method of claim 3, wherein the fuse signal generation unit An initialization unit for initializing the first node in response to the power-up signal; A signal input unit configured to receive the temperature code and the second enable signal and drive the first node; An antifuse connected between the first node and a back bias voltage supplied from the voltage pump; And And a level shifter for level shifting and outputting the signal of the first node. The method of claim 4, wherein the initialization unit A buffer for buffering the power up signal; And And a pull-up device configured to pull-up the first node in response to an output signal of the buffer. The method of claim 4, wherein the signal input unit A logic element configured to receive the temperature code and the second enable signal and perform a logic operation; And And a driving unit driving the first node in response to an output signal of the logic element. The method of claim 6, wherein the driving unit A pull-up device configured to pull-up the first node in response to an output signal of the logic device; And And a pull down device configured to pull down the first node in response to an output signal of the logic device. The reference voltage trimming circuit of claim 4, wherein the antifuse is shorted when the voltage difference between the first node and the back bias voltage is greater than or equal to a predetermined level. The method of claim 1, A multiplexer transferring the fuse signal or the temperature code to a control voltage in response to a test signal; And And a decoder configured to decode the control voltage to generate a trimming voltage. The method of claim 9, wherein the multiplexer A first transfer element transferring the fuse signal to a control voltage in response to the test signal; And And a second transfer device configured to transfer the temperature code to a control voltage in response to the test signal.
KR1020080132693A 2008-12-23 2008-12-23 Reference voltage trimming circuit KR20100073903A (en)

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