KR20100073513A - Method for controlling wireless electronic label, and wireless electronic label adopting the same - Google Patents

Abstract

PURPOSE: A method for controlling wireless electronic label, and a wireless electronic label adopting the same are provided to approve delayed reset signal of signal delay unit as power of plug generation unit, thereby preventing delay by inefficiently between some wireless electronic label and a reader. CONSTITUTION: A power supply unit(21) changes AC(Alternating Current) voltage of an antenna into set DC(Direct Current) voltage. While the direct current voltage rises over rated level, a reset signal generator(1111) generates a reset signal. A flag generation unit(1123) reproduces a flag signal of a digital control unit(1119). A signal delay unit(1113) delays the reset signal. The delayed reset signal is used as power supply voltage of the flag generation unit.

Description

Method for controlling wireless electronic label and wireless electronic label employing the same {Method for controlling wireless electronic label, and wireless electronic label adopting the same}

The present invention relates to a method for controlling a wireless electronic label, such as an RFID tag, and a wireless electronic label employing the same, and more particularly, to a method for controlling a wireless electronic label including an antenna and an integrated circuit device and employing the same. One wireless electronic label relates.

Wireless electronic labels, such as RFID tags, are currently used in a variety of ways.

In most cases, one reader receives tag information from multiple wireless electronic labels. Thus, the reader sends a flag signal of high logic or low logic to a plurality of radio electronic labels in order to set any radio electronic label of the communication object.

In this regard, the wireless electronic labels incorporate a tag generator. More specifically, in any wireless electronic label waiting to transmit its own tag information, the tag information reproduced after the flag information from the reader is reproduced in the tag generating unit is returned to the reader. Accordingly, the reader and the corresponding wireless electronic label can communicate.

On the other hand, in the above wireless electronic labels, AC power from the antenna of the reader is converted from the wireless electronic label to DC power and used. Thus, when the power supply is unstable, either wireless electronic label is switched off and then restored to on.

Here, a wireless electronic label is turned off due to a momentary instability of the supply power just before reproducing and returning a tag signal from the reader, and then restored to on again for a short time. Is generated. At this time of restoration, there is a problem that the flag signal of the high logic state that was stored immediately before switching to the off state is inverted due to the initialization operation inside the radio electronic label.

That is, if any wireless electronic label is switched off immediately before reproducing and returning a tag signal from the reader, and restored to the on state for a short time of several seconds, the wireless electronic label The label has a problem of waiting to receive a new flag signal from the reader.

Therefore, there is a problem that communication between any one of the wireless electronic labels and the reader is inefficiently delayed due to instantaneous instability of the power supply.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of controlling a wireless electronic label and a wireless electronic label employing the same, which can improve the problem that communication between any one of the wireless electronic labels and the reader is inefficiently delayed due to instantaneous instability of the power supply. It is.

The method of the present invention is a control method of a radio electronic label including an antenna, a digital control unit, a power supply unit, a reset signal generator, and a flag generator.

The method includes converting, by the power supply, an alternating voltage from the antenna into a set direct current voltage and providing it to the digital controller.

The reset signal generating unit generates a reset signal while providing the digital control unit while the DC voltage from the power supply unit rises above the rated level.

The flag generation section reproduces a flag signal from the digital control section and returns the flag signal to the digital control section.

Then, the reset signal from the reset signal generator is delayed, and the delayed reset signal is used as the power supply voltage of the flag generator.

The wireless electronic label of the present invention includes an antenna and an integrated circuit element. The integrated circuit device may include a digital controller, a power supply unit, a reset signal generator, a flag generator, and a signal delay unit.

The power supply unit converts an AC voltage from the antenna into a set DC voltage and provides the same to the digital controller.

The reset signal generator generates a reset signal while the DC voltage from the power supply rises above the rated level and provides the reset signal to the digital controller.

The flag generation unit reproduces a flag signal from the digital control unit and returns the flag signal to the digital control unit.

The signal delay unit delays the reset signal from the reset signal generator, and outputs the delayed reset signal as a power supply voltage of the flag generator.

According to the control method of the radio electronic label of the present invention and the radio electronic label employing the same, the delayed reset signal from the signal delay unit is applied as a power source of the flag generation unit. That is, the flag generator starts operation later than the digital controller.

Accordingly, the wireless electronic label according to the present invention is turned off due to the momentary instability of the supply power just before reproducing and returning the tag signal from the reader, and then back on again for a short time. When restored, the flag generator starts operation later than the digital controller.

Therefore, even if the digital control unit inputs a flag signal of an unknown logic state immediately after re-initializing the operation, the flag generation unit does not respond to it. The flag generator outputs a flag signal of a logic state which has been reproduced and stored immediately before the off state to the controller. That is, a flag signal of a logic state that has been reproduced and stored immediately before the off state can be conveyed to the reader through the digital controller. Accordingly, the reader may receive a flag signal of a logic state transmitted by the reader and communication may be resumed.

As a result, the problem that communication between any one of the wireless electronic labels and the reader is inefficiently delayed due to instantaneous instability of the power supply can be improved.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 1 shows the internal structure of an RFID tag 1 as a wireless electronic label in which the control method of one embodiment of the present invention is employed.

Referring to FIG. 1, in an RFID tag 1 as a wireless electronic label according to an embodiment of the present invention, an integrated circuit element 11 and an antenna 12 are formed on a substrate 14. Antenna 12 forms a single closed loop through integrated circuit element 11. That is, the conductor is connected to the connection region CN between the connection terminals 13a and 13b.

FIG. 2 shows an internal configuration of the integrated circuit device 11 of FIG. 1.

3 shows waveforms of respective parts generated in the circuit of FIG. 2. In FIG. 3, reference numeral V _DC2 denotes a DC voltage from the power supply 21 of FIG. 2, S _RS1 denotes a reset signal from the reset signal generator 1111 of FIG. 2, and S _RS2 denotes a signal delay of FIG. 2. The delayed reset signal of the rotor 1113 is an example of a flag signal to be transmitted from the digital controller 1119 of FIG. 2 to the flag generator 1123 of FIG. 2, and Sfd is a flag generator of FIG. 2. An example of a flag signal to be transmitted from 1123 to the digital controller 1119 of FIG. 2 is indicated. A time point t1 in FIG. 3 indicates a time point at which the state is turned off entirely due to a power problem of the RFID tag 1 as a wireless electronic label. At the time t2, since the power supply V _DC2 of the RFID tag 1 is restored, the reset signal S _RS1 from the signal generator 1111 is turned on, and thus digital It indicates the time point at which the control unit 1119 is turned on. A time point t2 indicates a time point at which the flag generator 1123 is turned on because the delayed reset signal of the signal delay unit 1113 turns on.

2 and 3, the integrated circuit device 11 of FIG. 1 includes a digital control unit 1119, a power supply unit 21, a clock pulse generator 1115, a reset signal generator 1111, and a signal delay unit ( 1113, a demodulator 1107, a modulator 1109, a memory 1121, a booster 1117, and a flag generator 1123.

The power supply unit 21 converts the AC voltage V _A from the antenna 12 into a set DC voltage V _DC2 and provides it to the digital controller 1119. The clock pulse generator 1115 is while the DC voltage V _DC2 from the power supply 21 rises above the first level lower than the rated level (for example, for a time after the time immediately before t2). Clock pulses S _CK to the digital controller 1119. The reset signal generator 1111 is a reset signal S _RS1 having a high logic state while the DC voltage from the power supply 21 rises above the rated level (for example, from a time point t2 to a subsequent time). Is generated and provided to the digital control unit 1119.

The set direct current voltage V _DC2 from the power supply unit 21 is also provided to the signal delay unit 1113.

The signal delay unit 1113 delays the reset signal S _RS1 from the reset signal generator 1111 for about 20 micro-seconds (t2 to t3) to delay the reset signal S _RS2 delayed. 1123 is provided as a power source. That is, the flag generator 1123 starts operation later than the digital controller 1119.

Therefore, the wireless electronic label according to the present invention is switched off (t1 time) due to instantaneous instability of the supply power just before reproducing and conveying the tag signal from the reader (t1 time point), and for a short time (t1 ~ When it is restored to the on state again at t2, the flag generator 1123 starts the operation later than the digital controller 1119.

Therefore, even if the digital control unit 1119 inputs an unknown logic signal to the flag generation unit 1123 immediately after re-initializing the operation, the flag generation unit 1123 does not respond to this. In addition, the flag generation unit 1123 outputs to the digital control unit 1119 a flag signal of a logic state which has been reproduced and stored immediately before the off state (time earlier than t1). That is, the flag signal of the logical state which was reproduced and stored immediately before the off state (time earlier than t1) can be conveyed to the reader via the digital control unit 1119. Accordingly, the reader may receive a flag signal of a logic state transmitted by the reader and communication may be resumed.

As a result, the problem that communication between any one of the wireless electronic labels and the reader is inefficiently delayed due to instantaneous instability of the power supply can be improved.

Meanwhile, the demodulator 1107 demodulates the input signal S _IN1 from the antenna 12 and provides the demodulated input signal S _IN2 to the digital controller 1119. In addition, the modulator 1109 modulates the output signal S _OUT1 from the digital controller 1119, and provides the modulated output signal S _OUT2 to the antenna 12.

Memory 1121 For example, identification information is stored in an EEPROM (Electrically Erasable & Programmable Read Only Memory) as a nonvolatile memory.

A set direct current voltage V _DC2 of about 1.7 volts V from the power supply 21 is provided to the memory 1121. However, in order to write data from the demodulator 1107 to the memory 1121, a higher voltage, for example, a voltage of 3.3 volts (V) is required. Accordingly, the boosting unit 1117, for example, a charge pump boosts the set DC voltage V _DC2 from the power supply unit 21 to store the write operation voltage V _DC3 of the memory 1121 in memory. Provided at 1121.

Meanwhile, the power supply unit 21 includes a rectifier 1101, a voltage limiter 1105, and a step-down unit 1103.

The rectifier 1101 converts the AC voltage V _AC from the antenna 12 into a first DC voltage V _DC1 . Here, the first DC voltage V _DC1 is a multiplied voltage of about 3.6 volts (V).

The voltage limiter 1105 restricts the level of the first DC voltage V _DC1 from the rectifier 1101 to not exceed an upper limit level, for example, about 3.6 volts (V).

The step-down unit 1103 steps down the first DC voltage V _DC1 from the rectifier 1101 and provides the digital control unit 1119 with a set DC voltage V _DC2 of about 1.7 volts (V).

4 illustrates an example of the signal delay unit 1113 of FIG. 2. 5 shows waveforms of each part in the circuit of FIG. 4. 4 and 5, reference numeral S _RS1 denotes a reset signal from the reset signal generator 1111 of FIG. 2, S _RS2 denotes a delayed reset signal of the rotor of the signal delay unit 1113 of FIG. 2, and V _C1 denotes a capacitor. The voltage of (C1) is indicated, respectively.

A time point t1 of FIG. 5 indicates a time point of rising of the reset signal S _RS1 from the reset signal generator 1111 of FIG. 2. The point in time t2 of FIG. 5 indicates a point of time when the delayed reset signal S _RS2 from the signal delay unit 1113 of FIG. 2 rises. The time t3 of FIG. 5 is a time of falling of the reset signal S _RS1 from the reset signal generator 1111 of FIG. 2, a time of falling of the delayed reset signal S _RS2 from the signal delay unit 1113, and a capacitor ( The rise time of the voltage of C41) is indicated.

4 and 5, the signal delay unit 1113 of FIG. 2 includes a first switch PM41, a resistor NM41, a capacitor C41, and an inverter INV41.

The first switch PM41 receives a set DC voltage V _DC2 from the power supply unit 21 of FIG. 2, and has a logic state in which the reset signal S _RS1 is high from the reset signal generator 1111 of FIG. 2. Off during (t1 to t3).

The resistor portion NM41 provides a current path between the first switch PM41 and the ground terminal.

The capacitor C41 performs charging and discharging between the first switch PM41 and the ground terminal.

The inverter INV41 is supplied with the set DC voltage V _DC2 from the power supply unit 21 of FIG. 2, and generates an inverted digital signal S _RS2 with respect to the voltage V _C1 of the capacitor C41.

The first switch PM41 is a P-channel field effect transistor. The set DC voltage V _DC2 from the power supply 21 is applied to the source of the P-channel field effect transistor as the first switch PM41. The reset signal S _RS1 is applied from the reset signal generator 1111 to a gate of the P-channel field effect transistor as the first switch PM41. The drain of the P-channel field effect transistor as the first switch PM41 is connected to the input terminal of the inverter INV41, the resistor portion NM41 and the capacitor C41.

The resistor portion NM41 is an N-channel field effect transistor.

The source of the N-channel field effect transistor as the resistor portion NM41 is grounded. A positive reference voltage S _REF is applied to a gate of the N-channel field effect transistor as the resistor portion NM41. The drain of the N-channel field effect transistor as the resistor portion NM41 is connected to the drain of the P-channel field effect transistor as the first switch PM41.

Accordingly, since the forward bias is applied to the gate of the resistor portion NM41, the resistor portion NM41 forms a current path while having a constant resistance value while the first switch PM41 is in an on state.

At time 0 to t1, since the reset signal S _RS1 from the reset signal generator 1111 of FIG. 2 is in a low logic state, the first switch PM41 is turned on. Accordingly, current flows from the first switch PM41 to the resistor portion NM41, and the voltage V _C41 of the capacitor C41 maintains the set DC voltage V _DC2 of about 1.7 volts V by charging. do.

At times t1 to t3, since the reset signal S _RS1 from the reset signal generator 1111 of FIG. 2 is in a high logic state, the first switch PM41 is turned off. As a result, the voltage V _C41 of the capacitor C41 is lowered by the discharge. As such, when the voltage V _C41 of the capacitor C41 reaches the threshold voltage of the inverter INV41 while the capacitor C41 is discharging, the output signal S _RS2 of the inverter INV41, that is, FIG. 2. The logic state of the delayed reset signal S _RS2 of the signal delay unit 1113 of the transitions from a low logic state to a high logic state.

By the above-described configuration and operation, the signal delay unit 1113 receives the reset signal S _RS1 from the reset signal generator 1111 for about 20 micro-seconds (μs) (t2 to t3 or t7 to t8). The delayed reset signal S _{RS2 is} provided to the flag generator (1123 of FIG. 2).

As is well known, the discharge rate of the capacitor C41 is inversely proportional to the product of the resistance value of the resistor portion NM41 and the capacitance of the capacitor C41. Therefore, the delay time t1 to t2 may be adjusted by adjusting the resistance value of the resistor NM41 and the capacitance of the capacitor C41.

6 illustrates another example of the signal delay unit 1113 of FIG. 2. In FIG. 6, the same reference numerals as used in FIG. 4 indicate objects of the same function.

Therefore, a difference between the circuit of the signal delay unit 1113 of FIG. 6 and the circuit of the signal delay unit 1113 of FIG. 4 is that the capacitor C41 is formed as a field effect transistor. The source and the drain of the field effect transistor as the capacitor C41 are grounded. In addition, a gate is connected to the input terminal of the inverter INV41.

According to the circuit of FIG. 6, an integrated circuit can be manufactured more easily than the circuit of FIG. 4. Of course, the operation of the circuit of FIG. 6 is as described with reference to FIG. 4.

FIG. 7 shows an example of the tag generator 1123 of FIG. 2. In FIG. 7, the same reference numerals as used in FIG. 2 indicate objects of the same function.

2 and 7, the tag generator 1123 of FIG. 2 includes a first inverter INV71, a second inverter INV72, a diode NM71, a capacitor C71, and a second N-type field effect. The transistor NM71 is included.

The first inverter INV71 operates by receiving the delayed reset signal S _RS2 from the signal delay unit 1113 as a power source, thereby inverting the flag signal Sdf from the digital control unit 1119.

The second inverter INV72 operates by receiving the delayed reset signal S _RS2 from the signal delay unit 1113 as a power source, thereby inverting the flag signal from the first inverter INV71.

The diode NM71 is connected between the second inverter INV72 and the flag input terminal of the digital controller 1119, and is turned on when the output signal from the second inverter INV72 is in a high logic state. Low logic states turn off.

The capacitor C71 is connected between the flag input terminal and the ground terminal of the digital control unit 1119, and is charged when the flag signal from the diode NM71 is in a high logic state.

In the second N-type field effect transistor NM71, the drain D thereof is connected to the flag input terminal of the digital controller 1119, the source S thereof is connected to the ground terminal, and the gate thereof is the first inverter INV71. When the flag signal from the first inverter INV71 is in a high logic state, the flag signal is turned on to discharge the capacitor C71.

The diode NM71 is a first N-type field effect transistor. In the first N-type field effect transistor as the diode NM71, the drain D and the gate are connected to the output terminal of the second inverter INV72, and the source S is connected to the flag input terminal of the digital controller 1119. .

FIG. 8 shows the structure of a conventional N-type field effect transistor as the diode NM71 of FIG. In FIG. 8, reference numeral B denotes a body end of the P + ion region, D denotes a drain of the N + ion region, G denotes a gate, and S denotes a source of the N + ion region, respectively.

9 equivalently shows the diagram of FIG. 8.

FIG. 10 shows that the charges that have been charged in the capacitor C71 of FIG. 7 are leaked by the equivalent circuit of FIG. 9.

FIG. 11 shows that the potential of the capacitor C71 of FIG. 7 is lowered faster by the leakage of FIG. 10. In FIG. 11, the same reference numerals as used in FIG. 3 indicate objects of the same function.

8 to 10, when a conventional N-type field effect overtransistor is used as the diode NM71 of Fig. 7, the body end B of the P + ion region should be grounded, so that the ground end and the drain It can be seen that the first parasitic diode JD _D1 grows in between, and the second parasitic diode JD _S1 grows between the ground terminal and the source. That is, it can be seen that parasitic diodes JD _D1 and JD _S1 are generated in addition to the normal diode MD ₁ .

Therefore, due to the characteristics of the capacitor C71 being charged, there is no possibility that current flows from the second parasitic diode JD _S1 to the capacitor C71 between the ground terminal and the source, but the first parasitic diode JD _D1 is removed from the ground terminal. There is a possibility that current flows through it. For example, when the potential of the first parasitic diode JD _D1 becomes lower than the ground terminal, the charges charged in the capacitor C71 leak from the ground terminal through the first parasitic diode JD _D1 . (See arrow in FIG. 10).

Therefore, due to such leakage, as shown in FIG. 11 (see the Sfd signal), the time for storing the flag signal of the high logic state in the flag generator (1123 in FIG. 2) is shortened during the interruption of power supply. There is a problem.

FIG. 12 shows an internal structure when the first N-type field effect transistor as the diode NM71 of FIG. 7 is an N-type field effect transistor for radio frequency.

Referring to FIG. 12, a structure of an N-type field effect transistor for a radio frequency as the diode NM71 of FIG. 7 will be described.

Deep N-type wells (DNW) 124 are formed over the underlying P-type substrate 123. In addition, an upper P-type substrate is formed in deep N-type well 124.

Drain D is formed in the upper P-type substrate as an N + ion region.

Sources (S) are also formed in the upper P-type substrate as N + ion regions.

Gates G and G are formed between the drain D and the source S.

A first guard ring 121 is formed between the drain D and one side of the deep N-type well 124.

A second guard ring 122 is formed between the source S and the other side of the deep N-type well 124.

The first guard ring 121 includes a first N-type well, a first N + ion region, and a first body region B. As shown in FIG. The first N-type well N-Well is formed between the drain D and one side of the deep N-type well 124. The first N + ion region is embedded in the first N-type well. The first body region B includes a first body region formed between the first N-type well N and the drain D. FIG.

Here, the first body region B is connected to the drain D.

The second guard ring 122 includes a second N-type well, a second N + ion region, and a second body region. The second N-type well N-Well is formed between the source S and the other side of the deep N-type well 124. The second N + ion region is embedded in the second N-type well. The second body region B is formed between the second N-type well N-Well and the source S.

Accordingly, referring to the structure of the N-type field effect transistor NM71 for radio frequency, it can be seen that the first body region B may be connected to the drain D. FIG. .

13 equivalently shows the diagram of FIG. 12. FIG. 14 shows that the charges charged to the capacitor of FIG. 7 are not leaked by the equivalent circuit of FIG. 13. FIG. 15 is a timing diagram illustrating that the potential of the capacitor C71 of FIG. 7 is lowered later by not leaking as shown in FIG. 14. In FIG. 15, the same reference numerals as used in FIG. 3 indicate objects of the same function.

12 to 14, when the N-type field effect transistor NM71 for radio frequency is used as the diode NM71, the body region B of the P + ion region is the drain D. Can be connected to.

Accordingly, it can be seen that only the parasitic diode JD _S1 between the drain D and the source S grows native. That is, it can be seen that one parasitic diode JD _S1 is generated in addition to the normal diode MD ₁ . In addition, since the parasitic diode JD _S1 is connected in the same manner as the normal diode MD ₁ , no leakage current flows.

Therefore, since no leakage current flows as described above, as shown in FIG. 15 (see the Sfd signal), the flag generator (1123 of FIG. 2) stores the high logic state flag signal during the interruption of power supply. It can be seen that the time to do not shorten.

FIG. 16 illustrates another example of the tag generator 1123 of FIG. 2. In FIG. 16, the same reference numerals as used in FIG. 7 indicate objects of the same function. Thus, the only difference of FIG. 16 to FIG. 7 is that a P-type field effect transistor is used as the diode PM71 of FIG.

Referring to FIG. 16, in the first P-type field effect transistor as the diode PM71, the source S is connected to the output terminal of the second inverter INV72, and the drain D and the gate are connected to the digital control unit 1119. Is connected to the flag input of.

FIG. 17 shows the structure of a P-type field effect transistor as the diode PM71 of FIG. 18 equivalently shows the diagram of FIG. 17. FIG. 19 shows that the charges charged to the capacitor C71 of FIG. 16 are not leaked by the equivalent circuit of FIG. 18.

16 to 19, the first P-type field effect transistor as the diode PM71 includes a base P-type substrate 171, an N-type well 172, a drain D, a source S, A gate G, and a body region.

An N-type well 172 is formed over the base P-type substrate 171.

In the N-type well 172, a drain D and a source S as P + ion regions are formed, respectively. A gate G is formed between the drain D and the source S. In addition, in the N-type well 172, a body region B is formed as an N + ion region. Body region B is connected to drain D.

As described above, when the P-type field effect transistor is used as the diode PM71, the body region B of the N + ion region may be connected to the drain D.

As a result, it can be seen that only the parasitic diode JD _S2 between the drain D and the source S grows native. That is, it can be seen that one parasitic diode JD _S2 is generated in addition to the normal diode MD ₁ . In addition, since the parasitic diode JD _S2 is connected in the same manner as the normal diode MD ₁ , no leakage current flows.

Therefore, since no leakage current flows as described above, as shown in FIG. 15 (see the Sfd signal), the flag generator (1123 of FIG. 2) stores the high logic state flag signal during the interruption of power supply. It can be seen that the time to do not shorten.

As described above, according to the method for controlling the radio electronic label according to the present invention and the radio electronic label employing the same, the delayed reset signal from the signal delay unit is applied as a power source of the flag generation unit. In other words, the flag generator starts operation later than the digital controller.

Accordingly, the wireless electronic label according to the present invention is turned off due to the momentary instability of the supply power just before reproducing and returning the tag signal from the reader, and then back on again for a short time. When restored, the flag generator starts operation later than the digital controller.

Therefore, even if the digital control section inputs a flag signal in an unknown logic state immediately after re-initializing the operation, the flag generation section does not respond to it. The flag generation section outputs a flag signal of a logic state, which has been reproduced and stored immediately before the off state, to the digital controller. That is, the flag signal of the logic state which was reproduced and stored immediately before the off state can be conveyed to the reader through the digital control unit. Accordingly, the reader may receive a flag signal of a logic state transmitted by the reader and communication may be resumed.

As a result, the problem that communication between any one of the wireless electronic labels and the reader is inefficiently delayed due to instantaneous instability of the power supply can be improved.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is a plan view showing an internal structure of an RFID tag as a wireless electronic label employing a control method according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an internal configuration of the integrated circuit device of FIG. 1.

3 is a timing diagram showing waveforms of each signal generated in the circuit of FIG. 2.

4 is a circuit diagram illustrating an example of the signal delay unit of FIG. 2.

FIG. 5 is a timing diagram showing waveforms of each unit in the circuit of FIG. 4.

6 is a circuit diagram illustrating still another example of the signal delay unit of FIG. 2.

FIG. 7 is a circuit diagram illustrating an example of a tag generator of FIG. 2.

FIG. 8 shows the structure of a conventional N-type field effect transistor as the diode of FIG.

FIG. 9 is an equivalent circuit diagram of the diagram of FIG. 8.

FIG. 10 is a circuit diagram illustrating leakage of charges charged in the capacitor of FIG. 7 by the equivalent circuit of FIG. 9.

FIG. 11 is a timing diagram illustrating that the potential of the capacitor of FIG. 7 is lowered faster by the leakage of FIG. 10.

FIG. 12 is a diagram illustrating an internal structure when the first N-type field effect transistor as the diode of FIG. 7 is an N-type field effect transistor for radio frequency.

FIG. 13 is a circuit diagram equivalently showing the drawing of FIG. 12.

FIG. 14 is a circuit diagram illustrating that the charges charged in the capacitor of FIG. 7 are not leaked by the equivalent circuit of FIG. 13.

FIG. 15 is a timing diagram illustrating that the potential of the capacitor of FIG. 7 is lowered later by not leaking as shown in FIG. 14.

16 is a circuit diagram illustrating still another example of the tag generator of FIG. 2.

FIG. 17 shows the structure of a P-type field effect transistor as the diode of FIG.

FIG. 18 is a circuit diagram equivalently showing the diagram of FIG. 17.

FIG. 19 is a circuit diagram illustrating that charges charged to the capacitor of FIG. 16 are not leaked by the equivalent circuit of FIG. 18.

<Explanation of symbols for the main parts of the drawings>

1 RFID tag, 11 integrated circuit device,

12 antenna, 21 power supply,

1101 ... rectifier, 1103 ...

1105 ... voltage limiter, 1107 ... demodulator,

1109 ... modulator, 111 ... reset signal generator,

1113 ... signal delay section, 1115 ... clock pulse generator section,

1117 ... booster, 1119 ... digital control,

1121 ... Memory, 1123 ... Flag generation part.

Claims (12)

In the wireless electronic label control method including an antenna, a digital control unit, a power supply unit, a reset signal generator, and a flag generator, Converting, by the power supply unit, an alternating voltage from the antenna into a set direct current voltage and providing the same to the digital controller; Generating, by the reset signal generator, a reset signal to the digital controller while the DC voltage from the power supply rises above the rated level; Reproducing, by the flag generation unit, a flag signal from the digital control unit and conveying the flag signal to the digital control unit; And Delaying the reset signal from the reset signal generator, and using the delayed reset signal as a power supply voltage of the flag generator. A wireless electronic label comprising an antenna and an integrated circuit element, The integrated circuit device, A digital controller; A power supply unit converting an AC voltage from the antenna into a set DC voltage and providing the same to the digital controller; A reset signal generator for generating a reset signal and providing it to the digital controller while the DC voltage from the power supply rises above the rated level; A flag generator which reproduces a flag signal from the digital controller and returns the flag signal to the digital controller; And And a signal delay unit for delaying the reset signal from the reset signal generator and outputting the delayed reset signal as a power supply voltage of the flag generator. The method of claim 1, wherein the signal delay unit, A first switch supplied with a set direct current voltage from the power supply and turned off while the reset signal is in a high logic state from the reset signal generator; A resistor unit providing a current path between the first switch and a ground terminal; A capacitor performing charge / discharge between the first switch and a ground terminal; And And an inverter receiving a set direct current voltage from the power supply unit and generating an inverted digital signal with respect to the voltage of the capacitor. The method of claim 1, wherein the flag generator, A first inverter configured to receive a delayed reset signal from the signal delay unit as a power source and to invert a flag signal from the digital controller; A second inverter configured to receive a delayed reset signal from the signal delay unit as a power source and to invert the flag signal from the first inverter; Connected between the second inverter and a flag input terminal of the digital controller, the output signal from the second inverter is turned on when the logic state is high, and turned off when the logic state is low; diode; A capacitor connected between a flag input terminal and a ground terminal of the digital controller, the capacitor being charged when the flag signal from the diode is in a high logic state; And A drain thereof is connected to a flag input terminal of the digital controller, a source thereof is connected to a ground terminal, a gate thereof is connected to an output terminal of the first inverter, and when the flag signal from the first inverter is in a high logic state; A wireless electronic label comprising a second N-type field effect transistor that is turned on to discharge the capacitor. The method of claim 4, wherein the diode, Wireless electronic label, an N-type field effect transistor for radio frequency. The N-type field effect transistor for radio frequency as the diode, A base P-type substrate; A deep N-type well formed over the underlying P-type substrate; An upper P-type substrate formed from the deep N-type well; A drain formed in the upper P-type substrate as an N + ion region; A source formed in said upper P-type substrate as an N + ion region; A gate formed between the drain and the source; A first guard ring formed between the drain and one side of the deep N-type well; And And a second guard ring formed between the source and the other side of the deep N-type well. The method of claim 6, wherein the first guard ring (Guard Ring), A first N-type well formed between the drain and one side of the deep N-type well; A first N + ion region embedded in the first N-type well; And And a first body region formed between the first N-type well and the drain. The method of claim 7, wherein Wireless electronic label wherein the first body region is connected to the drain. The method of claim 8, wherein the second guard ring (Guard Ring), A second N-type well formed between the source and the other side of the deep N-type well; A second N + ion region embedded in the second N-type well; And And a second body region formed between the second N-type well and the source. The method of claim 4, wherein the diode, And a source thereof is connected to an output terminal of the second inverter, and a drain and a gate thereof are connected to a flag input terminal of the digital controller. The P-type field effect transistor as the diode of claim 10, A base P-type substrate; An N-type well formed over said base P-type substrate; A drain formed in the N-type well as a P + ion region; A source formed in the N-type well as a P + ion region; A gate formed between the drain and the source; And A wireless electronic label comprising a body region formed within said N-type well as an N + ion region. The method of claim 11, A wireless electronic label in which the body region and the drain are connected to each other.

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