KR20100067598A - Reading method of nonvolatile semiconductor device - Google Patents

Abstract

PURPOSE: A reading method of a nonvolatile semiconductor device is provided to enable a word line to start fast by supplying a high voltage to a word line and then providing a certain level of voltage to the word line to read the word line. CONSTITUTION: A voltage higher than a fixed level is provided to a word line and starts the word line(a). The fixed level is provided to the word line. The word line voltage of the fixed level is set and reading of the word line is performed. A non-volatile semiconductor memory device supplies voltages of a low level, a middle level, and a high level to a word line. The voltage of a middle level(M) is supplied to the word line, and then the voltage of a low level is supplied to the word line. The voltage of a high level is supplied to the word line, and then the voltage of a middle level is supplied to the word line after the word line starts.

Description

READING METHOD OF NONVOLATILE SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to a method of reading a nonvolatile semiconductor memory device effective for application to a multilevel cell.

As one of the nonvolatile semiconductor memory devices, there is a multi-level cell (hereinafter referred to as "MLC") capable of storing a plurality of pieces of information. When MLC is used, word line voltage steps of N-1 times (N is the number of thresholds in the MLC, N-1 times normally three times) are required in one read operation.

1 is a view showing a waveform diagram of a word line voltage in a read operation when a conventional MLC is used.

Prior to referring to FIG. 1, the word line voltage is controlled in three stages: low level (L), medium level (M), and high level (H). Depending on which of the three stages the current flows through the MLC, one of the two bit data can be extracted.

However, for normal memory, the read time is specified by the specification. The memory steps the word line voltage within read time for data output. If the start time of the word line voltage is late, the memory performs a read operation without reaching the desired word line voltage level. As a result, problems such as read errors and difficulty in securing margins occur. In addition, since the load of the word line increases as the capacity increases, there is a problem in that the word line voltage is different at the near end and the far end of the cell array due to the delay caused by the load, so that sufficient margin cannot be obtained.

This problem is described with reference to FIG. 1. Referring to Fig. 1, the solid line in the figure is a word line voltage applied to a corner ((load: light)) of the cell array, that is, the gate of the cell closest to the word line driver. The dotted line in the figure is the word line voltage applied to the center portion ((load: heavy) of the cell array, that is, the gate of the cell furthest from the word line driver). However, whether the central load is the biggest depends on whether it is a drive on both sides or a drive on one side. When the word line voltage rises slowly, the word line voltage does not reach the desired level in the center of the cell array at the time of detecting the cell current in the sense amplifier, making it difficult to secure read errors and margins.

At this time, it is possible to avoid the read error and the lack of margin by delaying the sense time and waiting until the desired word line voltage is reached. However, this results in a delay of the read operation itself.

Further, Patent Document 1 (Japanese Patent Laid-Open No. 7-9889) further divides the main word line selected by the main decoder into a sub decoder to reduce the load on the main word line to start the word line voltage. It accelerates and speeds up. However, this method with a sub decoder leads to an increase in layout area. In recent years, since the capacity of the nonvolatile memory is increasing, the word line is increased. The method with the subdecoder requires the same number of sub decoders as the word line due to the increased word line.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above technical problem, and an object of the present invention is to provide a reading method of a nonvolatile semiconductor memory device capable of speeding up a read operation by speeding up a startup time of a word line voltage.

Another object of the present invention is to provide a method of reading a nonvolatile semiconductor memory device which can be read with sufficient margin.

Another object of the present invention is to provide a method of reading a nonvolatile semiconductor memory device which does not cause an increase in layout area.

According to another aspect of the present invention, there is provided a method of reading a nonvolatile semiconductor memory device in which a voltage is applied to a word line to read a word line, the method including starting a word line voltage by supplying a voltage higher than the predetermined level to the word line. Supplying a voltage of a level to the word line, and setting and reading the word line voltage of the predetermined level.

In this embodiment, the nonvolatile semiconductor memory device is a multi-level cell for reading by supplying voltages of low level, medium level, and high level to a word line, and in the case of supplying the low level voltage to a word line, When the voltage of the level is supplied to the word line to start the word line voltage, the voltage of the low level is supplied to the word line, and the voltage of the medium level is supplied to the word line. When the word line voltage is supplied to start the word line voltage, the medium level voltage is supplied to the word line, and the high level voltage is supplied to the word line. After starting, the high level voltage is supplied to the word line.

According to an exemplary embodiment of the present invention, a method of reading a nonvolatile semiconductor memory device, in which a plurality of levels of voltages are sequentially supplied to a word line, is used to perform a read operation by supplying a voltage of the highest level to the word lines. And performing a read operation by supplying the voltage of the one-level lower level to the word line at the time when the line voltage is discharged and lowered to the voltage of the one-level lower level.

In this embodiment, the nonvolatile semiconductor memory device is a multi-level cell that reads by supplying low, medium, and high voltages to a word line, and supplies a read operation by supplying the high level voltage to the word line. When the word line voltage is discharged and the word line voltage is lower than the medium level voltage, the medium line voltage is supplied to the word line to perform a read operation, and the word line voltage is discharged to discharge the word line voltage. The read operation is performed by supplying the low level voltage to the word line at a time point lower than the low level voltage.

In this embodiment, the word line voltage is discharged by an NMOS transistor connected to the word line.

According to the present invention, the read method proposed in the present invention can speed up the startup time of the word line voltage, thereby increasing the read operation speed and ensuring the margin. In addition, the read method proposed in the present invention does not cause an increase in the layout area as in the case of the sub decoder, since only the voltage converting and discharging means needs to be provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only parts necessary for understanding the operation according to the present invention will be described, and descriptions of other parts will be omitted so as not to distract from the gist of the present invention.

The present invention provides a method of reading a nonvolatile semiconductor memory device. Embodiments of the present invention are described in detail below.

First, the first embodiment of the present invention is described below.

The first embodiment of the present invention is a multi-level cell (hereinafter referred to as 'MLC') for reading by supplying voltages of low level (L), medium level (M), and high level (H) to a word line. It will be applied to).

2 is a waveform diagram for explaining a first embodiment of the present invention.

Referring to FIG. 2, (a) shows a word line voltage, (b) equalizes, (c) output data, and (d) shows a word line supply voltage. For the word line voltage waveform of (a), the solid line is the word line voltage applied to the gate of the cell closest to the word line driver, and the dotted line is the word line voltage applied to the gate of the cell farthest from the word line driver.

For the MLC, the nonvolatile semiconductor memory device reads by supplying the voltages of the low level (L), the middle level (M), and the high level (H) to the word lines in sequence.

However, as shown in Fig. 2, in the first embodiment of the present invention, when a low level L voltage is supplied to a word line for reading, the nonvolatile semiconductor memory device applies a medium level M voltage. Once supplied to the word line to start the word line voltage. Thereafter, the low level L voltage is supplied to the word line to read.

In addition, when reading is performed by supplying the voltage of the middle level M to the word line, the nonvolatile semiconductor memory device starts the word line voltage by supplying the voltage of the high level H to the word line. Thereafter, the voltage of the middle level M is supplied to the word line for reading.

In addition, when reading is performed by supplying the high level H voltage to the word line, the nonvolatile semiconductor memory device supplies the word line voltage higher than the high level H to the word line to supply the word line voltage. Start up. Thereafter, a high level voltage is supplied to the word line to read.

As described above, in the first embodiment of the present invention, when the nonvolatile semiconductor memory device reads by supplying a predetermined level of voltage to the word line, the nonvolatile semiconductor memory device starts to supply the higher voltage to the word line to start the word line voltage. Thereafter, a voltage of a predetermined level for returning to the original voltage is supplied to the word line for reading.

Here, the higher the start level of the word line is, the higher the arrival voltage at any time or the faster the arrival time at any voltage. Therefore, it can be seen from Equation 1 below that when the word line voltage is started at a voltage higher than the read voltage of each level, the start time of the word line voltage is fast.

은 워드 라인 전압, E는 일단 시동하는 레벨의 전압, RC는 드라이버와 워드 라인에 포함되는 부하이다.In Equation 1,

Is the word line voltage, E is the voltage at the level of starting, and RC is the load included in the driver and word line.

Thus, in the first embodiment of the present invention, in the nonvolatile semiconductor memory device, the start of the word line voltage is faster, the read voltage is confirmed faster, and the read voltage at the near end and far-end of the cell array is faster. As a result, margins are improved, resulting in faster read operations. In addition, since the method as in the first embodiment only needs to have a voltage converting means, it does not cause an increase in layout area as in the case of having a sub decoder.

3 is a circuit diagram for realizing a first embodiment of the invention.

Referring to FIG. 3, WL is a word line and is connected to gates of the plurality of MLCs 11. The drain of each MLC 11 is connected to the corresponding bit line BL. The word line WL is driven by a word line driver 12 which receives a decode signal. The word line voltage conversion circuit 13 is connected to the word line driver 12.

The word line voltage conversion circuit 13 includes a low level L, a middle level M, a high level H, and a voltage source VPX of a fourth level Z, and first to fourth switch transistors 14L and 14M. , 14H, 14Z). The first to fourth transistors 14L, 14M, 14H, and 14Z may supply voltages of the voltage source VPX (low level L, middle level M, high level H, and fourth level Z). Supply to the word line driver. The first switch transistor 14L is controlled by the first switch control signal RDHBL to supply a low level L voltage to the word line driver 12. The second switch transistor 14M is controlled by the second switch control signal RDHBM to supply a voltage of the middle level M to the word line driver 12. The third switch transistor 14H is controlled by the third switch control signal RDHBH to supply the high level H voltage to the word line driver 12. The fourth switch transistor 14Z is controlled by the fourth switch control signal RDHBZ to supply the voltage of the fourth level Z to the word line driver 12.

In order to realize the operation according to the first embodiment, the operation of the first to fourth switch transistors will be described.

When reading by supplying the voltage of the low level L to the word line WL, the second switch transistor 14M is turned on once by the second switch control signal RDHBM and the voltage of the middle level M is turned on. Supply to word line driver 12 or word line WL. Thereafter, the first switch transistor 14L is turned on by the first switch control signal RDHBL to supply a low level L voltage to the word line driver 12 or the word line WL.

In addition, when the voltage of the middle level M is supplied to the word line WL for reading, the third switch transistor 14H is turned on once by the third switch control signal RDHBH and the high level H is turned on. The voltage is supplied to the word line WL. Thereafter, the second switch transistor 14M is turned on by the second switch control signal RDHBM and supplies the voltage of the middle level M to the word line WL.

When the high level H is supplied to the word line WL for reading, the fourth switch transistor 14Z is turned on once by the fourth switch control signal RDHBZ and the fourth level Z is turned on. Is supplied to the word line WL. Thereafter, the third switch transistor 14H is turned on by the third switch control signal RDHBH to supply a high level H voltage to the word line WL.

Moreover, since the voltages of the low level L, the middle level M, and the high level H exist in the existing circuit, they are used. However, since the voltage of the fourth level Z does not exist in the existing circuit, a separate power source is prepared and generated. Moreover, the voltage of the low level L, the middle level M, and the high level H can also be generated through another power supply.

The same word line voltage control method as that of the first embodiment can also be applied to a single level cell SLC.

Next, a second embodiment of the present invention is described below.

The second embodiment of the present invention is applied to an MLC which reads by supplying voltages of low level (L), medium level (M), and high level (H) to a word line.

4 is a waveform diagram for explaining a second embodiment of the present invention.

Referring to FIG. 4, (a) shows a word line voltage, (b) equalizes, (c) output data, (d) shows a word line supply voltage, and (e) shows a discharge timing. For the word line voltage waveform of (a), the solid line is the word line voltage applied to the gate of the cell closest to the word line driver, and the dotted line is the word line voltage applied to the gate of the cell farthest from the word line driver.

For the MLC, the nonvolatile semiconductor memory device reads by supplying the voltages of the low level (L), the middle level (M), and the high level (H) in turn to the word line.

However, as shown in Fig. 4, in the second embodiment of the present invention, the nonvolatile semiconductor memory device first supplies the high level H voltage to the word line to start the word line voltage up to the high level H. The nonvolatile semiconductor memory device performs a read operation at the high level H for the first time with the voltage at the high level H supplied to the word line.

Next, the nonvolatile semiconductor memory device turns on the word line voltage discharge NMOS transistor connected to the word line to discharge the word line voltage. The nonvolatile semiconductor memory device turns off the word line voltage discharge NMOS transistor when the word line voltage is lower than the voltage of the middle level (M). At the same time, the nonvolatile semiconductor memory device performs a read operation at the middle level M with the voltage of the middle level M supplied to the word line and the voltage of the middle level M supplied to the word line.

Thereafter, the nonvolatile semiconductor memory device turns on the word line voltage discharge NMOS transistor connected to the word line again to discharge the word line voltage again. The nonvolatile semiconductor memory device turns off the word line voltage discharge NMOS transistor when the word line voltage falls below the low level (L) voltage. At the same time, the nonvolatile semiconductor memory device supplies a low level L voltage to the word line to perform a read operation at the low level L while the low level L voltage is supplied to the word line.

Here, the higher the start level of the word line is, the higher the arrival voltage at any time or the faster the arrival time at any voltage. Therefore, it can be seen from Equation 2 below that the start time of the word line is faster than supplying the highest voltage to the word line for the first time, rather than increasing the word line voltage from the low level in turn.

은 워드 라인 전압, E는 일단 시동하는 레벨의 전압, RC는 드라이버와 워드 라인에 포함되는 부하이다. 또한, 방전용의 NMOS 트랜지스터는 드라이버에 포함되는 PMOS 트랜지스터보다 온 저항이 낮기 때문에, 수학식 2에 있어서 RC가 작아진다. 즉, 부하가 가벼워져 시동 또는 보다 더 빠른 시간에 방전을 실시할 수 있다.In Equation 2,

Is the word line voltage, E is the voltage at the level of starting, and RC is the load included in the driver and word line. In addition, since the on-resistance of the NMOS transistor for discharge is lower than that of the PMOS transistor included in the driver, RC in Equation 2 becomes small. In other words, the load becomes lighter, and the discharge can be performed at the start-up or faster time.

Therefore, the second embodiment of the present invention first supplies the highest level of voltage to the word line, and then sequentially lowers the voltage by the discharge from the voltage. Then, in the second embodiment of the present invention, as in the first embodiment, the read voltage is confirmed faster, and the read voltage is confirmed at the near end and far-end of the cell array. As a result, the read operation can be speeded up. In addition, the method similar to the second embodiment only needs to have voltage conversion and discharge means, and thus does not cause an increase in layout area as in the case of providing a sub decoder.

5 is a circuit diagram for realizing a second embodiment of the present invention.

Referring to FIG. 5, the circuit of FIG. 5 has a structure similar to that of FIG. 3. However, for the word line voltage conversion circuit 13, the voltage source of the fourth level Z and the fourth switch transistor 14Z are omitted. On the other hand, the NMOS transistor 15 for word line voltage discharge is connected to the word line WL. The NMOS transistor 15 is controlled by the word line discharge control signal DCG.

The word line voltage converting circuit 13 firstly turns on the third switch transistor 14H by the third switch control signal RDHBH to supply a high level H voltage to the word line driver 12 or the word line WL. The read operation is performed at a high level (H) voltage by supplying the power to.

Next, the word line voltage conversion circuit 13 turns on the word line voltage discharge NMOS transistor 15 by the word line discharge control signal DCG to discharge the word line voltage. The word line voltage conversion circuit 13 turns off the word line voltage discharge NMOS transistor 15 when the word line voltage falls below the voltage at the middle level M. As shown in FIG. At the same time, the word line voltage converting circuit 13 turns on the second switch transistor 14M by the second switch control signal RDHBM to convert the voltage of the medium level M into the word line driver 12 or the word line WL. ), The read operation is performed at the voltage of the middle level (M).

Thereafter, the word line voltage conversion circuit 13 turns on the word line voltage discharge NMOS transistor 15 again by the word line discharge control signal DCG to discharge the word line voltage again. The word line voltage conversion circuit 13 turns off the word line voltage discharge NMOS transistor 15 when the word line voltage falls below the low level (L) voltage. At the same time, the word line voltage conversion circuit 13 turns on the first switch transistor 14L by the first switch control signal RDHBL to supply the low level L voltage to the word line driver 12 or the word line WL. By supplying it to, the read operation is performed at a low level (L) voltage. In this manner, the operation according to the second embodiment can be realized.

In the nonvolatile semiconductor memory device, a voltage higher than a predetermined level is supplied to a word line to start a word line voltage, and then a voltage of a predetermined level is supplied to a word line for reading. In addition, the present invention first supplies a voltage of the highest level to a word line to perform a read operation, and then lowers the voltage by the discharge from the voltage to perform a read operation at the next level.

That is, the present invention includes two embodiments.

First, the nonvolatile semiconductor memory device starts a word line voltage to supply a word line with a second level higher than that of the first level. The nonvolatile semiconductor memory device supplies a second level of voltage to a word line. Thereafter, the nonvolatile semiconductor memory device supplies a voltage of a first level to a word line. The nonvolatile semiconductor memory device performs a read operation with a voltage of a first level supplied to a word line. When starting (ie, rising) each level voltage, the nonvolatile semiconductor memory device uses a voltage higher than the level voltage for reading.

Secondly, the nonvolatile semiconductor memory device starts up the word line voltage to supply a fourth voltage lower than the voltage of the third level to the word line. The nonvolatile semiconductor memory device supplies a fourth level of voltage to a word line. Thereafter, the nonvolatile semiconductor memory device supplies a fourth level of voltage to the word line. The nonvolatile semiconductor memory device performs a read operation in a state where a voltage of a fourth level is supplied to a word line. When starting (ie, decreasing) each level voltage, the nonvolatile semiconductor memory device uses a voltage lower than that level voltage for reading.

As such, the nonvolatile semiconductor memory device of the present invention increases the word line voltage (for example, a precharge period) to a voltage higher than the voltage of the corresponding level before the detection period (that is, the detection time) to reduce the read operation time. Or lower the word line voltage to a lower voltage (eg, a discharge period). The precharge section is a section in which the word line voltage is precharged, and the discharge section is a section in which the word line voltage is discharged.

Meanwhile, switch control signals RDHBL, RDHBM, RDHBH, and RDHBZ and word line discharge control signals DCG for controlling the switches may be generated by a control circuit (not shown) that controls the overall operation of the nonvolatile semiconductor memory device. Can be.

The present invention can speed up the read operation by increasing the startup time of the word line voltage. In addition, the present invention enables a read operation with sufficient margin, and does not cause an increase in layout area.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

1 is a waveform diagram of a word line voltage in a read operation when a conventional MLC is used.

2 is a waveform diagram for explaining a first embodiment of the present invention;

3 is a circuit diagram for realizing a first embodiment of the invention;

4 is a waveform diagram for explaining a second embodiment of the present invention, and

5 is a circuit diagram for realizing a second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

WL: word line BL: bit line

11: MLC 12: Word Line Driver

13: word line voltage conversion circuit

14L, 14M, 14H, 14Z: first to fourth switch transistors

15: NMOS transistor for word line voltage discharge

Claims (5)

A read method of a nonvolatile semiconductor memory device for reading by supplying a voltage of a predetermined level to a word line, Starting a word line voltage by supplying a voltage higher than the predetermined level to the word line; Supplying the voltage of the predetermined level to the word line; And Setting the word line voltage at the predetermined level and performing a read. The method of claim 1, The nonvolatile semiconductor memory device is a multi-level cell for reading by supplying voltages of low, middle, and high levels to a word line, When the low level voltage is supplied to the word line, the medium level voltage is supplied to the word line to start a word line voltage, and then the low level voltage is supplied to the word line. When the medium level voltage is supplied to the word line, the high level voltage is supplied to the word line to start a word line voltage, and then the medium level voltage is supplied to the word line. And when the high level voltage is supplied to the word line, a voltage higher than the high level is supplied to the word line to start a word line voltage, and then the high level voltage is supplied to the word line. A read method of a nonvolatile semiconductor memory device in which a plurality of levels of voltage are sequentially supplied to a word line for reading. Supplying a voltage of a highest level to the word line to perform a read operation; And And discharging the word line voltage to supply a lower level voltage to the word line to perform a read operation when the word line voltage is discharged. The method of claim 3, wherein The nonvolatile semiconductor memory device is a multi-level cell for reading by supplying voltages of low, middle, and high levels to a word line, A read operation is performed by supplying the high level voltage to the word line; When the word line voltage is discharged and the word line voltage falls below the middle level voltage, the middle line voltage is supplied to the word line to perform a read operation. And discharging a word line voltage to supply the low level voltage to the word line when the word line voltage is lower than the low level voltage to perform a read operation. The method according to any one of claims 3 and 4, And the discharge of said word line voltage is performed by an NMOS transistor connected to said word line.

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