KR20100066939A - Semiconductor package - Google Patents

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Publication number
KR20100066939A
KR20100066939A KR1020080125462A KR20080125462A KR20100066939A KR 20100066939 A KR20100066939 A KR 20100066939A KR 1020080125462 A KR1020080125462 A KR 1020080125462A KR 20080125462 A KR20080125462 A KR 20080125462A KR 20100066939 A KR20100066939 A KR 20100066939A
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South Korea
Prior art keywords
circuit board
printed circuit
ball
semiconductor package
substrate body
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Application number
KR1020080125462A
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Korean (ko)
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정정태
김종현
권진호
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주식회사 하이닉스반도체
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Priority to KR1020080125462A priority Critical patent/KR20100066939A/en
Publication of KR20100066939A publication Critical patent/KR20100066939A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE: A semiconductor package is provided to improve an adhesion between a solder ball and a ball land by attaching the solder ball including a metal particle to the ball land which is coated with a persistent magnetic powder. CONSTITUTION: A printed circuit board(100) includes a substrate body, a first wiring(112a) and a second wiring(112b). The first wiring is arranged on the one side of the substrate body and includes a bond finger. The second wiring is arranged on the other side of the substrate body and includes a ball land(116). A semiconductor chip(122) is attached on the printed circuit board. A connecting unit(126) electrically connects the semiconductor chip and the printed circuit board. An outer connector(130) is attached to the ball land of the printed circuit board and contains a metal particle.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor Package {SEMICONDUCTOR PACKAGE}

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 솔더 볼과 같은 외부 접속 단자의 실장 신뢰성을 향상시킨 반도체 패키지에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having improved mounting reliability of an external connection terminal such as a solder ball.

최근 들어 집적회로 칩의 집적도가 증가하면서 동일 크기의 칩에 더 많은 회로 배치가 가능해짐에 따라 집적회로 칩은 더 많은 입출력 신호를 주고받게 되었다. 이에 따라, 반도체 패키지 역시 제한된 면적 내에 더 많은 입출력 핀을 배치해야 할 필요가 있다.In recent years, as the degree of integration of integrated circuit chips has increased, more circuit arrangements are possible on chips of the same size, and thus the integrated circuit chips have more I / O signals. Accordingly, the semiconductor package also needs to place more input / output pins within a limited area.

이러한 요구를 충족시키기 위한 방편 중의 하나로 BGA(Ball Grid Array) 패키지가 개발되어 사용중이다. One way to meet these needs is to develop and use a Ball Grid Array (BGA) package.

상기와 같은 BGA 패키지는 부품 실장시 더 많은 수의 부품, 즉, 반도체 칩을 실장 할 수 있는 고밀도화 및 고정도화가 가능한 인쇄회로기판을 이용한 실장 기술을 이용하고 있는 추세이며, 그에 대한 관심도 점점 증가하고 있는 실정이다. The BGA package is using a mounting technology using a printed circuit board capable of high-density and high-precision mounting of a larger number of components, that is, a semiconductor chip, and the interest is also increasing. It is true.

따라서, 전자기기의 경박 단소화를 위한 기술은 실장되는 부품의 미세 가공 기술 뿐만 아니라, 고밀도의 부품 실장을 가능하게 하는 인쇄회로기판의 제공이 필수적으로 요구된다. Therefore, the technology for light and thin shortening of the electronic device is required to provide a printed circuit board that enables high-density component mounting, as well as fine processing technology of the components to be mounted.

특히, 입출력 핀들이 칩 주변 쪽에 1차원적으로 배열되던 기존의 리드 프레임(Lead Frame) 패키지와 달리, BGA 패키지는 입출력 핀으로 사용되는 솔더 볼(Solder Ball)들을 칩 표면 쪽에 2차원적으로 배열하기 때문에 훨씬 효율적인 핀 배치가 가능해졌다.In particular, unlike conventional lead frame packages in which I / O pins are arranged one-dimensionally around the chip, BGA packages have two-dimensional arrangement of solder balls used as I / O pins on the chip surface. This makes pin placement much more efficient.

한편, 반도체 패키지 분야에서는 점점 고용량의 반도체 모듈을 제공하기 위하여 많은 연구가 진행되어 왔으며, 반도체 칩의 패키징 밀도를 높이기 위한 일환으로서 상기와 같은 BGA 패키지 보다 더 소형화된 소위 칩 스케일 패키지라 불리는 FBGA(Fine Pitch Ball Grid Array) 패키지가 개발되었다. On the other hand, in the field of semiconductor packaging, a lot of research has been conducted to provide higher capacity semiconductor modules, and as a part to increase the packaging density of semiconductor chips, FBGA (Fine called FBGA), which is more compact than the BGA package as described above, is further miniaturized. The Pitch Ball Grid Array package has been developed.

이러한 FBGA 패키지는 전술한 BGA 패키지의 일종으로서 상기 BGA에 비해 상대적으로 크기가 작고 매우 좁은 간격으로 배열된 솔더 볼 어레이(Solder Ball Array)를 채용하고 있다. The FBGA package is a kind of the above-described BGA package and employs a solder ball array that is relatively smaller in size than the BGA and is arranged at very narrow intervals.

그러나, 자세하게 도시하고 설명하지는 않았지만, 전술한 종래 기술의 경우에는, 점점 소형화되는 패키지의 크기가 대응하여 솔더 볼의 크기도 점점 소형화됨에 따라 인쇄회로기판의 볼 랜드에 상기 솔더 볼을 부착하는 솔더 볼 마운트 공정시, 상기 솔더 볼을 정확하게 부착하기가 점점 어려워져 그에 따른 여러 문제점이 발생되고 있다.However, although not shown and described in detail, in the above-described prior art, the solder ball attaching the solder ball to the ball land of the printed circuit board as the size of the package becomes smaller and the solder ball becomes smaller. In the mounting process, it is increasingly difficult to accurately attach the solder balls, which causes various problems.

예컨대, 볼 랜드에 솔더 볼이 부착되지 않는 미싱(Missing) 볼 현상 및 인접한 솔더 볼 간들이 접합되는 브릿지(Bridge) 볼 및 더블(Double) 볼 현상이 발생되게 된다.For example, a missing ball phenomenon in which a solder ball does not adhere to a ball land, and a bridge ball and a double ball phenomenon in which adjacent solder balls are joined are generated.

따라서, 전체 반도체 패키지에서 불량이 발생하게 되고, 그 결과 생산성이 저하되게 된다.Therefore, defects occur in the entire semiconductor package, and as a result, productivity is lowered.

본 발명은 솔더 볼 마운팅 공정시, 미싱 볼, 브릿지 볼 및 더블 볼 현상을 방지한 반도체 패키지를 제공한다.The present invention provides a semiconductor package which prevents missing balls, bridge balls and double ball from occurring during a solder ball mounting process.

또한, 본 발명은 상기와 같이 솔더 볼 마운팅 공정시, 미싱 볼, 브릿지 볼 및 더블 볼 현상을 방지하여 그에 따른 반도체 패키지의 불량 발생 및 생산성 저하를 방지한 반도체 패키지를 제공한다.In addition, the present invention provides a semiconductor package that prevents the missing ball, bridge ball and double ball phenomenon during the solder ball mounting process as described above to prevent defects and lower productivity of the semiconductor package.

본 발명에 따른 반도체 패키지는, 기판 몸체, 상기 기판 몸체의 일면에 배치되며 본드핑거를 갖는 제1배선 및 상기 기판 몸체의 타면에 배치되며 볼 랜드를 갖는 제2배선을 포함하는 인쇄회로기판; 상기 인쇄회로기판 상에 부착된 반도체 칩; 상기 반도체 칩과 상기 인쇄회로기판 간을 전기적으로 연결하는 연결 부재; 및 상기 인쇄회로기판의 볼 랜드에 부착되며, 내부에 금속 파티클이 함유된 외부 접속 단자;를 포함한다.A semiconductor package according to the present invention includes a printed circuit board including a substrate body, a first wiring disposed on one surface of the substrate body and having a bond finger, and a second wiring disposed on the other surface of the substrate body and having a ball land; A semiconductor chip attached to the printed circuit board; A connection member electrically connecting the semiconductor chip to the printed circuit board; And an external connection terminal attached to the ball land of the printed circuit board and containing metal particles therein.

상기 볼 랜드는 표면에 영구 자석 분말이 코팅된 것을 특징으로 한다.The ball land is characterized in that the permanent magnet powder is coated on the surface.

상기 외부 접속 단자는 솔더 볼을 포함하는 것을 특징으로 한다.The external connection terminal is characterized in that it comprises a solder ball.

상기 외부 접속 단자는, 몸체를 이루며, 원 형상을 갖는 바인더(Binder); 상기 바인더 내에 함유되며, 상기 바인더에 의해 포획되는 금속 파티클; 및 상기 바인더를 감싸는 금속막;을 포함한다.The external connection terminal comprises a binder having a body and having a circular shape; Metal particles contained in the binder and captured by the binder; And a metal film surrounding the binder.

상기 금속 파티클은 Fe을 포함하는 것을 특징으로 한다.The metal particle is characterized in that it contains Fe.

상기 금속막은 Pb를 포함하는 것을 특징으로 한다.The metal film is characterized in that it comprises Pb.

상기 본드핑거 및 볼 랜드를 노출시키도록 상기 기판 몸체의 일면 및 타면 각각에 배치된 솔더 레지스트를 더 포함하는 것을 특징으로 한다.And a solder resist disposed on each of one side and the other side of the substrate body to expose the bond fingers and the ball lands.

상기 반도체 칩과 상기 연결 부재를 포함하는 인쇄회로기판의 일면을 밀봉하는 봉지 부재를 더 포함하는 것을 특징으로 한다.And an encapsulation member for sealing one surface of the printed circuit board including the semiconductor chip and the connection member.

본 발명은 반도체 패키지 형성시 표면에 영구 자석 분말이 코팅된 볼 랜드와, 내부에 금속 파티클이 함유된 솔더 볼이 부착되어 형성됨으로써, 상기 볼 랜드와 솔더 볼 간의 부착력을 향상시킬 수 있다.In the present invention, when the semiconductor package is formed, the ball land coated with the permanent magnet powder and the solder ball containing the metal particles are attached to the surface, thereby improving adhesion between the ball land and the solder ball.

따라서, 본 발명은 솔더 볼 마운팅 공정시 발생하는 미싱 볼, 브릿지 볼 및 더블 볼 현상을 방지할 수 있으므로, 전체 반도체 패키지의 불량 발생을 방지할 수 있다.Therefore, the present invention can prevent the missing ball, bridge ball and double ball phenomenon occurring during the solder ball mounting process, it is possible to prevent the occurrence of defects of the entire semiconductor package.

그 결과, 본 발명은 전체 생산성 저하를 방지할 수 있다.As a result, this invention can prevent the fall of whole productivity.

이하에서는 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

도 1 내지 도 3은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도로서, 이를 설명하면 다음과 같다.1 to 3 are cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

도 1 내지 도 3에 도시된 바와 같이, 본 발명의 실시예에 따른 반도체 패키 지(150)는, 인쇄회로기판(100), 반도체 칩(122) 및 연결 부재(126)를 포함한다.1 to 3, a semiconductor package 150 according to an embodiment of the present invention includes a printed circuit board 100, a semiconductor chip 122, and a connection member 126.

인쇄회로기판(100)은, 기판 몸체(110). 제1배선(112a) 및 제2배선(112b)을 포함한다.The printed circuit board 100 includes a substrate body 110. The first wiring 112a and the second wiring 112b are included.

기판 몸체(110)는 제1절연층(102), 금속막(104), 비아 배선(106) 및 제2절연층(108)을 포함한다.The substrate body 110 includes a first insulating layer 102, a metal film 104, a via wiring 106, and a second insulating layer 108.

제1절연층(102)은 기판 몸체(110)를 이루며 예를 들면 코어층으로 이루어진다.The first insulating layer 102 forms the substrate body 110 and is formed of, for example, a core layer.

금속막(104)은 이러한 코어층으로 이루어진 제1절연층(102)의 일면에 배치되며, 이러한 금속막(104)은 예를 들면 구리막으로 이루어진다.The metal film 104 is disposed on one surface of the first insulating layer 102 made of such a core layer, and the metal film 104 is made of, for example, a copper film.

비아 배선(106)은 제2절연층(108)의 내부에 다수 개 배치되어, 제1절연층(102) 일면에 배치된 금속막(104)과 제2절연층(108) 상부의 제1 및 제2배선(112a, 112b) 간을 전기적으로 접속시킨다.The plurality of via wires 106 are disposed inside the second insulating layer 108, and the first and second upper portions of the metal film 104 and the second insulating layer 108 disposed on one surface of the first insulating layer 102. The second wirings 112a and 112b are electrically connected to each other.

제1배선(112a)은 이러한 이러한 제1절연층(102), 금속막(104), 비아 배선(106) 및 제2절연층(108)을 포함하는 기판 몸체(110)의 일면에 배치되며, 본드핑거(114)를 갖는다.The first wiring 112a is disposed on one surface of the substrate body 110 including the first insulating layer 102, the metal film 104, the via wiring 106, and the second insulating layer 108. It has a bond finger 114.

제2배선(112b)은 이러한 이러한 제1절연층(102), 금속막(104), 비아 배선(106) 및 제2절연층(108)을 포함하는 기판 몸체(110)의 타면에 배치되며, 볼 랜드(116)를 갖는다.The second wiring 112b is disposed on the other surface of the substrate body 110 including the first insulating layer 102, the metal film 104, the via wiring 106, and the second insulating layer 108. It has a ball land 116.

이때, 볼 랜드(116)는 표면에 영구 자석 분말(120)이 코팅된다.At this time, the ball land 116 is coated with a permanent magnet powder 120 on the surface.

또한, 인쇄회로기판(110)은 솔더 레지스트(118)를 더 포함하며, 이러한 솔더 레지스트(118)는 제1 및 제2배선(112a, 112b)의 본드핑거(114) 및 볼 랜드(116) 부분을 노출시키도록 기판 몸체(110)의 일면 및 타면에 각각 배치된다.In addition, the printed circuit board 110 further includes a solder resist 118, which is a portion of the bond finger 114 and the ball land 116 of the first and second wirings 112a and 112b. It is disposed on one surface and the other surface of the substrate body 110 to expose the.

반도체 칩(122)은 이러한 인쇄회로기판(100)의 일면에 배치되며 다수의 본딩패드(124)를 갖는다.The semiconductor chip 122 is disposed on one surface of the printed circuit board 100 and has a plurality of bonding pads 124.

연결 부재(126)는 이러한 반도체 칩(122)의 본딩패드(124)와 인쇄회로기판(100)의 본드핑거(114) 간을 전기적으로 연결한다. 이러한 연결 부재(126)는 예를 들면 와이어를 포함한다.The connection member 126 electrically connects the bonding pad 124 of the semiconductor chip 122 and the bond finger 114 of the printed circuit board 100. This connecting member 126 comprises a wire, for example.

또한, 본 발명의 실시예에 따른 반도체 패키지(150)는, 실장수단으로서 외부 접속 단자(130)를 더 포함하며, 이러한 외부 접속 단자(130)는 인쇄회로기판(100)의 볼 랜드(116)에 부착된다.In addition, the semiconductor package 150 according to the embodiment of the present invention further includes an external connection terminal 130 as a mounting means, the external connection terminal 130 is a ball land 116 of the printed circuit board 100 Is attached to.

이때, 외부 접속 단자(130)는 도 3에 도시된 바와 같이 바인더(Binder : 132), 금속 파티클(134) 및 금속막(136)으로 이루어진 솔더 볼을 포함한다.In this case, as illustrated in FIG. 3, the external connection terminal 130 includes a solder ball including a binder 132, a metal particle 134, and a metal layer 136.

바인더(132)는 이러한 외부 접속 단자(130)의 몸체를 이루며, 예를 들면 원 형상을 갖는 코어로 이루어진다.The binder 132 forms a body of the external connection terminal 130 and is formed of, for example, a core having a circular shape.

금속 파티클(134)은 이러한 바인더(132) 내에 다수 개 함유되며, 이러한 바인더(132)에 의해 포획된다. 이러한 금속 파티클(134)은 예를 들면 Fe을 포함한다.A large number of metal particles 134 are contained in the binder 132 and are captured by the binder 132. Such metal particles 134 include Fe, for example.

금속막(136)은 이러한 Fe로 이루어진 포함 금속 파티클(134)이 함유된 바인더(132)를 외부에서 감싸도록 배치된다. 이러한 금속막(134)은 예를 들면 Pb를 포함한다.The metal film 136 is disposed to surround the binder 132 containing the containing metal particles 134 made of Fe from the outside. The metal film 134 includes Pb, for example.

이 경우, 본 발명은 상기와 같이 인쇄회로기판(100)의 볼 랜드(116) 표면에 코팅된 영구 자석 분말(120) 및 외부 접속 단자(130) 내에 함유된 금속 파티클(134)에 의해 외부 접속 단자(130)가 볼 랜드에 부착시, 그의 부착력을 종래 보다 향상시킬 수 있다.In this case, the present invention is externally connected by the permanent magnet powder 120 coated on the surface of the ball land 116 of the printed circuit board 100 and the metal particles 134 contained in the external connection terminal 130. When the terminal 130 is attached to the ball land, its adhesion can be improved more than before.

또한, 본 발명의 실시예에 따른 반도체 패키지(150)는, 반도체 칩(122)을 외부의 스트레스로부터 보호하기 위해 이러한 반도체 칩(122)과 연결 부재(126)를 포함하는 인쇄회로기판(100)의 일면을 밀봉하는 봉지 부재(128)를 더 포함한다.In addition, the semiconductor package 150 according to the embodiment of the present invention, the printed circuit board 100 including the semiconductor chip 122 and the connection member 126 to protect the semiconductor chip 122 from external stress. The sealing member 128 further includes a sealing member.

이러한 봉지 부재(128)는 예를 들면 EMC(Epoxy Molding Compound)로 이루어진다.The encapsulation member 128 is made of, for example, an epoxy molding compound (EMC).

전술한 바와 같이 본 발명은, 표면에 영구 자석 분말이 코팅된 볼 랜드와, 내부에 금속 파티클이 함유된 솔더 볼 간이 부착되어 반도체 패키지가 형성됨으로써, 상기 볼 랜드와 솔더 볼 간의 부착력을 향상시킬 수 있다.As described above, in the present invention, the ball land coated with the permanent magnet powder and the solder ball containing the metal particles are attached to the surface to form a semiconductor package, thereby improving adhesion between the ball land and the solder ball. have.

따라서, 상기와 같이 볼 랜드와 솔더 볼 간의 부착력을 향상시킬 수 있으므로, 종래의 솔더 볼 마운트 공정시, 솔더 볼을 정확하게 부착하기가 점점 어려워짐에 따라 유발되는 미싱(Missing) 볼, 브릿지(Bridge) 볼 및 더블(Double) 볼 현상의 발생을 방지할 수 있다.Therefore, as described above, the adhesion between the ball land and the solder ball can be improved, and thus, a missing ball or bridge caused by the difficulty in attaching the solder ball accurately in the conventional solder ball mounting process is caused. The occurrence of balls and double balls can be prevented.

따라서, 전체 반도체 패키지에서의 불량 발생을 방지할 수 있으므로, 전체 생산성 저하를 방지할 수 있다.Therefore, it is possible to prevent the occurrence of defects in the entire semiconductor package, it is possible to prevent the reduction in overall productivity.

이상, 전술한 본 발명의 실시예들에서는 특정 실시예에 관련하고 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.In the above-described embodiments of the present invention, the present invention has been described and described with reference to specific embodiments, but the present invention is not limited thereto, and the scope of the following claims is not limited to the scope of the present invention. It will be readily apparent to those skilled in the art that the present invention may be variously modified and modified.

도 1 내지 도 3은 본 발명의 실시예에 따른 반도체 패키지를 설명하기 위해 도시한 단면도.1 to 3 are cross-sectional views illustrating a semiconductor package according to an embodiment of the present invention.

Claims (8)

기판 몸체, 상기 기판 몸체의 일면에 배치되며 본드핑거를 갖는 제1배선 및 상기 기판 몸체의 타면에 배치되며 볼 랜드를 갖는 제2배선을 포함하는 인쇄회로기판;A printed circuit board comprising a substrate body, a first wiring disposed on one surface of the substrate body and having a bond finger, and a second wiring disposed on the other surface of the substrate body and having a ball land; 상기 인쇄회로기판 상에 부착된 반도체 칩; A semiconductor chip attached to the printed circuit board; 상기 반도체 칩과 상기 인쇄회로기판 간을 전기적으로 연결하는 연결 부재; 및A connection member electrically connecting the semiconductor chip to the printed circuit board; And 상기 인쇄회로기판의 볼 랜드에 부착되며, 내부에 금속 파티클이 함유된 외부 접속 단자;An external connection terminal attached to a ball land of the printed circuit board and containing metal particles therein; 를 포함하는 것을 특징으로 하는 반도체 패키지.Semiconductor package comprising a. 제 1 항에 있어서,The method of claim 1, 상기 볼 랜드는 표면에 영구 자석 분말이 코팅된 것을 특징으로 하는 반도체 패키지.The ball land is a semiconductor package, characterized in that the permanent magnet powder is coated on the surface. 제 1 항에 있어서,The method of claim 1, 상기 외부 접속 단자는 솔더 볼을 포함하는 것을 특징으로 하는 반도체 패키지.The external connection terminal comprises a solder ball, characterized in that the semiconductor package. 제 1 항에 있어서,The method of claim 1, 상기 외부 접속 단자는, The external connection terminal, 몸체를 이루며, 원 형상을 갖는 바인더(Binder);A binder forming a body and having a circular shape; 상기 바인더 내에 함유되며, 상기 바인더에 의해 포획되는 금속 파티클; 및Metal particles contained in the binder and captured by the binder; And 상기 바인더를 감싸는 금속막;A metal film surrounding the binder; 을 포함하는 것을 특징으로 하는 반도체 패키지.A semiconductor package comprising a. 제 4 항에 있어서,The method of claim 4, wherein 상기 금속 파티클은 Fe을 포함하는 것을 특징으로 하는 반도체 패키지.The metal particle is a semiconductor package, characterized in that containing Fe. 제 4 항에 있어서,The method of claim 4, wherein 상기 금속막은 Pb를 포함하는 것을 특징으로 하는 반도체 패키지.The metal film comprises a Pb. 제 1 항에 있어서,The method of claim 1, 상기 본드핑거 및 볼 랜드를 노출시키도록 상기 기판 몸체의 일면 및 타면 각각에 배치된 솔더 레지스트를 더 포함하는 것을 특징으로 하는 반도체 패키지.And a solder resist disposed on each of one side and the other side of the substrate body to expose the bond fingers and the ball lands. 제 1 항에 있어서,The method of claim 1, 상기 반도체 칩과 상기 연결 부재를 포함하는 인쇄회로기판의 일면을 밀봉하는 봉지 부재를 더 포함하는 것을 특징으로 하는 반도체 패키지.And a sealing member for sealing one surface of the printed circuit board including the semiconductor chip and the connection member.
KR1020080125462A 2008-12-10 2008-12-10 Semiconductor package KR20100066939A (en)

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