KR20100064481A - Driving method of memory device for reduceing coupling effect between memory cells, and memory device having the same - Google Patents

Abstract

PURPOSE: A memory device and a method for driving the same are provided to prevent the disturbance of a program by boosting a cell which is prohibited to be programmed with high power. CONSTITUTION: A semiconductor system(200) includes a memory device and a processor(220). The processor controls the writing operation, the reading operation or the verifying-reading operation of the semiconductor device. A timing controller performs the verifying-reading operation or a program operation in response with control signal from the processor. A battery(250) supplies operational power to the memory device and the processor. An input-output device provides interface with an external data process device for transmitting and receiving data.

Description

Driving method of a memory device capable of reducing coupling between memory cells, and a memory device including the same {Driving method of memory device for reducing coupling effect between memory cells, and memory device having the same}

An embodiment of the present invention relates to a memory device, and more particularly, to a method of driving a memory device capable of reducing coupling between memory cells during a program operation, and a memory device including the same.

Nonvolatile semiconductor devices have the advantage of being capable of electrically erasing and storing data and preserving data even when power is not supplied. Therefore, the non-volatile semiconductor device has recently been expanded in various fields.

Such nonvolatile semiconductor devices are classified into NAND type memory devices and NOR type memory devices according to the structure of the memory cell array. These nonvolatile semiconductor devices have advantages and disadvantages that are classified into high integration and high speed. Therefore, the use in the application where each advantage is highlighted is increasing trend.

With the development of the process technology, the size of the semiconductor device, that is, the memory cell constituting the memory device, and the separation distance between the memory cells are decreasing. As a result, parasitic capacitance and coupling effects existing between the bit lines are increasing to an undeniable level. Due to such a problem, the memory device may cause a malfunction because the window margin of the memory cell is reduced to determine the exact data.

In particular, as the memory device increases in density, the capacity of the parasitic capacitors between the pairs of bit lines increases, causing a slowing of the sensing margin due to the coupling phenomenon between them.

Accordingly, a memory device capable of reducing the coupling phenomenon between memory cells is required.

SUMMARY An object of the present invention is to provide a method of driving a memory device capable of reducing coupling between adjacent memory cells and a memory device including the same.

According to an embodiment of the present disclosure, a method of driving a memory device may include preset setting each of cells to be programmed and each of cells to be program-prohibited to a program prohibition state during a program operation, and each of the cells to be programmed and the program prohibition. (B) programming each of the cells to be programmed according to the program data.

(a) precharging, during the precharge operation, precharging each first bit line connected to each of the cells to be programmed and each second bit line connected to each of the cells to be prohibited to a first voltage; Presetting each of the cells to be programmed and each of the cells to be program inhibited to the program inhibited state in response to a program pass voltage supplied to each selected word line to which each of the cells to be programmed and each of the cells to be program inhibited are connected; It may include.

(b) discharging the voltage of each of the first bit lines precharged to the first voltage to ground voltage according to the program data, and responsive to a program voltage supplied to each of the selected word lines. Programming each of the cells to be programmed.

In addition, the memory device according to an embodiment of the present disclosure may include a first bit line connected to each of the cells to be programmed, a second bit line connected to each of the cells to be prohibited, and a cell to be programmed during a program operation. And a driving circuit for programming each of the cells to be programmed and each of the cells to be program inhibited according to program data after presetting each and each of the cells to be program inhibited to a program inhibit state.

In a driving method of a memory device according to an exemplary embodiment of the present invention, a program data is boosted by boosting channel voltages of all memory cells, regardless of whether a neighboring memory cell is a cell to be programmed or a cell to be programmed during a program operation, and then program data. According to the present invention, when the programs are selectively programmed in each of the memory cells, coupling between adjacent cells is reduced, and thus, program disturb is prevented by boosting a cell to be prohibited to a high voltage.

In addition, the memory device driving method according to an embodiment of the present invention can secure a window margin for a cell to be prohibited from program during a program operation, thereby stably performing a program operation.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a schematic block diagram of a memory device according to an embodiment of the present invention. Referring to FIG. 1, the memory device 100 includes a memory cell block 110, a low decoder 130, a timing controller T / G 140, a voltage generator 150, and a page buffer 160.

The memory cell block 110 includes a plurality of memory cell arrays 10.

The memory cell array 10 includes a plurality of bit lines BLj (j = 0 to m), a plurality of word lines WL0 to WLn, a string selecting line SSL, and a ground selecting line. Line (GSL), Common Source Line (CSL), String Selecting Transistor (SST), Ground Selecting Transistor (GST), and a plurality of memory cells MC0 to MCn. do.

The string select transistor SST is connected to the corresponding bit lines BLi and i = 0 to m, respectively, and is controlled through the string select line SSL, and the ground select transistor GST is connected to the common source line CSL. ) Is controlled via the ground select line (GSL).

Each of the plurality of word lines WL0 to WLn is connected to a gate of each of the plurality of memory cells MC0 to MCn, and applies a control voltage to each corresponding memory cell.

The plurality of memory cells MC0 to MCn are connected in series between the string select transistor SST and the ground select transistor GST to form one string. For example, the number n + 1 of the memory cells MC0 to MCn forming one string may be 16, 32, or 64 depending on the device, but the present invention is not limited thereto.

Here, the memory device 100 may read or program data in page units for each of the plurality of memory cells connected to the selected word line.

The row decoder 130 is connected to the memory cell block 110 through the plurality of word lines WL0 to WLn and is a block for selecting a plurality of memory cells connected to one word line based on an address signal. Generates an enable signal. The block enable signal is commonly applied to the gates of each of the plurality of select transistors SST through the string select line SSL. Each of the select transistors is turned on in response to a block enable signal, so that voltages output from the voltage generator 150 are transferred to the plurality of word lines WL0 to WLn, the string selection line SSL, and the ground selection line GSL. To be authorized.

In addition, the row decoder 130 generates a control signal BS1 for controlling the operation of the power supply control circuit 180 based on the address signal.

The voltage generator 150 generates a plurality of voltages required when programming, erasing, and reading the plurality of memory cells. Each of the plurality of voltages may include a read voltage, a program voltage Vpgm, and a program pass voltage Vpass.

The timing controller T / G 140 controls the operation of at least one of the memory cell block 110, the row decoder 130, the timing controller 140, the voltage generator 150, and the page buffer 160. Generate at least one control signal for the device. For example, the timing controller 140 generates the first precharge signal PRE1 and the second precharge signal PRE2 for controlling the operation of the precharge circuit 170 of the page buffer. Here, the first precharge signal PRE1 is a signal for supplying the first voltage Vcc to a corresponding bit line among the plurality of bit lines, and the second precharge signal PRE2 is among the plurality of bit lines. This signal is for supplying the ground voltage Vss to the corresponding bit line. At this time, after the logic of the first precharge signal PRE1 transitions, the logic of the second precharge signal PRE2 transitions.

The page buffer 160 is connected to the memory cell block 110 through a plurality of bit lines BL0 to BLm, and includes a power supply control circuit 180 and a precharge circuit 170.

The precharge circuit 170 may output one of the first voltage Vcc and the ground voltage Vss in response to any one of the plurality of precharge signals PRE1 and PRE2.

The power supply control circuit 180 is connected to the memory cell array 110 through the plurality of bit lines BL0 to BLn, and the plurality of bit lines in response to the control signal BS1 output from the row decoder 130. At least one of the bit lines B i and i = 0 to m is selected.

The power supply control circuit 180 may precharge the first bit line to which the cell to be programmed and the precharge circuit 170 and / or the second bit line to which the cell to be programmed is connected in response to the control signal BS1. The circuits 170 may be electrically connected to each other.

For example, the power supply control circuit 180 forms a current path between the first bit line to which the cell to be programmed and the precharge circuit 170 are connected in response to the control signal BS1, thereby forming the current of the precharge circuit 170. An output voltage may be supplied to the first bit line.

In addition, the power supply control circuit 180 forms a current path between the precharge circuit 170 and the second bit line to which the cell to be prohibited is connected in response to the control signal BS1, thereby precharging the circuit 170. The output voltage of may be supplied to the second bit line.

Although the power supply control circuit 180 is implemented as part of the page buffer 160 in the embodiment of the present invention, the present invention is not limited thereto, and the power supply control circuit 180 may include at least one of the nonvolatile memory device 100. It can be implemented as part.

2 is a diagram illustrating a coupling phenomenon between memory cells in a general memory device. For convenience of description, three memory cells connected to one word line will be described as an example.

During a program operation, the memory device 100 applies a program voltage Vpgm to a selected word line, and applies a voltage of 0 V to a bit line of the cell to be programmed, thereby providing a gap between the channel region of the cell transistor and the control gate CF. The electrons in the channel region are injected into the floating gate FG by FN tunneling due to a high voltage difference of. Here, each of the plurality of memory cells connected to the selected word line may be divided into a cell to be programmed and a cell to be prohibited.

At this time, as the program voltage Vpgm is applied not only to the cell to be programmed but also to the cells to be program inhibited, the memory device 100 is connected to a bit line to which the cell to be program inhibited is programmed in order to prevent the cells to be programmed. By applying a high voltage (eg, a first voltage Vcc) to boost the channel voltage of the cell to be program inhibited, it is possible to prevent program disturb in which unwanted memory cells are programmed.

In general, however, in a nonvolatile memory device, when a program operation is performed, a coupling phenomenon occurs in which charges stored in the floating gate FG of the memory cell move to adjacent memory cells, and a program disturb may occur due to the coupling phenomenon. have.

That is, as shown in FIG. 2, parasitic capacitors Ccc, Ccf, Cg, Cf, and Cd exist between all adjacent memory cells, and the parasitic capacitors Ccc, Ccf, Cg, Cf, and Cd during a program operation. The leakage current flowing through each of the plurality of channels) lowers the channel voltage Vch for boosting the cell to be program inhibited, and as a result, the cell to be program inhibited can be program disturbed.

This coupling phenomenon is caused by the increase in the leakage current flowing through each of the parasitic capacitors Ccc, Ccf, Cg, Cf, and Cd as the voltage difference between the cell to be program inhibited and the bit line pair of the adjacent cell increases. The channel voltage Vch of is lowered.

3 is a timing diagram illustrating a change in channel voltage of a cell to be programmed prohibited in a general memory device, and FIGS. 4A and 4B illustrate a program inhibited boosting according to data of adjacent cells in a general memory device. It is a figure for explaining the channel voltage of the cell to be.

In the precharge operation (t6), the precharge circuit precharges the first bit line to which the cell to be programmed is precharged to the ground voltage (0V) according to the data of each of the memory cells, and the second bit to which the cell to be programmed prohibited is connected. The line is precharged to the first voltage Vcc.

When a voltage is applied to the string select line SSL (t7), each of the plurality of string select transistors SST is turned on to each of the plurality of memory cells connected to the corresponding bit line. As a voltage is applied, a channel region of each of the plurality of memory cells is boosted to a predetermined voltage (Vcc-Vth).

Thereafter, in the program operation, the program pass voltage Vpass is first applied to each of the selected word line WLn-1 and the non-selected word line Others WLs (t8), and then the selected word line passes after a predetermined time. The program voltage Vpgm (for example, Vpgm = 9V) is applied only to WLn-1 (t9). In this case, the channel voltage Vch of a cell to be program inhibited may vary according to program data of an adjacent cell. That is, as the current of the channel region of the cell to be program inhibited boosted to the high voltage flows through the parasitic capacitor Ccc to the adjacent cell, that is, the channel region of the cell to be programmed, the channel voltage Vch of the cell to be program inhibited is reduced. Can be.

As shown in Fig. 4A, when programming data '010', i.e., all cells adjacent to a cell to be programmed inhibited are cells to be programmed, a voltage between the channel region of the cell to be programmed prohibited and the channel region of the cell to be programmed. Since the difference is large, the leakage current flowing through the parasitic capacitor Ccc between the adjacent cells due to the coupling phenomenon is greatest. Therefore, the channel voltage (Vch = 9V) of the cell to be boosted program inhibited may be reduced to a predetermined voltage by 6V due to this leakage current.

As shown in FIG. 4B, when data '111' is programmed, that is, when all cells adjacent to a cell to be program-prohibited are cells to be program-prohibited, the channel region of the adjacent cells is also high voltage like the channel region of the cell to be prohibited. For example, by boosting to 9V, there is little leakage current flowing through the parasitic capacitor Ccc between adjacent cells. Therefore, it is possible to maintain the channel voltage (Vch = 9V) of the cell to be program inhibited to be boosted without being influenced by the adjacent cells. .

As described above, in the conventional memory device, the program disturb may easily occur because the amount of change in the channel voltage Vch of the cell to be prohibited according to the data of the adjacent cell is large. In addition, due to such a coupling phenomenon, the channel voltage Vch of a cell to be prohibited to be boosted during a program operation may cause data of adjacent memory cells (for example, data "1" or data "0") to be programmed. By decreasing according to whether the cell is to be prohibited or programmed, the window margin of the channel voltage Vch of the cell to be program inhibited is reduced.

FIG. 5 is a timing diagram illustrating a change in channel voltage of a cell to be prohibited from program generation during a program operation according to an exemplary embodiment of the present disclosure.

The precharge circuit 170 outputs the first voltage VSS in response to the first precharge signal PRE1 output from the timing controller 140, and the power supply control circuit 180 supplies the control signal BS1. In response, the signal is turned on to precharge each of the plurality of bit lines BLi and i to be a first voltage. That is, each first bit line connected to each of the programmed cells and each second bit line connected to each of the programmed inhibited cells are precharged to the first voltage Vcc. .

When a voltage is applied to the string select line SSL (t1), each of the string select transistors SST is turned on to each of the plurality of memory cells connected to the corresponding bit line. Apply voltage. That is, the first voltage Vcc is applied to each of the plurality of memory cells MC0 to MCn connected to the first bit line and the plurality of memory cells MC0 to MCn connected to the second bit line. The channel region of each of the memory cells MC0 to MCn in is boosted to a predetermined voltage (eg, Vcc-Vth).

Thereafter, when a program pass voltage Vpss output from the row decoder 130 is applied to the selected word line (t2), each of the cells to be programmed connected to the first bit line and the program inhibit connected to the second bit line are prohibited. Each of the cells to be boosted by the first channel voltage V1.

As described above, the memory device 100 according to the embodiment of the present invention has a high voltage, for example, a first voltage Vcc, on a plurality of memory cells connected to a selected word line, that is, a cell to be programmed prohibited and a bit line of each cell to be programmed. Is applied, and a program pass voltage Vpass is applied to the selected word line. Accordingly, each of the plurality of memory cells is preset to a program prohibition state regardless of program data.

After a predetermined time, the precharge circuit 170 outputs the ground voltage Vss = 0V in response to the second precharge signal PRE2, and the power supply control circuit 180 controls the control signal BS1. In response, a current path is formed between the first bit line and the output node ND1 among the plurality of bit lines BLi and i are integers. Accordingly, the voltage of the first bit line pulled up to the first voltage Vcc is discharged to the ground voltage OV. In this case, each second bit line connected to each of the programmed inhibited cells maintains the voltage of the second bit line pulled up to the first voltage Vcc.

When the voltage of the first bit line is discharged to the ground voltage Vss (t3), the program boosted to the first channel voltage a by the coupling phenomenon between the first bit line and the second bit line is prohibited. The channel voltage Vch of the cell decreases. That is, the channel voltage Vch of the cell to be prohibited due to leakage current generated between the second bit line pulled up to the first voltage Vcc and the first bit line pulled down to the ground voltage Vss is The second channel voltage V2 is lower than the first channel voltage V1.

When the above voltages are applied to the memory cell, the program voltage Vpgm is applied to the control gate of the cell to be program inhibited, but the channel region has the program voltage Vpgm, the program pass voltage Vpass, and the voltage of the bit line. The channel region of the cell to be program inhibited is boosted by the voltage ratio due to the inter coupling phenomenon.

In the conventional memory device, as the program voltage Vpgm is applied while the first bit line is pulled down to the ground voltage and the second bit line is pulled up to the first voltage Vcc, the program voltage Vpgm Since the voltage difference between the voltages of the bit lines is large, the amount of change in the channel voltage of a cell to be program inhibited that is boosted according to data of adjacent cells is large. Accordingly, the boosted channel voltage (Vch = 6V) of the cell to be programmed inhibited reduced due to the influence of the neighboring cell when the adjacent cells are to be programmed inhibited and the boosted channel voltage of the cell to be programmed prohibited when the neighboring cells are cells to be programmed. The window margin was small due to the difference (Vch = 9V).

However, in the memory device 100 according to an embodiment of the present disclosure, as the program voltage Vpgm is applied while the first bit line and the second bit line are pulled up to the first voltage Vcc, the program voltage Vpgm is applied. ), As the voltage difference between the bit lines decreases, coupling between adjacent cells is reduced as compared with the conventional memory device. Therefore, the channel voltage Vch of the cell to be program inhibited may be boosted to a high channel voltage regardless of the data of the adjacent cell.

In addition, when the cell adjacent to the cell to be program inhibited is the cell to be program inhibited, the first bit line maintains the pull-up state to the first voltage Vcc, so that the channel voltage Vch of the cell to be program inhibited is the first channel. Maintain the voltage V1.

Then, when the program pass voltage Vpss output from the row decoder 130 is applied to the selected word line WLn-1 (t4), each of the selected plurality of memory cells is selectively programmed according to the program data.

As described above, the memory device 100 according to an embodiment of the present invention sets a cell to be programmed prohibited and a cell to be programmed regardless of program data before performing a program operation, and then sets the program data to the program inhibited state. Accordingly, by selectively performing the program operation, the amount of change in the channel voltage Vch of the cell to be prohibited, which is reduced by the influence of the adjacent cell during the program operation, may be reduced. Therefore, there is an effect that can improve the window margin compared to the conventional memory device.

6 is a diagram illustrating a step-by-step operation of a memory device according to an embodiment of the present disclosure.

First, a program pass voltage Vpass is applied to a selected word line, and a plurality of bit lines to which a memory cell is connected, for example, a first bit line to which a cell to be programmed is connected and a second bit line to which a cell to be programmed prohibited is connected. A high voltage, for example, a first voltage Vcc is applied to each of them regardless of the program data. Accordingly, regardless of whether each of the plurality of memory cells is a cell to be programmed or a cell to be program inhibited, all of the plurality of memory cells are boosted to the first channel voltage V1 = 9V to be in a program inhibit state.

Thereafter, a voltage is selectively applied to each of the plurality of bit lines according to the program data. That is, the first voltage Vss is applied to the first bit line, and the ground voltage Vss is applied to the second bit line. As a result, the channel voltage of the cell to be prohibited due to the coupling between the first bit line and the second bit line is reduced to a second channel voltage (V2 = 8.5V) lower than the first channel voltage (V1 = 9V). .

Then, when the program voltage Vpgm is applied to the word line, the cell to be programmed is programmed by the high voltage difference between the channel region of the cell to be programmed and the control gate, and the cell to be programmed inhibited correlates with the data of the adjacent cell. Without this, the program disturb can be prevented by boosting to a high voltage, that is, the first channel voltage V1 = 9V or the second channel voltage V1 = 8.5V.

As described above, the memory device 100 according to an embodiment of the present invention boosts the channel voltages of all memory cells to a program inhibited state regardless of whether the adjacent memory cell is a cell to be programmed or a cell to be prohibited during a program operation. After fabrication, by selectively programming each of the memory cells according to program data, coupling between adjacent cells can be reduced. Therefore, the cell to be program inhibited is boosted with a high channel voltage as compared with the conventional memory device, thereby preventing program disturb.

In addition, since the memory device according to the embodiment of the present invention can secure the window margin for the cell to be prohibited from the program during the program operation, the memory device can stably perform the program operation.

7 is a schematic block diagram of a semiconductor system including a semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 7, a semiconductor system 200 such as a computer includes a memory device 100 and a processor 220 connected to a system bus 210.

The processor 220 may overall control a write operation, a read operation, or a verify read operation of the semiconductor device 200. For example, the processor 120 outputs a command and write data for controlling a write operation of the memory device 100.

In addition, the processor 220 may generate a command for controlling a read operation or a verify read operation of the memory device 100. Accordingly, the timing controller T / G 140 of the memory device 100 may perform a verification read operation or a program operation (or a write operation) in response to a control signal output from the processor 120.

If the semiconductor system 200 is implemented as a portable application, the semiconductor system 100 further includes a battery 250 for supplying operation power to the memory device 100 and the processor 220. can do.

Portable applications include portable computers, digital cameras, personal digital assistants (PDAs), cellular telephones, MP3 players, portable multimedia players (PMPs), and automotive navigation systems. , Memory cards, smart cards, game consoles, electronic dictionaries, or solid state discs.

The semiconductor system 200 may further include an interface for exchanging data with an external data processing device, such as an input / output device 130.

When the semiconductor system 200 is a wireless system, the semiconductor system 200 may further include a memory device 100, a processor 220, and a wireless interface 240. In this case, the wireless interface 240 may be connected to the processor 220 and may exchange data with an external wireless device (not shown) through the system bus 210.

For example, the processor 220 may process and store data input through the air interface 240 in the memory device 100, and may read data stored in the memory device 100 and transmit the data stored in the memory device 100 to the air interface 240. .

The wireless system may be a PDA, a portable computer, a wireless telephone, a pager, a wireless device such as a digital camera, an RFID reader, or an RFID system. The wireless system may be a wireless local area network (WLAN) system or a wireless personal area network (WPAN) system. The wireless system may also be a mobile telephone network.

When the semiconductor system 200 is an image pick-up devoce, the semiconductor system 200 may further include an image sensor 260 capable of converting an optical signal into an electrical signal. The image sensor 260 may be an image sensor using a CCD and may be a CMOS image sensor manufactured using a CMOS process. In this case, the semiconductor system 200 may be a digital camera or a mobile phone to which a digital camera is attached. In addition, the semiconductor system 200 may be a satellite system to which a camera is attached.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

 1 is a schematic block diagram of a memory device including a power supply control circuit according to an embodiment of the present invention.

2 is a diagram illustrating a coupling phenomenon between memory cells in a general memory device.

FIG. 3 is a timing diagram illustrating a change in channel voltage of a cell to be prohibited, which is generated during a program operation in a general memory device.

4A and 4B are diagrams for describing channel voltages of cells to be program inhibited that are boosted according to data of adjacent cells in a general memory device.

FIG. 5 is a timing diagram illustrating a change in channel voltage of a cell to be prohibited from being generated during a program operation according to an exemplary embodiment of the present invention.

FIG. 6 is a diagram illustrating a coupling phenomenon between memory cells in a memory device according to example embodiments of the inventive concept.

7 is a schematic block diagram of a semiconductor system including a semiconductor device according to an embodiment of the present disclosure.

Claims (4)

(A) pre-setting each of the cells to be programmed and each of the cells to be program inhibited to a program inhibited state during a program operation; And (B) programming each of the cells to be programmed and each of the cells to be programmed prohibited according to program data. The method of claim 1, wherein step (a) During a precharge operation, precharging each first bit line connected to each of the cells to be programmed and each second bit line connected to each of the cells to be program inhibited with a first voltage; And Presetting each of the cells to be programmed and each of the cells to be program inhibited to the program inhibited state in response to a program pass voltage supplied to each selected word line to which each of the cells to be programmed and each of the cells to be program inhibited are connected; And driving the memory device. The method of claim 1, wherein step (b) comprises: Discharging the voltage of each of the first bit lines precharged to the first voltage according to the program data to a ground voltage; And Programming each of the cells to be programmed in response to a program voltage supplied to each of the selected word lines. A first bit line connected to each of the cells to be programmed; A respective second bit line connected to each of the cells to be program inhibited; And A memory including a driving circuit for programming each of the cells to be programmed and each of the cells to be program-prohibited to a program prohibit state in advance during a program operation, and then programming each of the cells to be programmed and each of the cells to be program-prohibited according to program data Device.

Images