KR20100063409A - Method for manufacturing wafer improved in nanotopography - Google Patents

Abstract

PURPOSE: A manufacturing method of a wafer improved a nanotopography is provided to omit a BTP process of improving the nanotopography by eliminating micro-bending by an etching existing on a wafer back side in a polishing process. CONSTITUTION: A slicing process for thinly cutting ingot to a wafer shape is operated. A lapping process for mechanically training both sides of the wafer cutting is operated. An etching process for eliminating a faulty and a damage caused by the lapping is operated. A polishing process for polishing the surface of the wafer is operated. The etching process is composed of an alkali etching process by an alkaline solution. The execution result(b) is much better than comparison example(a).

Description

Method for manufacturing wafer improved in nanotopography

The present invention relates to a method for manufacturing a wafer, and more particularly, to a wafer manufacturing method capable of improving nanotopography of a wafer.

Wafers, such as single crystal silicon wafers, which are raw materials for manufacturing semiconductor devices, etc., are largely manufactured through a shaping process, a polishing process, and a cleaning process, and further selectively grow the epitaxial layer. Can be done. The shaping process is again a slicing process in which single crystals in the ingot form are cut into wafer forms, and a lapping process in which the wafers are mechanically polished to remove defects caused by the slicing process and to control thickness and flatness. It can be subdivided into the etching process etc. which chemically remove the defect resulting from a process and a lapping process.

On the other hand, since the physical properties and the quality of the wafer directly affects the quality, quantity, and defects of the semiconductor device manufactured from the wafer, semiconductor device manufacturers are increasingly demanding strict quality for various items. One of such quality items has recently emerged as nanotopography. As shown in FIG. 1, nanotopography 20 is a surface determinant present in the intermediate region between wafer flatness 10 and surface roughness 30, and is sensitive to fine bending of the wafer. It is also a factor by which the quality characteristics are determined. In the recent semiconductor process, the importance of nanotopography is gradually increasing, and studies on new methods and studies on various methods of controlling fine bending of a wafer are being conducted.

However, the factors affecting nanotopography and the principles of control or improvement of nanotopography are not clearly known yet, and the polishing process and the grinding process are being discussed. On the other hand, Patent Application Publication No. 10-2005-51296, which is a prior application by the present applicant, proposes a wafer manufacturing method that improves the nanotopography by taking advantage of the respective advantages by performing the alkaline etching and acid etching in succession have.

However, in spite of the above prior arts, the recent semiconductor devices require higher quality for wafers, especially for nanotopography, as the degree of integration is further increased. As a result, the degree of improvement of the nanotopography according to the prior art becomes difficult to satisfy even higher quality requirements.

The present invention has been made to solve the above problems, and it is to provide a method capable of manufacturing a wafer further improved nanotopography.

Other objects and advantages of the present invention can be understood by the following description, and will be more clearly understood by the embodiments of the present invention. Also, it will be readily appreciated that the objects and advantages of the present invention may be realized by the means and combinations thereof indicated in the claims.

In order to achieve the above object, the present inventors have completed the present invention by recognizing that configuring the above etching process only by alkaline etching can significantly improve the nanotopography of the wafer.

That is, a method of manufacturing a nitride semiconductor substrate according to one aspect of the present invention, a method for manufacturing a wafer from an ingot, a slicing step of cutting the ingot thinly in the form of a wafer; A lapping process of mechanically polishing both sides of the cut wafer; An etching step of removing defects and damages caused by the lapping step; And a polishing step of polishing the surface of the wafer, wherein the etching step comprises only an alkaline etching step with an alkaline solution.

Here, the alkaline solution may be used NaOH solution, it is preferable that the ratio of NaOH in this NaOH solution is 40 to 50% by weight.

Moreover, it is preferable to maintain the temperature of alkaline solution at 75-85 degreeC during the said alkali etching process.

Furthermore, according to the present invention, in the polishing process, the BTP (Backside Touch Polishing) process of removing fine bends due to etching present on the back surface of the wafer to improve nanotopography may not be performed.

According to the present invention, the nanotopography of the wafer can be remarkably improved only by alkali etching, without performing acid etching, which is considered to be essential. Furthermore, according to the present invention, the BTP process which is generally performed in the past can be omitted. Therefore, according to the present invention, it is possible to save time and money by reducing the process, and to provide a more environmentally friendly process by reducing the use of chemicals (acid etching solution).

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in this specification and claims should not be construed as being limited to the common or dictionary meanings, and the inventors should properly explain the concept of terms in order to best describe their invention. Based on the principle that can be defined, it should be interpreted as meaning and concept corresponding to the technical idea of the present invention. Therefore, the embodiments described in the specification and the drawings shown in the drawings are only the most preferred embodiment of the present invention and do not represent all of the technical idea of the present invention, various modifications that can be replaced at the time of the present application It should be understood that there may be equivalents and variations.

The wafer manufacturing method according to the present invention includes a slicing process, a lapping process, an etching process, and a polishing process. In addition, in some cases, a grinding process may be added between the etching process and the polishing process to remove defects caused by the etching process and to control flatness, and further, a process of growing an epitaxial layer on the wafer surface. It can also be done with Furthermore, a process of cleaning the wafer is inserted between the respective processes.

Meanwhile, the present invention is mainly characterized by a process for improving nanotopography, that is, an etching process, and thus mainly describes the etching process and omits description of other processes. Other processes that omit this description can be carried out according to methods well known in the art.

In the present invention, as described above, the etching step performed to remove defects and damages due to lapping after the lapping step comprises only an alkaline etching step with an alkaline solution.

Specifically, the alkaline solution uses a NaOH solution, the NaOH solution in the NaOH solution is 40 to 50% by weight, more preferably 48% by weight. In addition, it is preferable to maintain the temperature of the NaOH solution at 75 to 85 ° C during the alkali etching process.

The temperature and proportion of this NaOH solution affects the etch rate, which affects the thickness control of the wafer removed by etching. That is, the higher the ratio of NaOH and the higher the temperature of the NaOH solution, the faster the etching rate, but it is difficult to finely control the thickness removed. Therefore, it should be appropriately adjusted according to the thickness and allowable deviation of the wafer to be removed by alkali etching. According to the experiments of the present inventors, the NaOH ratio and the solution temperature in the above-described range are appropriate.

On the other hand, the thickness of the wafer to be removed in the alkaline etching process is a range of 15 to 25 ㎛ is appropriate depending on the product specifications.

Next, the experimental example and the result which were performed in order to confirm the effect of this invention are demonstrated.

First, an embodiment in which the etching process is configured by only alkaline etching according to the present invention described above, and a comparative example in which the etching process is configured by the aforementioned prior art, namely, alkali etching + acid etching (including a cleaning process in the middle) under the following conditions Was carried out.

division Example Comparative example Etching solution NaOH solution NaOH solution Mixed acid solution
(Fluoric acid, nitric acid, acetic acid) Composition (% by weight) 40-50 40-50 5 ~ 10, 30 ~ 45, 15 ~ 20 Temperature (℃) 75-85 75-85 25-35 Removal amount (thickness) (㎛) 20 ± 2 24 ± 3 7 ± 2

As shown in Table 1, the difference between the Example and the comparative example according to the present invention is that, first, in the Comparative Example, followed by alkali etching with NaOH solution, followed by a washing process and a mixed acidic solution of hydrofluoric acid, nitric acid and acetic acid (by weight ratio of 5 to 5). 10: 30 ~ 45: 15 ~ 20), the acid etching process was further performed. In addition, in the embodiment according to the present invention, the thickness of the wafer removed by the alkali etching process by the NaOH solution was reduced by about 4 μm compared with the comparative example.

After etching the wafer by the Example and Comparative Example according to the present invention under the above conditions, the backside morphology affecting the nanotopography was observed. As a result, as shown in FIG. 2, it can be seen that Example (b) according to the present invention has a smaller etched morphology size by etching than Comparative Example (a). That is, it can be seen that surface curvature and morphology are improved as a result of reducing the removal amount by etching without performing acid etching.

From these results, according to the present invention, even if the nanotopography is not performed, the BTP (Backside Touch Polishing) process, which is conventionally performed to improve nanotopography, is performed to remove fine bends due to etching present on the back surface. It can be seen that the graphics can be improved. The BTP process is to improve wafer flatness or nanotopography by polishing a small amount of the backside of the wafer (approximately 0.5 to 2 μm). The surface is usually polished by about 8 to 10 μm on the front surface where semiconductor elements are formed on the wafer. This is different from the general polishing process of mirroring. However, since the equipment and method used in the actual process, such as a polishing pad or a polishing slurry, are the same as the general polishing process, it is described here that the BTP process is included in the polishing process.

In addition, as shown in Figure 3, also in nanotopography Example (b) according to the present invention is significantly improved compared to the comparative example (a). In FIG. 3, nanotopography may be roughly compared by contrast, and the sharper the contrast, the greater the nanotopography value (that is, the worse).

The following shows the improvement effect of the nanotopography according to the Examples and Comparative Examples according to the present invention as shown in the following table.

Window size Comparative Example
Nanotopography Value Example
Nanotopography Value Improvement Improvement 2 * 2 mm ² 31.6 nm 20.4 nm 11.2 nm 35.4% 10 * 10 mm ² 80.7 nm 49.9 nm 30.8 nm 38.2%

In Table 2, the nanotopography values are divided into windows of each size (2 * 2 mm ² , 10 * 10 mm ² ), overlapped by each window, nanotopography was measured and normalized, and then the top 0.05. It means the average of the values in%.

From Table 2, it can be seen that the nanotopography is remarkably improved according to the present invention even in numerical terms.

On the other hand, it can be estimated from the above results that acid etching has a great influence on the nanotopography of the wafer in the etching process, which was confirmed as follows. That is, another comparative example in which the etching process was configured by only acid etching was performed, and nanotopography was measured. Specifically, in the comparative example described above, only acid etching was performed using a mixed acid solution of hydrofluoric acid, nitric acid, and acetic acid as the conditions of Table 1, and nanotopography was measured in the same manner as in the above-described examples and comparative examples.

As a result, the above-described Comparative Example (alkali etching + acid etching) 10 * 10 mm ² nano-topography values are described in Table 2 as being 80.6nm acid etching one another comparison example 10 * 10 mm ² compared to only perform as shown in the case of Nanotopography values were found to be about 160 nm. In other words, it can be seen that the deterioration of nanotopography by acid etching is much larger than expected. Thus, acid etching has the advantage of obtaining uniform surface roughness, but the adverse effect on nanotopography is so great that it is difficult to include acid etching in the etching process to meet the increasingly stringent requirements of nanotopography. You can check it.

Although the present invention has been described above by means of limited embodiments and drawings, the present invention is not limited thereto and will be described below by the person skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the scope of the claims.

The following drawings, which are attached to this specification, illustrate exemplary embodiments of the present invention, and together with the detailed description of the present invention serve to further understand the technical spirit of the present invention, the present invention includes matters described in such drawings. It should not be construed as limited to.

1 is a view for explaining the concept of the flatness (flatness), nanotopography (nanotopography) and surface roughness (waferness) of the wafer.

FIG. 2 is a photograph showing the results of observing backside morphology of a wafer after etching the wafer according to Examples and Comparative Examples of the present invention.

3 is a nanotopography map showing a result of measuring nanotopography after etching a wafer according to Examples and Comparative Examples of the present invention.

4 is a nanotopography map showing a result of measuring nanotopography after etching a wafer according to the comparative example and another comparative example in which the etching process is constituted only by acid etching.

Claims (6)

In the method of manufacturing a wafer from an ingot, A slicing process of cutting the ingot thinly into a wafer form; A lapping process of mechanically polishing both sides of the cut wafer; An etching step of removing defects and damages caused by the lapping step; And A polishing process for polishing the surface of the wafer, Wafer manufacturing method for improving nanotopography, characterized in that the etching process comprises only an alkaline etching process with an alkaline solution. The method of claim 1, Wafer manufacturing method for improving nanotopography, characterized in that the alkaline solution is NaOH solution. The method of claim 2, The method of manufacturing a wafer with improved nanotopography, characterized in that the ratio of NaOH in the alkaline solution is 40 to 50% by weight. The method of claim 3, The method of manufacturing a wafer with improved nanotopography, wherein the temperature of the alkaline solution is maintained at 75 to 85 ° C. during the alkali etching process. The method according to any one of claims 1 to 4, The thickness of the wafer removed in the alkali etching process is 15 to 25 ㎛ wafer manufacturing method with improved nanotopography. The method according to any one of claims 1 to 4, In the polishing process, a wafer manufacturing method for improving nanotopography, which does not perform a BTP (Backside Touch Polishing) process that removes fine bends due to the etching present on the back surface of the wafer to improve nanotopography.

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