KR20100062190A - Extensible flash memory device and control method thereof - Google Patents

Abstract

PURPOSE: An extension flash memory device and a control method thereof for deleting and adding new memory module are provided to extend the storage capacity according to the need of the user. CONSTITUTION: A board comprises a connection unit equipping one or more memory module. When the memory module installs to the connection unit, a controller(120) forms a partial mapping table about the memory module. The controller assigns the mapping table to the memory module. The controller controls the mapping table part mapping tables about one or more memory module in the connection unit.

Description

Extensible flash memory device and control method

The present invention relates to an extended flash memory device and a control method thereof.

In general, a solid state disk (SSD) is formed by soldering a plurality of memory chips to a substrate, and storage capacity does not increase or decrease. This is similar to using a 80GB mechanical hard disk at its stated capacity until the end of its life. However, unlike a mechanical hard platter, a semiconductor memory chip may add additional capacity when a slot or socket type connection device is formed on a substrate. Current SSDs overlook this feature of semiconductor memory chips.

Due to the structural characteristics of the current SSD, even if a separate connection device is formed on the substrate, it is difficult to provide a normal mapping table for the flash type memory chip constituting the SSD. The mapping table is provided to level out wear of the flash type memory chip. Since the current SSD stores the entire mapping table evenly in each memory chip, even if an additional memory chip is installed, the mapping table is mapped to the newly added memory chip. It is not easy to allocate a table.

SUMMARY OF THE INVENTION An object of the present invention is to provide an expandable flash memory device and a method of controlling the same, which can expand a storage capacity according to a user's needs.

Another object of the present invention is to provide an extended flash memory device which does not require a large change to a mapping table of a storage device when the storage capacity is changed according to a user's need, and a control method thereof.

The above object is, according to the present invention, a substrate having a connection portion for mounting at least one memory module, and when the memory module is mounted to the connection portion, forming a partial mapping table for the mounted memory module, the formed portion This is accomplished by a control unit which assigns a mapping table to the mounted memory module.

According to the present invention, the above object is achieved by forming a partial mapping table for each of a plurality of memory modules mounted on a substrate, and storing the partial mapping table corresponding to the corresponding memory module.

The present invention can add or delete new memory modules in a storage device using a nonvolatile memory.

The present invention does not need to newly create a mapping table for the entire memory module even if the memory module constituting the storage device is attached or detached by allocating a mapping table to each memory module constituting the storage device.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The extended flash memory device described herein may be a flash memory device using a NAND gate or a NOR gate. In addition, the extended flash memory device described in the present invention may be configured as a chip according to an SLC (Single Level Cell) method or a MLC (Multi Level Cell) method.

The present invention is not affected by the type of memory chip used. Therefore, the memory module referred to in the present invention may use a flash memory chip of a NAND gate or a NOR gate method, and likewise, a memory chip according to the SLC method or a chip according to the MLC method may be applied. Do not.

In addition, in the following description, a controller for controlling a memory module is referred to as a controller, and a "module" or a "unit" may be used as a suffix to components constituting the controller.

Components used in the present specification, and suffixes thereof are given only in consideration of ease of preparation of the present specification, and the "module" and "unit" may be used interchangeably.

The "expandable flash memory device" described in the present specification may be implemented as a solid state disk (SSD) or may serve as a nonvolatile storage medium in an embedded device. Accordingly, the expandable flash memory device described herein may be applied to various devices for storing personal computers, servers, notebooks, PDAs, personal media players (PMPs), video game machines, mobile phones, and other data. .

1 is a conceptual diagram illustrating a connection relationship between an extended flash memory device and a host according to the present invention.

Referring to FIG. 1, an extended flash memory device 100 according to an exemplary embodiment of the present invention is connected to a host 30 and used, and when the host 30 is booted, it negotiates an address system for data transmission with the host 30. It handles mutual data transmission according to the negotiated address system.

First, when the host 30 is booted (or reset), the processor 31 obtains device information on the extended flash memory device (SSD) 100 through the BIOS 32. The BIOS 32 includes device information on various hardware devices mounted on the host 30, and transmits various hardware device information to the processor 31 when the host 30 is booted. Next, the processor 31 recognizes the existence of the extended flash memory device 100 and checks whether the extended flash memory device 100 is available (S1). The controller 120 of the extended flash memory device 100 responds to the availability of the host 30 (S2), and negotiates an address system for data transmission with the host 30 (S3). In the CHS addressing system, the BIOS 32 stores cylinder, head, and sector information of the hard disk drive, and the processor 31 of the host 30 uses the CHS information to store the hard disk information. An address system that performs data communication with a disk drive.

Logical Block Addressing (LBA) addressing refers to an addressing system that assigns a serial number to the first sector of a hard disk drive and then assigns the next serial number to the next sector to form an address. Currently, the LBA addressing system is applied to not only a mechanical hard disk drive but also a flash memory device. This specification will be described based on the currently widely used LBA address system.

When the host 30 and the control unit 120 of the extended flash memory device 100 recognize each other and the negotiation about the address system for data transmission is completed, the host 30 reads data into the extended flash memory device 100. , Write, delete, and various other control commands may be transmitted (S4), and the extended flash memory device 100 may perform a response to a control command of the host 30 (S5). ). The response of the extended flash memory device 100 transmits data to the host 30 when the host 30 reads, writes, or deletes desired data, or processes a control command of the host 30. This corresponds to one of sending the result to the host 30.

On the other hand, the extended flash memory device 100 must form an entire mapping table for each of the memory modules 160a to 160c before the host 30 transmits a control command.

The entire mapping table means that the partial mapping table for each memory module 160a to 160c mounted on the substrate 150 is formed as one mapping table. In the present invention, the partial mapping table is provided in each memory module 160a to 160c. Since each of the memory modules 160a to 160c may be mounted on or removed from the substrate 150, the controller 120 first checks the existence of the memory modules 160a to 160c mounted on the substrate 150. When a newly installed memory module is present on the substrate 150, the controller 120 forms an entire mapping table through the memory modules 160a to 160c that already exist, and then stores a newly installed memory address. Create a complete mapping table by assigning it to a module.

At this time, the controller 120 writes the partial mapping table in the newly installed memory module.

Here, the partial mapping table allocated to each memory module has an important difference from the partial mapping table allocated to a general flash memory device.

Since a typical flash memory device cannot be mounted or removed from a memory module, the whole flash memory is divided into a plurality of blocks, and a partial mapping table is stored in each block. At this time, the partial mapping table stored in each block is not associated with the stored block.

On the other hand, the partial mapping table according to the present invention is directly associated with each memory module 160a to 160c is stored for each memory module (160a to 160c).

The present invention allows each memory module 160a-160c to have a partial mapping table associated with it. Therefore, when any one of the memory modules 160a to 160c is removed, the partial mapping table corresponding to the removed memory modules 160a to 160c is removed.

When a new memory module is mounted on the substrate 150, the controller 120 assigns an address area to the newly mounted memory module, which is not used in the entire mapping table formed by each memory module 160a to 160c. This makes it easy to build a complete mapping table.

Referring to FIG. 1, the substrate 150 may include three memory modules 160a to 160c, and the connection portions 140d to 140n may be empty.

The empty connection portions 140d to 140n may allow a user to later install a new memory module to increase the storage capacity of the extended flash memory device, and may be implemented in the form of a socket and a slot.

Similarly, any one of the memory modules 160a-160c can be removed according to the needs of the user. That is, the present invention can increase or decrease the capacity of the extended flash memory device 100, and the old memory modules 160a to 160c can be removed as necessary.

Each memory module 160a to 160c is composed of a plurality of blocks.

The blocks for each memory module 160a-160c are not partitioned on the basis of cylinders, headers, and sectors, unlike mechanical hard disk drives. Therefore, in order to perform data communication with the host 30 instead of the hard disk drive that is still widely used, each physical block must correspond to each physical block with the logical address system of the host 30. The entire mapping table must be used to map the logical address of the host and the physical address of each block.

The controller 120 collects the partial mapping tables distributed and stored in each of the memory modules 160a to 160c to form one entire mapping table, and stores the entire mapping table in the memory 150. Thereafter, when the host 30 transmits a control command such as read, write, delete, and format by using the logical address, the controller 120 associates the corresponding block by using the entire mapping table.

2 is a block diagram illustrating an extended flash memory device according to an embodiment of the present invention.

Referring to FIG. 2, an extended flash memory device according to the present invention may include a host interface unit 110, a controller 120, a memory interface unit 130, memory modules 160a-160c, and memory modules 160a-160c. And a connecting portion 140 for mounting and detaching.

The memory modules 160a to 160c are composed of one or a plurality of flash memory chips capable of writing, rewriting, and erasing. Each memory module 160a to 160c is divided into a plurality of blocks. Each of the memory modules 160a to 160c divides a data storage area capable of reading and writing data into blocks, and reads, writes, and rewrites data of the host 30 in blocks.

Each memory module 160a to 160c has a partial mapping table corresponding to its own capacity among the total storage capacities. The partial mapping table determines which block of the memory module 160a to 160c to map the logical address of the host 30 when the host 30 wants to read or write data through its logical address.

In the present embodiment, the mapping table is provided in each memory module 160a to 160c mounted on the substrate 150. Each memory module 160a to 160c has its own mapping table (partial mapping table).

In the conventional mapping table, the partial mapping table for the entire memory modules 160a to 160c is simply divided and stored regardless of the memory modules 160a to 160c. However, in the present embodiment, the memory modules 160a to 160c correspond to themselves. Only a partial mapping table is provided.

This feature is enhanced when the external memory module 141 is additionally mounted to the substrate 150. For example, assuming that the external memory module 141 has the same form as a general-purpose computer memory of the DDR2 type, and the board 150 is provided with a slot accessible to the external memory module 141, the external memory module 141 is provided. ) Is mounted in the slot, the controller 120 allocates a range of logical addresses not allocated to the memory modules 160a to 160c among the logical addresses of the host 30 to the newly installed external memory module 141, and By storing in the memory module 141, the entire mapping table and the partial mapping table creation are completed.

The connection unit 140 may be one or plural and have a slot or socket. The connection unit 140 mounts or detaches the external memory module 141 through a slot or a socket. The connection unit 140 is formed on the substrate 150 of the expandable flash memory device 100, and the user adds an external memory module 141 to increase the storage capacity, or any unnecessary memory modules 160a to 160c. Make it easy to remove.

The controller 120 detects whether a new external memory module 141 is mounted in the slot (or socket) provided in the connection unit 140. When the new external memory module 141 is mounted in the slot, the newly installed external memory is installed. The partial mapping table for the module 141 is generated and the generated partial mapping table is recorded in the newly mounted external memory module 141.

In addition, the controller 120 adds the partial mapping table of the newly mounted external memory module 141 to the entire mapping table included in the controller 120 to form the entire mapping table.

Here, the entire mapping table is stored in the memory 150. The entire mapping table is the sum of the partial mapping tables stored in each of the memory modules 160a to 160c. Therefore, the controller 120 is detached from the entire mapping table when the memory module 160a to 160c installed in the slot (or socket) constituting the connection unit 140 is detached from the slot (or socket). The information corresponding to the memory modules 160a to 160c is deleted to reconstruct the entire mapping table. In addition, when the external memory module 141 is additionally mounted in the slot (or socket), a partial mapping table is generated by allocating some of the logical addresses of the host 30 to the newly installed external memory module 141. The generated partial mapping table is recorded in the storage area of the newly mounted external memory module 141. In this case, the controller 120 updates the entire mapping table by reflecting the partial mapping table for the newly installed external memory module 141 in the entire mapping table.

Meanwhile, a memory module (or an external memory module) mounted in a slot (or socket) is divided into a plurality of blocks to correspond to data input / output requests of the host 30 in units of blocks.

Preferably, the control unit 120 includes an FTL processing unit 121, and when the FTL processing unit 121 issues a read command to a block included in a specific memory module, the host 30 is provided at the host 30. The physical address PBA of the block corresponding to the logical address LBA is mapped.

Each memory module 160a to 160c performs writing, rewriting, and erasing on a block-by-block basis for each memory module 160a to 160c, and the controller 120 blocks blocks constituting each memory module 160a to 160c. Wear-leveling is performed so that writing, erasing, and rewriting of a specific block is not concentrated and worn out.

The host interface unit 110 converts the type of data transmitted between the host 30 and the control unit 120. For example, when the host 30 interfaces with the extended flash memory device 100 through a Serial-ATA (SATA) interface, the host interface 110 may receive data transmitted from the controller 120. Converted according to SATA method and provided to host 30. The host interface unit 110 may support SATA1, SATA2, SCSI, and IDE interfaces according to the interface method of the host 30. In addition, various interfaces may be applied according to the interface required by the host 30. have.

In addition, the host interface 110 receives a command transmitted from the host 30, and provides the received command to the controller 120. The command transmitted by the host 30 may be a main command for reading and writing, but may be a command for requesting RAID support, and a command for requesting status information on other data recording devices.

The control unit 120 receives various commands of the host 30 through the host interface unit 110 and performs the received commands. In addition, the controller 120 returns the processing result of the command received through the host interface unit 110 to the host 30, and when the host 30 requests data, the controller 120 sends the data from the memory modules 160a to 160c. The data is read and the data read through the host interface 110 is provided to the host 30.

The memory modules 160a to 160c are formed by integrating one or more flash type memory chips capable of writing, rewriting, and erasing, and are divided into a plurality of blocks by the controller 120.

The memory interface unit 130 transmits a command provided from the controller 120 to the memory modules 160a to 160c and provides data read from the memory modules 160a to 160c to the controller 120.

3 and 4 show an example of a connection.

First, FIG. 3 shows a first embodiment of a connecting portion formed on the substrate 150.

Referring to FIG. 3, the connection unit 140 interfaces with the external memory module 141 or the memory modules 160a to 160c through slots 170a to 170n attached to the substrate. The user may change the storage capacity of the expanded semiconductor memory device 100 by mounting the external memory module 141 in the slots 170a through 170n or by removing the mounted memory modules 160a through 160c. In this case, the external memory module 141 mounted in the slots 170a to 170n may include a plurality of flash chips 171a, 171b, and 171c.

Next, referring to FIG. 4, the connection part 140 has a form of a socket attached to the substrate 150. When the connection unit 140 has a socket shape, the external memory module 141 may be fastened to the sockets 180a to 180n by levers 181a to 181n provided at the sockets 180a to 180n. In addition, since the connection portion 140 has a socket shape, the distance between the external memory module 141 and the substrate 150 is smaller than that of the slot method, thereby reducing the thickness of the extended flash memory device. have.

5 conceptually illustrates a mapping table structure of an extended flash memory device according to the present invention.

Referring to FIG. 5, the extended flash memory device 100 according to the present invention includes a partial mapping table for each memory module 160a to 160c mounted in a slot (or socket). The partial mapping table is a mapping table for the memory modules 160a to 160c mounted in the slot (or the socket, which will be omitted later), and when the partial mapping table of all the memory modules 160a to 160c mounted in the slot is added, the extended flash It becomes an entire mapping table for the memory device 100. In the figure, the mapping table of each memory module corresponds to a logical address of the host 30 and a physical address of a block constituting each memory module.

Since the logical address of the host 30 and the corresponding partial mapping table are independent of each other, it is easy to modify the entire mapping table when the memory module 160a to 160c is removed from the slot.

Similarly, when the external memory module 141 is mounted in the slot, an empty logical address among the logical addresses LBA of the host 30 is allocated to the external memory module 141 to create the entire mapping table, Creation and assignment are complete.

6 is a reference diagram for a connection relationship between a memory module and a controller.

Referring to FIG. 6, the controller 120 is connected to each memory module 160a to 160n through buses BUS0 to BUSn, and a flash chip constituting each memory module 160a to 160n is selected from among buses BUS0 to BUSn. Connect to either.

In FIG. 6, a partial mapping table (eg, a mapping table of memory module 1) is stored in some of the storage areas of the memory modules 160a to 160n. The partial mapping tables provided in the memory module 160a and the memory module 160n are independent of each other and do not overlap with the logical addresses of the host 30. Therefore, even when the user removes the memory modules 160a to 160n, the partial mapping table (mapping table of the memory module 2) of the memory modules 160a to 160n has no effect, and thus the memory modules 160a to 160n have no effect. You do not need to change the partial mapping table. This is the most important difference between the mapping table according to the invention and the mapping table for a conventional flash memory device. This will be described with reference to FIG. 7 and FIG. 8 together.

7 and 8 conceptually illustrate a method of constructing a conventional mapping table compared to the present invention.

First, referring to FIG. 7, the general mapping table creates the entire mapping table, divides it, forms partial mapping tables 51a to 53a, and assigns them to each memory module 51 to 53. FIG. At this time, the partial mapping table allocated to each of the memory modules 51 to 53 has no direct relation with each of the memory modules 51 to 53.

Next, referring to FIG. 8, when the memory module 52 of FIG. 7 is arbitrarily removed, the partial mapping table 52a stored in the memory module 52 is not the memory module 52, but the entire mapping table. This is one of the partial mapping tables that composes, so you must rewrite the entire mapping table.

9 is a flowchart illustrating a method of configuring a mapping table in a control method of an extended flash memory device according to the present invention.

First, the controller 120 scans the slots 170a to 170n to determine whether there is an external memory module 141 added to the slots 170a to 170n (S301). As a result, when the external memory module 141 added to the slots 170a to 170n exists, the controller 120 generates a partial mapping table for the added external memory module 141 (S302). The partial mapping table for the external memory module 141 forms a logical address of the host 30 corresponding to the physical address of the external memory module. The formed partial mapping table is stored in the added external memory module 141 (S304). Therefore, the external memory module 141 includes a partial mapping table independent of the mapping table of the other memory modules 160a to 160c mounted on the substrate 150.

Next, the controller 120 forms an entire mapping table by using the memory modules 160a to 160c mounted on the substrate 150 and the partial mapping table for the external memory module (S304). The entire mapping table may be stored in the memory 150 or in a separate memory connected to the controller 120.

Next, the controller 120 determines whether there is a memory module (or an external memory module) removed from the slots 170a to 170n (S305). In the present invention, the memory module (or external memory module) can be added to or removed from the slots 170a-170n by the user.

If the memory module (or external memory module) removed from the slots 170a to 170n exists, the controller 120 deletes the partial mapping table of the memory module (or external memory module) removed from the entire mapping table. In this case, the controller 120 does not need to newly create the entire mapping table other than the deleted partial mapping table.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a conceptual diagram of a connection relationship between an extended flash memory device and a host according to the present invention;

2 is a block diagram of an extended flash memory device according to an embodiment of the present invention;

3 and 4 are views illustrating an example of a connection unit;

FIG. 5 conceptually illustrates a mapping table structure of an extended flash memory device according to the present invention; FIG.

6 is a reference diagram for a connection relationship between a memory module and a controller;

7 and 8 conceptually illustrate a method of constructing a conventional mapping table compared with the present invention; and

9 is a flowchart illustrating a method of configuring a mapping table in a control method of an extended flash memory device according to the present invention.

* Description of the symbols for the main parts of the drawings *

110: host interface unit 120: control unit

130: memory interface unit 150: connection unit

160a to 160c: memory module

Claims (14)

A substrate having a connection portion to which at least one memory module is mounted; And And a controller configured to form a partial mapping table for the mounted memory module and to allocate the formed partial mapping table to the mounted memory module when the memory module is mounted in the connection unit. . The method of claim 1, The control unit, And a partial mapping table for at least one memory module mounted in the connection unit to form one entire mapping table. The method of claim 2, The control unit, And removing the partial mapping table for the detached memory module from the entire mapping table when the memory module is detached from the connection unit. The method of claim 2, And a memory configured to store the entire mapping table. The method of claim 1, The at least one memory module is divided into a plurality of blocks, The control unit, the flash memory device, characterized in that for performing the block as a unit. The method of claim 1, The connecting portion, And at least one slot for mounting and detaching the memory module. The method of claim 1, The connecting portion, And at least one socket for mounting and detaching the memory module. The method of claim 1, Each memory module, An extended flash memory device comprising at least one nonvolatile memory chip. Forming a partial mapping table for each of the plurality of memory modules mounted on the substrate; And And storing the respective partial mapping tables in correspondence with a corresponding memory module. 10. The method of claim 9, And forming a whole mapping table by using the partial mapping table for each memory module. The method of claim 10, And removing any partial mapping table corresponding to the removed memory module from the entire mapping table when any one of the memory modules is removed from the substrate. Way. 10. The method of claim 9, Forming the partial mapping table, And when a memory module is newly added to the substrate, forming a partial mapping table for the memory module. 10. The method of claim 9, And performing wear leveling on each of the memory modules using the partial mapping table. The method of claim 13, Performing the wear level leveling, And a plurality of blocks constituting the memory modules.

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