KR20100058347A

KR20100058347A - Suspended clock state detection logic and semiconductor device using thereof

Info

Publication number: KR20100058347A
Application number: KR1020080117112A
Authority: KR
Inventors: 심용
Original assignee: 삼성전자주식회사
Priority date: 2008-11-24
Filing date: 2008-11-24
Publication date: 2010-06-03

Abstract

A suspend clock state sensing circuit and a semiconductor device using the same are provided. The present invention relates to a device capable of detecting whether an external clock is normally toggled or in a suspended state. An object of the present invention is to provide a device capable of detecting when the external clock is in a suspended state and immediately detecting the external clock when the external clock is restored to its normal state. According to the present invention, when the external clock is in the suspended state, the operation of the semiconductor device using the external clock can be switched to an operation mode with low power consumption.

Description

Suspended clock state detection circuit and semiconductor device using same

The present invention relates to a suspended clock state sensing circuit. More particularly, the present invention relates to a device for detecting an external clock change to a suspended state by detecting a voltage drop caused by discharge of charge charged in a capacitor when an external clock changes to a suspended state in a memory semiconductor.

Currently, for most memory operations, the external clock is implemented to be always constant. However, to reduce current consumption, some companies use external clocks in suspend state. When the external clock is switched to the suspended state when the external clock does not need to operate like this, a device that can detect this and use it to reduce the current consumption of the memory is needed.

In order to solve the above problems of the conventional technology, the present invention is to provide an apparatus for detecting when the external clock is switched to the suspended state.

It also aims to provide a device that immediately detects when an external clock returns from a suspended state to a normal state.

In addition, the present invention provides a device that can reduce power consumption when an external clock is in a suspended state by using a circuit for detecting a suspended state.

In addition, other objects of the present invention will be readily understood through the following description of the embodiments.

According to the present invention, an external clock and a control signal are input, the input unit for outputting an output signal corresponding to the external clock only when the control signal is enabled (enable) and in response to the output signal of the input unit Whether the external clock is in a toggling normal operating state or a non-toggling suspend state is determined using a change in voltage through charge / discharge of the charge, and the external clock is in a suspended state. There is provided a suspended clock state detection circuit of a semiconductor, including a suspended state signal generator for generating a suspended state signal.

Here, the suspended state signal generator generates a second signal by dividing the change of the voltage through charge and discharge of the first signal unit and the charge and discharge of the charge to distinguish the change of the voltage through the charge and discharge of the charge; And a signal output unit configured to receive the first signal and the first signal and the second signal to generate the suspended state signal.

Here, the first signal unit charges and discharges a first capacitor connected to the inverter and outputting a power supply voltage or a ground voltage in response to the output signal of the inverter connected to the inverter and the inverter to receive the output signal of the input unit inverted state; And a first capacitor connected between the first capacitor charge / discharge unit and the ground and charged / discharged by an output voltage of the first capacitor charge / discharge unit, wherein the second signal unit corresponds to a power supply voltage in response to an output signal of the input unit. Or a second capacitor charge / discharge unit for outputting a ground voltage, and a second capacitor connected between the second capacitor charge / discharge unit and ground and charged / discharged by the output voltage of the second capacitor charge / discharge unit. have.

The first capacitor charge / discharge unit and the second capacitor charge / discharge unit may each include a PMOS transistor and at least one NMOS transistor, wherein the PMOS transistor is disposed between a power supply voltage and the NMOS transistor. The PMOS transistor is connected to output the power supply voltage, and the NMOS transistor is connected between the PMOS transistor and the ground to output the ground voltage when the NMOS transistor is operated. Suspended clock state detection circuit.

Here, the PMOS transistor may have a high driving capability to immediately output a power supply voltage when the external clock returns to the normal operation state.

Here, the first signal and the second signal may be connected to a Schmitt Trigger circuit, respectively, to eliminate ripple.

In addition, in the semiconductor device, a suspend clock state detection circuit unit for inputting an operation control signal and an external clock of the semiconductor device and detecting a suspended state of the external clock by the operation control signal and outputting a suspended state signal; A semiconductor device is provided, comprising: an operation change unit for receiving the suspended state signal from a suspended clock state detection circuit unit and outputting an operation change signal for changing an operation of an internal circuit of the semiconductor device.

Here, the suspended clock state detection circuit unit receives an external clock input to the semiconductor device and determines whether the external clock is in a normal operating state in which the external clock is toggling or in a suspended state in which the external clock is not toggled. It is possible to distinguish using a change in voltage, and generate the suspended state signal when the external clock is in a suspended state.

According to the present invention, in the suspended clock state detection circuit, when the external clock is in the suspended state, it detects this to generate a suspended state signal, and when the external clock is in a normal state, the suspended state signal is not generated or not. This has the effect of knowing whether the external clock is normal or in a suspended state.

In addition, in the semiconductor device, the operation of the internal circuits of the semiconductor device may be changed to normal and sleep modes using a suspended clock state sensing circuit, thereby reducing power consumption of the semiconductor device when the external clock is in the subpended state. There is.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

Terms used to describe various components may be used in the present invention, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating the configuration of a suspended clock state detection circuit as an embodiment of the present invention.

In the present invention, the suspended state refers to a state in which the clock does not operate and will be used as a word representing the same meaning below.

The suspended clock state detection circuit 10 includes an input unit 100 and a suspended state signal generator 200.

The input unit 100 receives an external clock EXT_CLK and a control signal CONTROL. When the control signal CONTROL is disabled, the external clock EXT_CLK toggles the normal operating state. Alternatively, the output signal is output in the 'high' state regardless of the suspended state which is not toggled. However, when the control signal CONTROL is enabled, the external clock EXT_CLK is output in the high state when the external clock EXT_CLK is input in the low state (including the suspended state). In addition, the generated output signal is transferred to the suspended state signal generator 200. The operation of the input unit 100 will be described with reference to FIGS. 2 and 3.

The suspended state signal generator 200 outputs a signal for distinguishing whether the external clock EXT_CLK is in a normal state or a suspended state in response to an output signal of the input unit. A detailed description of the suspended state signal generator 200 will be described with reference to FIGS. 2 and 3.

2 is a diagram illustrating a circuit configuration of a suspended clock state detection circuit according to an embodiment of the present invention.

The input unit 100 includes a NAND gate 110, and an external clock EXT_CLK and a control signal CONTROL are respectively input. Only when the control signal (CONTROL) is in an enabled state (for example, when the voltage is 'high'), the output of the input (i.e., the voltage state of node A) will change according to the external clock (EXT_CLK). According to the case where the clock EXT_CLK is in a normal operating state and in a suspended state, the output signal of the input unit may have a different state signal. For example, when the control signal CONTROL is enabled, that is, when the control signal voltage is 'high', the external clock EXT_CLK is inverted from the external clock while the external clock EXT_CLK is normally toggled. This output signal comes out. If the external clock EXT_CLK is in the suspended state, that is, the external clock EXT_CLK is not toggled while the control signal CONTROL is enabled, the output signal is output at a constant level. For example, when the external clock EXT_CLK is kept in a low state without being toggled, the output signal of the input unit 100 is output at a 'high' level. On the other hand, when the control signal (CONTROL) is in a disabled state (for example, when the voltage is 'low'), the output signal of the input part even when the external clock EXT_CLK is normally toggled and in the suspended state. The signal 'high' of the same state is output. Therefore, when it is desired to detect whether the external clock EXT_CLK is in a suspended state, the control signal CONTROL is input as an enable state.

The suspended state signal generator 200 includes a first signal unit 210, a second signal unit 220, and a signal output unit 230. The first signal unit 210 includes a first capacitor charge and discharge unit 211 connected in series with the inverter 213 and a first capacitor 212 charged and discharged by the first capacitor charge and discharge unit. The second signal unit 220 includes a second capacitor charge and discharge unit 221 and a second capacitor 222 charged and discharged by the second capacitor charge and discharge unit. The first signal unit 210 and the second signal unit 220 are connected through the input unit 100 and the node A, and the outputs of the first signal unit 210 and the second signal unit 220 are signal output units, respectively. It is input to the input terminal of 230. Since the first signal unit 210 receives the output signal of the input unit 100 through the inverter 213, the signals input to the first capacitor charge / discharge unit 211 and the second capacitor charge / discharge unit 221 are different from each other. Is entered.

Referring to the first signal unit 210 in more detail, the first capacitor charge / discharge unit 211 is composed of a PMOS transistor and a plurality of NMOS transistors, as shown in FIG. 2, from the node A through the inverter 213. When the input signal is at the 'low' level, the first capacitor 212 is charged through the PMOS. When the signal input from the node A via the inverter 213 is 'high' level, the first capacitor 212 is discharged through the NMOS. Here, a plurality of NMOSs are implemented to increase the discharge time of the first capacitor 212. Therefore, even when the signal input to the node A changes periodically, since the discharge time of the first capacitor 212 is longer than the period of the signal input to the node A, the voltage applied to the node B can maintain a high state. . However, when the signal input from the node A through the inverter 213 is constant at the 'high' level, since the first capacitor 212 is discharged through the NMOS, the voltage applied to the node B is maintained at the 'low' state. . The first signal unit 210 has a circuit configuration in which the output signal of the input unit 100 is input via the inverter 213 as shown in FIG. 2.

Since the second signal unit 220 has the same circuit configuration except for the first signal unit 210 and the inverter 213, a detailed description of the configuration and operation of the second signal unit 220 will be omitted. Shall be.

As described above, when the signals input to the first signal unit 210 and the second signal unit 220 periodically change, that is, when the external clock EXT_CLK is normally toggled, the node B and the node C are caught. The voltage remains 'high'. However, when the signals input to the first signal unit 210 and the second signal unit 220 do not change periodically, that is, when the external clock EXT_CLK is in the suspended state, the voltages applied to the node B and the node C are different from each other. It becomes a state. That is, when the voltage of node B is 'high', the voltage of node C is 'low', and when the voltage of node B is 'low', the voltage of node C is 'high'.

When the external clock EXT_CLK is in the suspended state, the voltage applied to the node B and the node C becomes 'high' or 'low' depending on the circuit configuration, but it is obvious that the voltage is within the scope of the present invention. .

Therefore, as described above, if the voltages applied to the node B and the node C are both 'high' state, the external clock (EXT_CLK) is a normal state toggling, and if the voltages applied to the node B and the node C are different voltage states, It can be seen that the external clock EXT_CLK is in a suspended state.

In this case, the output of the first signal unit 210 and the second signal unit 220 may be connected to Schmitt Trigger circuits 214 and 215, respectively, to obtain a more stable output. The Schmitt Trigger circuits 214 and 215 have hysteresis characteristics to prevent unstable output changes at the threshold, so that the voltage states of Node B and Node C are 'high' or 'low' within the threshold. Prevents unstable changes to level. That is, the change of the output at the critical point due to the ripple of the first signal and the second signal which are the outputs of the first signal unit 210 and the second signal unit 220 is prevented. It is apparent that the first signal and the second signal are the same as the voltage states applied to the node B and the node C, respectively.

In addition, the characteristics of the PMOS of the first capacitor charging and discharging unit 211 and the second capacitor charging and discharging unit 221 have a low resistance so that current flows immediately when a low voltage is applied to the gate. When EXT_CLK) returns to the normal state, the node B and the node C can be immediately energized. For this purpose, the driving capability of the PMOS is largely implemented. For example, the size of PMOS can be increased.

The signal output unit 230 receives the output signals (ie, the first signal and the second signal) of the first signal unit 210 and the second signal unit 220 to inform that the external clock EXT_CLK is in a suspended state. Generate a suspended status signal. The signal output unit 230 includes a NAND gate 231. Accordingly, the suspended state signal output through the NAND gate 231 is 'low' level only when both the output signals of the first signal unit 210 and the second signal unit 220 are 'high', and the first signal unit When the output signals of the 210 and the second signal unit 220 are different from each other, the suspended state signal output through the NAND gate 231 becomes 'high' level. That is, when the suspended state signal output through the NAND gate 231 is 'high' level, it can be seen that the external clock EXT_CLK is in the suspended state. Here, the output signal of the first signal unit 210 is the first signal and has the same meaning as the voltage state of the node B, and the output signal of the second signal unit 220 has the same meaning as the voltage state of the node C as the second signal. to be.

3 is a timing diagram illustrating a change in a suspended state signal according to a change in an external clock when the control signal is enabled according to an embodiment of the present invention.

In FIG. 3, EXT_CLK means an external clock, A means node A, B means node B, and C means node C. In FIG.

When the external clock EXT_CLK is in a normal state toggling normally, the node A is output in the opposite direction to the external clock EXT_CLK. In this case, the voltages of the node B of the first signal part and the node C of the second signal part are maintained 'high' by the charges charged in the first capacitor 212 and the second capacitor 222 as described in FIG. 2. If the voltages of node B and node C are 'high', the suspended state signal is output 'low'.

When the external clock EXT_CLK is in the suspended state, node A is output as 'high'. At this time, the node B of the first signal part is outputted as 'high' by operating the PMOS transistor as described in FIG. 2, and the voltage of the node C of the second signal part is operated by the NMOS transistor as described in FIG. The charge of the capacitor 222 is discharged and output as 'low'. In this case, the time for discharging the charge of the second capacitor 222 is required until the voltage of the node C of the second signal unit is output as 'low'. That is, as shown in FIG. 3, the voltage of the node C is output 'low' after the time when the charge of the second capacitor 222 is discharged. When the voltage of the node C is output 'low' after a time when the charge of the second capacitor 222 is discharged, the suspended state signal is output 'high'.

When the external clock EXT_CLK returns to the normal state in which the external clock EXT_CLK is normally toggled again, as shown in FIG. 2, the PMOS transistors of the first signal part and the second signal part operate to operate with the first capacitor 212. The second capacitor 222 is charged, whereby the voltages of the nodes B and C are output as 'high'. In this case, as described above, the suspended state signal is output as 'low'.

4 is a diagram illustrating the configuration of a semiconductor device using a suspended clock state detection circuit as an embodiment of the present invention.

The semiconductor device 400 of the present invention includes a suspended clock state detection circuit unit 410, an operation change unit 420, and an internal circuit unit 430.

The suspended clock state detection circuitry 410 determines whether the external clock is toggling when the operation control signal is input (i.e., when the control signal is enabled) or is in a suspended state where the external clock is not toggled. It performs a function of generating a suspended state signal when the external clock is in a suspended state by using a change in voltage through charge and discharge of charge. The operation control signal may be input from the outside of the semiconductor device or may be a signal set inside the semiconductor device. The suspended clock state detection circuit unit 410 includes a circuit that charges and discharges charges by an external clock. For more information about the suspended clock state detection circuit unit 410, refer to the suspended clock state detection circuit 10 described above.

The operation change unit 420 receives the suspended state signal from the suspended clock state detection circuit unit 410 and outputs an operation change signal. The operation change unit 420 transfers an operation change signal to the internal circuit unit 430 to change the operation of the internal circuit unit 430. For example, when the external clock is in the suspended state, an operation change signal is generated to change the internal circuit unit 430 of the semiconductor device to the sleep mode. When the internal circuit unit 430 of the semiconductor device is changed to the sleep mode, current consumption is reduced as compared to the normal mode. In addition, when the external clock recovers to the normal state, the operation change unit 420 changes the operation of the internal circuit unit 430 from the sleep mode to the normal mode again. That is, when the external clock is in the suspended state, the operation change unit 420 receives the suspended state signal from the suspended clock state detection circuit unit 410 to generate an operation change signal to reduce power consumption of the semiconductor device, thereby generating a circuit inside the semiconductor device. Change the circuits to the sleep mode and change the circuits inside the semiconductor device to the normal mode in which the normal operation is possible when the external clock is restored to the normal state.

The internal circuit unit 430 refers to a general term of internal circuits configured in the semiconductor device. The internal circuits may be, for example, a delay lock loop (DLL), a phase lock loop (PLL), a data input / output (I / O) circuit, or the like. The above circuits are changed from the normal mode to the sleep mode when the operation change signal is input from the operation change unit 420. Obviously, other circuits may be added to the circuit included in the internal circuit unit 430.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

10: suspend clock state detection circuit

100; Input

110: NAND gate

200: suspended state signal generation unit

210: first signal part

211: first capacitor charge and discharge circuit

212: first capacitor

213: Inverter

214: Schmitt Trigger Circuit

220: second signal part

221: second capacitor charge and discharge circuit

222: the second capacitor

224: Schmitt Trigger Circuit

230: signal output unit

231: Nand Gate

400: semiconductor device

410: suspended clock state detection circuitry

420: motion change unit

430: internal circuit

Claims

An input unit for outputting an output signal corresponding to the external clock only when an external clock and a control signal are input and the control signal is in an enable state;

In response to the output signal of the input unit, the external clock is divided into a normal operating state of toggling or a suspended state of non-toggling by using a change of voltage through charge / discharge of charge, and the external And a suspended state signal generator for generating a suspended state signal when the clock is in a suspended state.

The method of claim 1,

The suspended state signal generator

A first signal unit for generating a first signal by distinguishing the change in voltage through the charge and discharge of the charge

A second signal unit configured to generate a second signal by dividing a change in voltage through charge / discharge of the charge;

And a signal output unit configured to receive the first signal and the second signal to generate the suspended state signal.

The method of claim 2,

The first signal unit

Inverter that receives the output signal of the input unit and outputs the signal of the inverted state

A first capacitor charge / discharge unit connected to the inverter and outputting a power supply voltage or a ground voltage in response to an output signal of the inverter;

And a first capacitor connected between the first capacitor charge and discharge unit and the ground and charged and discharged by an output voltage of the first capacitor charge and discharge unit.

The second signal unit

A second capacitor charge and discharge unit configured to output a power supply voltage or a ground voltage in response to an output signal of the input unit;

And a second capacitor connected between the second capacitor charge / discharge unit and the ground and charged / discharged by the output voltage of the second capacitor charge / discharge unit.

The method of claim 3,

The first capacitor charge and discharge unit and the second capacitor charge and discharge unit each include a PMOS transistor and at least one NMOS transistor, wherein the PMOS transistor is connected between a power supply voltage and the NMOS transistor. The power supply voltage is output when the PMOS transistor is in operation, and the NMOS transistor is connected between the PMOS transistor and ground, and outputs the ground voltage when the NMOS transistor is in operation. Suspended clock state detection circuitry for semiconductors.

The method of claim 4, wherein

And the PMOS transistor has a high driving capability to immediately output a power supply voltage when the external clock returns to the normal operation state.

The method of claim 2,

And the first signal and the second signal are respectively connected to a Schmitt Trigger circuit so that ripple is eliminated.

In a semiconductor device,

A suspended clock state detection circuit unit configured to detect a suspended state of an external clock and output a suspended state signal in response to an operation control signal of the semiconductor device;

And an operation change unit configured to receive the suspended state signal from the suspended clock state detection circuit unit and output an operation change signal for changing an operation of an internal circuit of the semiconductor device.

The method of claim 7, wherein

The suspend clock state detecting circuit unit receives the external clock input to the semiconductor device and determines whether the external clock is in a normal operating state toggling or a suspended state not toggling, and then charges and discharges the voltage. And the suspended state signal is generated when the external clock is in the suspended state.