KR20100055201A - Data programming device, and data programming method - Google Patents

Data programming device, and data programming method Download PDF

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Publication number
KR20100055201A
KR20100055201A KR1020080114167A KR20080114167A KR20100055201A KR 20100055201 A KR20100055201 A KR 20100055201A KR 1020080114167 A KR1020080114167 A KR 1020080114167A KR 20080114167 A KR20080114167 A KR 20080114167A KR 20100055201 A KR20100055201 A KR 20100055201A
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South Korea
Prior art keywords
block
programming
host
data
control unit
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KR1020080114167A
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Korean (ko)
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김종명
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엘지전자 주식회사
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Publication of KR20100055201A publication Critical patent/KR20100055201A/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The present invention relates to a flash memory device and a method for performing wear leveling using a programming number instead of an erase count, simplifying a structure of a control unit for controlling a memory cell, and reducing a process and time required for data programming. will be.

Description

Flash memory device, and data recording method {Data programming device, and data programming method}

The present invention relates to a flash memory device and a data writing method.

BACKGROUND With the development of semiconductor technology, flash memory devices using flash memory have tended to replace conventional mechanical hard disks.

The flash memory cannot perform an in-place update such as a hard disk and requires a process of erasing a block to be written beforehand before recording data.

In addition, each block of flash memory has a limit that can be erased. In the case of a MLC (MultiLevel Cell) chip, the flash memory has a recordable number of times of about 10,000 blocks, and a SLC (Single Level Cell) chip does not exceed 100,000. Therefore, the flash memory searches for blocks with fewer erase counts by referring to the erase count for each block, erases the blocks with fewer erase counts, and then programs (writes) data transmitted from the host, and after programming the data, Has a process of increasing the erase count for the programmed block.

The wear leveling method for equally erasing each block constituting the flash memory is divided into a dynamic wear leveling method and a static wear leveling method.

Dynamic Wear Leveling is a method in which a controller of a flash memory selects a block having the least erase cycle in the flash memory when a host data write request occurs.

Static wear leveling is a method in which the flash controller copies data from the least erased block in flash memory to the block with the highest erase count.

Here, the dynamic wear leveling method and the static wear leveling method,

-Before writing data to the flash memory, the controller of the flash memory should refer to the mapping table once to level out wear,

After writing data to flash memory, the mapping table must be updated to count +1 erases.

That is, every time data is written to flash memory, the mapping table must be referenced twice.

Such a writing process increases the process and time required to write data to the flash memory, and also complicates the controller structure of the flash memory.

Accordingly, an object of the present invention is to provide a flash memory device and a data writing method that not only reduce the time required for data writing but also simplify the structure of a control unit for controlling each block constituting a memory cell.

The above object is to form a mapping table having at least one memory cell composed of a plurality of blocks, the number of programming for each block, according to the present invention, and when programming for a block to be written, A control is performed by updating a programming number for a block and performing wear leveling on each block based on the programming number for each block.

According to the present invention, the object of the present invention is to select a minimum block having the least number of data programming, among a plurality of blocks constituting each of the at least one memory cell, and in response to a data write request from a host. After updating the number of programming, programming the data in the minimum block is achieved.

Therefore, the present invention simplifies the structure of the control unit for controlling the memory cell and reduces the time required for data programming.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The flash memory device described herein may be a flash memory device using a NAND gate or a NOR gate. In addition, the flash memory device described in the present invention may be a flash memory device having a chip according to an SLC (Single Level Cell) method or a MLC (Multi Level Cell) method.

The present invention is not affected by the type of memory cell used. Therefore, the memory cell referred to in the present invention may use a flash memory chip of a NAND gate or a NOR gate method, and likewise, a memory chip according to the SLC method or a chip according to the MLC method may be applied. Do not.

In the following description, a controller for controlling a memory cell is referred to as a controller, and a "module" or a "unit" may be used as a suffix to components constituting the controller.

Components used in the present specification, and suffixes thereof are given only in consideration of ease of preparation of the present specification, and the "module" and "unit" may be used interchangeably.

The "flash memory device" described herein may be implemented as a solid state disk (SSD) or may serve as a nonvolatile storage medium in an embedded device. Accordingly, the flash memory device described herein may be a personal computer, a server, a notebook computer, a personal digital assistant (PDA), a personal media player (PMP), a video game machine, a mobile phone, and various devices for storing data. Can be applied to

1 is a conceptual diagram illustrating a connection relationship between a flash memory device and a host according to the present invention.

Referring to FIG. 1, the flash memory device 100 according to the present invention is connected to a host 50 and used, and when the host 50 is booted, it negotiates a data transmission scheme with the host 50 and negotiates a data transfer scheme. Process mutual data transmission according to the data transmission method.

First, when the host 50 is booted, the processor (CPU) 51 obtains device information on the flash memory device (SSD) 100 through the BIOS 52. The BIOS 52 includes device information about various hardware devices mounted on the host 50, and transmits various hardware device information to the processor 51 when the host 50 is booted. Next, the processor 51 recognizes the existence of the flash memory device 100 and checks whether the flash memory device 100 is usable (S1). The controller 120 of the flash memory device 100 responds to the availability of the host 50 (S2), and negotiates an address system for data transmission with the host 50 (S3). In the CHS address system, the BIOS 52 stores cylinder, head, and sector information of the hard disk drive, and the processor 51 of the host 50 uses the CHS information to store the hard disk drive. This refers to an address system that communicates data with.

Logical Block Addressing (LBA) addressing refers to an addressing system that assigns a serial number to the first sector of a hard disk drive and then assigns the next serial number to the next sector to form an address. This specification will be described based on the currently widely used LBA address system.

When the host 50 and the controller 120 of the flash memory device 100 recognize each other and the negotiation about the address system for data transmission is completed, the host 50 reads and writes data to the flash memory device 100. , Delete, and various other control commands may be transmitted (S4), and the flash memory device 100 may perform a response to the control command of the host 50 (S5). The response of the flash memory device 100 transmits the data to the host 50 when the host 50 reads, writes, or deletes the desired data, or the processing result of the control command (commnand) of the host 50. Corresponds to one of transmitting to the host 50.

Meanwhile, the flash memory device 100 forms a mapping table for each block constituting the memory cell 140 before the host 50 transmits a control command.

The memory cell 140 is composed of a plurality of blocks, and each block is not partitioned based on cylinders, headers, and sectors, unlike mechanical hard disk drives. Therefore, in order to perform data communication with the host 50 instead of the hard disk drive that is still widely used, each physical block needs to correspond to the logical address system of the host 50, and generally uses a "mapping table". In the present invention, the mapping table is divided into a plurality to form a plurality of partial mapping tables, and each partial mapping table is distributed and stored in each of the blocks 140a to 140n.

The controller 120 collects the partial mapping tables distributed and stored in each of the blocks 140a to 140n to form one global mapping table, and stores the entire mapping table in the memory 150. Thereafter, when the host 50 transmits a control command using the logical address, the controller 120 associates the corresponding block using the entire mapping table.

In this case, the entire mapping table may change the address PBA of the physical block corresponding to the logical address LBA of the host 50 with reference to the wear level of each block 140a to 140n.

Generally, before programming each block 140a to 140n, wear leveling is performed by referring to the number of times of erasing the block. However, in the present invention, wear leveling is performed by referring to the number of programming instead of the number of erasing. When leveling wear with a programming count,

When programming the block corresponding to the LBA, the control unit 120 counts the number of programming, and after programming is completed, the control unit 120 does not perform a count for leveling wear. Therefore, the control unit 120 is simpler in structure and easier to implement than in the related art, and also increases the processing speed since the counting process for leveling wear is simplified. This will be described in detail later with reference to FIGS. 2 to 6.

2 is a block diagram of a flash memory device according to an embodiment of the present invention.

2, a flash memory device according to the present invention includes a host interface 110, a controller 120, a memory interface 130, and a memory cell 140.

One or more memory cells 140 may be configured. In the drawing, there are n memory cells 140, and show first memory cells 140a to nth memory cells 140n.

Each memory cell 140a to 140n is constituted by a flash chip capable of writing, rewriting, and erasing. Each memory cell 140a to 140n has a unique physical address (PBA) corresponding to the logical address (LBA) of the host 30.

The physical address PBA corresponds 1: 1 with the logical address LBA on the host 50 side, but when the wear level of the block exceeds an average value, the block may be changed to another LBA. The change is reflected in the entire mapping table formed in the memory 150.

The host interface unit 110 converts the type of data transmitted between the host 50 and the controller 120. For example, when the host 50 interfaces with a flash memory device through a Serial-ATA (SATA) interface, the host interface unit 110 controls the data transmitted from the controller 120 according to the SATA method. The conversion is provided to the host 50. The host interface unit 110 may support SATA1, SATA2, SCSI, and IDE interfaces according to the interface method of the host 50. In addition, various interfaces may be applied according to the interface required by the host 50. have.

In addition, the host interface 110 receives a command transmitted by the host 50 and provides the received command to the controller 120. The command transmitted by the host 50 may be a read and write command, but may be a command for requesting RAID support, and a command for requesting status information about the flash memory device 100.

The controller 120 receives various commands of the host 50 through the host interface 110 and performs the received commands. In addition, the controller 120 returns the processing result of the command received through the host interface unit 110 to the host 50. When the host 50 requests data, the controller 120 reads data from the memory cell 140. In addition, the data read through the host interface unit 110 is provided to the host 50.

The control unit 120 divides each memory cell 140a to 140n into a plurality of blocks, and maps the physical address PBA of each block to the logical address of the host 50 with reference to the entire mapping table.

In addition, the control unit 120 changes the physical address PBA of the block corresponding to the logical address LBA frequently called by the host 50 with reference to the wear level of each block 141a to 143n, thereby changing each block 140a to 143n. 140n) to wear evenly.

At this time, the controller 120 changes the correspondence relationship between the logical address and the physical address with reference to the wear degree of each memory cell 140a to 140n, or within a block included in any one of the memory cells 140a to 140n. You can change the correspondence between logical and physical addresses.

For example, when the controller 120 determines that the memory cell 140a is the most worn memory cell, the control unit 120 may perform wear leveling on the blocks 141a to 141n of the memory cell 140a.

That is, the control unit 120,

Perform wear leveling around the highest wear memory cell (e.g., "140a"), or

Wear leveling can be performed for all blocks 141a to 143n constituting the entire memory cells 140a to 140n.

Throughout the present invention, wear leveling may be performed for individual memory cells (eg, reference numeral “140a”) or for all memory cells 141a to 143n constituting the entire memory cells 140a to 140n. .

Preferably, the control unit 120 includes an FTL processing unit 121 for leveling wear. The FTL processing unit 121 sets the block having the least programming number as the minimum block by using a mapping table. When the data writing request is generated in the host 50, the FTL processing unit 121 requests the data writing to the minimum block.

In this case, the minimum block is,

-The block with the least number of programming,

Unused blocks, and

Blocks with fewer programming times than the average value for the number of programming may correspond.

In this case, since the number of programming means which data has been written in which block, the FTL processing unit 121 selects the minimum block, and then, after +1 processing the programming number for the minimum block, the data for the minimum block immediately. You can pass a write command.

Therefore, the FTL processing unit 121 does not need a process (for example, updating the erase count) to be added after data recording for the minimum block is performed. This feature simplifies the structure and processing of the control unit 120 including the FTL processing unit 121 and the FTL processing unit 121.

In this case, the mapping table referenced by the FTL processing unit 121 may be provided in the control unit 120 or may be located in a separate memory (not shown) connected to the control unit 120, and each of the memory cells 140a to 140n may have a mapping table. One area may be used.

Each block 141a to 143n constituting each of the memory cells 140a to 140n requires a process of erasing the write target block before programming the data, but after programming the write target block, the erase count is written to the mapping table. The process of recording is not necessary.

The memory interface unit 130 transmits a command provided to each of the memory cells 140a to 140n from the controller 120, and provides data read from each of the memory cells 140a to 140n to the controller 120.

3 shows a data recording method according to the present invention, and FIG. 4 shows a conventional data recording method for comparison with the present invention.

First, referring to FIG. 3, the data writing method according to the present invention refers to the number of programming for each block constituting a memory cell, unlike a general wear leveling method. The number of programming refers to the number of times data is written to the block, which corresponds to the important feature that distinguishes the present invention from the conventional data recording method which refers to the number of times of erasing the block (number of erases) before writing the data to the block. .

As the present invention uses the number of programming for wear leveling, the data recording method proposed by the present invention uses a mapping table that is different from the general wear leveling method.

The mapping table according to the present invention has a programming number for each block constituting a memory cell. Unlike the erase count, the programming count can be updated before programming the data into the block.

The data recording method according to the present invention finds the minimum block with the least programming with reference to the number of programming, and after processing +1 the programming number for the minimum block, updates the mapping table in which the programming number for the minimum block is recorded.

That is, in the data writing method according to the present invention, for the data write command of the host, the minimum block is selected with reference to the number of programming, the number of programming for the minimum block is updated, and the programming command is assigned to each memory cell 140a to 횟수. 140n).

Next, referring to FIG. 4, the conventional data writing method performs wear leveling by referring to the erase count of each block constituting each of the memory cells 140a to 140n in response to a data writing command of the host.

In the conventional data recording method, a block having a small erase count is selected as a recording target block with reference to the erase count, and a programming command is executed for the recording target block. However, the conventional wear leveling method transmits a programming command for a block to be written, and updates the erase count of the mapping table when programming of the block is completed. Therefore, in the conventional wear leveling method using the erase count, the process of writing a host's write command takes longer than that of the present invention, and the structure of the control unit that controls the memory cell is increased as the process increases.

5 shows a structure of a mapping table according to the present invention, and FIG. 6 shows a conventional mapping table structure compared with the present invention.

First, referring to FIG. 5, the mapping table according to the present invention includes programming of logical addresses LBA0 to LBAn of a host 50, physical addresses PBA0 to PBAn corresponding to logical addresses of a host, and each block. It has a program cycle.

The logical address of the host 50 corresponds to an address system that the host 50 transmits to the controller 120. The address system of the host 50 is different from the address system of each memory cell 140a to 140n managed in units of blocks, and is usually determined according to the address system of the operating system.

The physical addresses PBA0 to PBAn represent addresses of respective blocks (for example, reference numeral 141a) corresponding to the logical addresses of the host 50. The block corresponding to each of the physical addresses PBA0 to PBAn is determined by the number of times data is written by the host 50.

When the MLC type flash memory having a large storage capacity per unit area and low cost constitutes each memory cell 140a to 140n, approximately 10,000 writes are possible. The program cycle for determining the wear level of each block 141a to 143n constituting each memory cell 140a to 140n is stored in association with the logical address and the physical address of each block 141a to 143n. do.

Next, referring to FIG. 6, although the conventional mapping table also has a host address and a physical address, the physical address for each block has a structure stored in association with the erase count, and this structure is large compared with the present invention. Causes a difference.

When the wear level is equalized by using the erase count, the flash memory device processes programming for the block to be written, and updates the erase count by +1 in the mapping table. Therefore, in the conventional data recording method using the mapping table according to FIG. 5, a processing step is further added compared to the present invention which performs programming immediately after +1 programming times, and the mapping table is referred to twice.

When data is written using the erase count, the conventional flash memory device needs to refer to the mapping table once for leveling wear, and to refer again after programming the data. That is, the structure and processing steps of the controller 120 become complicated.

7 shows a flowchart according to an example of the present invention.

First, the control unit 120 receives a command of the host 50 through the host interface unit 110, and determines whether a data recording command exists among the commands of the host 50 (S201). If the command transmitted from the host 50 is not a command for reading data stored in each of the memory cells 140a to 140n, it is determined whether the command is a control command for each of the memory cells 140a to 140n (S206). In the case of a control command, a control command is performed (S207). The control command includes a command for confirming whether or not the flash memory device 100 can perform data writing, a command for confirming whether data writing is completed, and a command for requesting a response to the non-responsive block. When the device 100 is configured as a RAID, instructions such as data distribution and data verification may be further included.

Next, when the command provided from the host 50 is a data write command for the block, the controller 120 refers to the mapping table (S202) and selects the minimum block having the minimum number of data write operations (S203). The minimum block can be selected by the following two methods.

-Selecting a block having the smallest number of data writes as the minimum block by comparing the number of data writes for each block; and

Obtaining a mean value for the number of data writes for each block, specifying a plurality of blocks having a write count less than the average value as the minimum block, and selecting one of the minimum blocks.

Meanwhile, the minimum block is determined based on the memory cells 140a to 140n having the highest wear among the memory cells 140a to 140n or all the blocks 141a constituting the entire memory cells 140a to 140n. To 143n).

That is, the controller 120 selects the block having the largest wear among the blocks included in the memory cells 140a to 140n having the highest wear as the minimum block, or configures the entire memory cells 140a to 140n. With respect to the blocks 141a to 143n, the block having the largest wear can be determined as the minimum block.

The controller 120 selects the minimum block to which data is to be recorded, and then updates the programming times for the minimum block. The update of the number of programming is preferably updated by +1 the number of programming recorded in the mapping table.

The controller 120 updates the number of programming for the mapping table and immediately transmits a data write command for the minimum block (S205). At this time, the controller 120 determines whether a recording command is transmitted from the host 50 after the data recording operation for the minimum block is finished, and if the host 50 requests the next recording of data, SS201 to S205. Repeat the process to perform recording of the next data.

Unlike a conventional flash memory device, the controller 120 according to the present invention does not update or refer to the mapping table again after data recording for the minimum block is finished. Therefore, the control unit 120 may simplify the process for recording data, and as a result, the structure of the control unit 120 may be simply implemented.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

1 is a conceptual diagram of a connection relationship between a flash memory device and a host according to the present invention;

2 is a block diagram of a flash memory device according to an embodiment of the present invention;

3 shows a data recording method according to the present invention, and FIG. 4 shows a conventional data recording method for comparison with the present invention;

5 shows the structure of a mapping table according to the present invention, FIG. 6 shows a conventional mapping table structure compared with the present invention, and

7 shows a flowchart according to an example of the present invention.

* Description of the symbols for the main parts of the drawings *

100: flash memory device 110: host interface unit

120: control unit 121: FTL processing unit

130: memory interface unit 140: memory cell

Claims (19)

At least one memory cell consisting of a plurality of blocks; A mapping table having a programming number for each block is formed, and when programming a block to be recorded, the programming number for the block to be recorded is updated, and each block is based on the number of programming for each block. And a control unit for performing wear leveling on the flash memory device. The method of claim 1, The control unit, And selecting a block having a minimum value among the number of programming for each block as a recording target block. The method of claim 1, The control unit, And selecting a block having a programming number less than the average value as a recording target block based on the average value of the programming number for each block. The method of claim 1, The control unit, And selecting an unused block among the blocks as a recording target block. The method of claim 1, The control unit, And selecting a block having a minimum programming number for blocks belonging to any one of the memory cells as a recording target block. The method of claim 1, The control unit, And selecting a block having a less programming number as a recording target block based on an average value of programming times for blocks belonging to any one of the memory cells. The method of claim 1, The control unit, And selecting an unused block among blocks belonging to any one of the memory cells as a recording target block. The method of claim 1, The control unit, And updating the programming number of the block to be written, and then programming the block to be written. The method of claim 1, The mapping table is, And divided into a plurality of partial mapping tables according to the number of each block, and distributed in each of the blocks. 10. The method of claim 9, The control unit, And, upon resetting, forming the mapping table by combining the partial mapping tables. The method of claim 1, The control unit, And one of the blocks corresponding to a logical address (LBA) transmitted from a host by using the mapping table. The method of claim 1, The control unit, And a FTL processing unit for converting a logical address of a host for each block into a physical address for each block. The method of claim 1, The mapping table is, And a logical address of the host for each block, a physical address for the logical address, and a programming number for each block. The method of claim 1, And an interface unit provided between the control unit and the host, the interface unit converting data read in any one of the blocks according to the interface of the host. Selecting the least block among the plurality of blocks constituting each of the at least one memory cell, the least number of times of data programming; And And programming the data in the minimum block after updating the programming number of the minimum block in response to a host data write request. The method of claim 15, Selecting the minimum block, Referencing a mapping table having a number of data programming times for each block; And And selecting the block having the smallest number of data programming times of the host as the minimum block through the mapping table. The method of claim 16, The mapping table is, And having information about any one of a logical address transmitted from the host, a physical address of a block corresponding to the logical address among the respective blocks, and a programming number of a block having a physical address corresponding to the logical address. A data recording method of a flash memory device. The method of claim 15, The minimum block is, And a block having a minimum number of programming among blocks included in each of the memory cells. The method of claim 15, The minimum block is, And a block having the minimum programming number for the entire block included in each of the memory cells.
KR1020080114167A 2008-11-17 2008-11-17 Data programming device, and data programming method KR20100055201A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140057082A (en) * 2012-11-02 2014-05-12 삼성전자주식회사 Non-volatile memory system and host communicating with the same
US8996786B2 (en) 2011-01-28 2015-03-31 SK Hynix Inc. Nonvolatile memory system and block management method
CN113253925A (en) * 2021-04-30 2021-08-13 新华三大数据技术有限公司 Method and device for optimizing read-write performance

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8996786B2 (en) 2011-01-28 2015-03-31 SK Hynix Inc. Nonvolatile memory system and block management method
KR20140057082A (en) * 2012-11-02 2014-05-12 삼성전자주식회사 Non-volatile memory system and host communicating with the same
CN113253925A (en) * 2021-04-30 2021-08-13 新华三大数据技术有限公司 Method and device for optimizing read-write performance

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