KR20100054392A - Method for forming the pattern in semiconductor device - Google Patents

Method for forming the pattern in semiconductor device Download PDF

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Publication number
KR20100054392A
KR20100054392A KR1020080113303A KR20080113303A KR20100054392A KR 20100054392 A KR20100054392 A KR 20100054392A KR 1020080113303 A KR1020080113303 A KR 1020080113303A KR 20080113303 A KR20080113303 A KR 20080113303A KR 20100054392 A KR20100054392 A KR 20100054392A
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KR
South Korea
Prior art keywords
pattern
phase inversion
mask
semiconductor device
layer
Prior art date
Application number
KR1020080113303A
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Korean (ko)
Inventor
박준택
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080113303A priority Critical patent/KR20100054392A/en
Publication of KR20100054392A publication Critical patent/KR20100054392A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
    • G03F1/34—Phase-edge PSM, e.g. chromeless PSM; Preparation thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70466—Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)

Abstract

PURPOSE: A method for forming a pattern in a semiconductor device is provided to improve a process margin by performing a double exposure using a chrome-less phase shift mask and a binary mask. CONSTITUTION: In a method for forming a pattern in a semiconductor device, a first exposure process is performed by using a chrome-less phase shift mask(300). A second exposure process is performed by using a binary mask. The chrome-less phase shift mask is formed by latticing a first phase inversion layer(302) and a second phase shift layer(304).

Description

METHODS FOR FORMING THE PATTERN IN SEMICONDUCTOR DEVICE

The present invention relates to a method of forming a pattern of a semiconductor device. In particular, it is related with the pattern formation method using a chromeless phase inversion mask.

In general, a photomask used in a lithography process serves to form a desired pattern on a wafer by irradiating light on a pattern of the photomask and selectively transmitting light to the wafer. Such photomasks have generally used a binary mask including a light-transmitting region through which light is transmitted and a light-blocking region through which light is blocked by forming a light blocking layer pattern including chromium (Cr) on a substrate formed of a transparent material. . However, as the integration degree of the device increases, the size of the pattern becomes smaller and it is difficult to accurately implement a desired pattern due to diffraction or interference of light passing through the binary mask.

In order to overcome the difficulty in implementing the accurate pattern as described above, a light-transmissive pattern is formed on a phase shift mask or a transparent material substrate using a phase shift material having a transmittance of several percent, thereby forming the pattern only by phase difference of light. Research on forming a chromeless phase shift mask is ongoing.

Here, the chromeless phase inversion mask has a light transmittance of 100% in all the portions where the pattern is formed. Therefore, when light is irradiated, light is transmitted in both a portion having a pattern and a portion having no pattern. As the transmitted light passes through the mask, a mutual phase difference of 180 ° is formed, and a predetermined pattern is formed by mutual interference of light on the photoresist where the irradiated light is reached. Since the chromeless phase inversion mask is actually a pattern formed on the photoresist due to the interference caused by the phase difference of light between the pattern formed on the mask and the pattern, when the patterns are ideally arranged and formed, they are finer than the photomask using the conventional chromium light shielding film. There is an advantage to form an elaborate pattern.

1A and 1B illustrate a general exposure mask and a pattern forming method using the same.

Referring to FIG. 1A, the exposure mask 100 includes a light blocking pattern 120 in which a contact hole predetermined region 110 is defined on a quartz substrate (not shown). Here, the contact hole planning area 110 is a transmissive area, and the exposure mask of FIG. 1A is used to form the contact hole.

The light shielding pattern 120 is formed of a chromium layer. Herein, the pitch between the contact hole planning areas 110 may be defined as the X and Y axis pitches from the beginning of the contact hole planning area 110 to the beginning of the adjacent contact hole planning area 110. It is represented by 'P1' and 'P2'.

FIG. 1B illustrates a pattern formed using the exposure mask 100 of FIG. 1A. The contact hole pattern 130 is formed in a portion corresponding to the light transmissive region 110.

2A and 2B illustrate a chromeless phase inversion mask and a pattern forming method using the same.

Referring to FIG. 2A, the 180 ° phase inversion layer 210 and the 0 degree phase inversion layer 215 are formed in a lattice form. Here, the 180 degree phase shift layer 210 and the 0 degree phase shift layer 215 are disposed adjacent to each other. That is, a phase shifting layer 215 of 0 degrees is disposed between the phase shifting layers 210 of 180 degrees, and a phase shifting layer 210 of 180 degrees is disposed between the phase shifting layers 215 of 0 degrees.

Here, the X-axis pitch 'P3' and the Y-axis pitch 'P4' of the 180-degree phase shift layer 210 and the 0-degree phase shift layer 215 are formed twice as large as the pitch of the exposure mask shown in FIG. 1A. do. In this case, the size of the pitch is generally expressed by distances on the X and Y axes in the vertical and horizontal directions.

FIG. 2B illustrates the shape of a pattern formed using the chromeless phase inversion mask of FIG. 2A.

FIG. 2B illustrates contact hole pattern formation, in which contact hole patterns 230 are formed on the substrates corresponding to the phase inversion layer 210 at 180 degrees and the phase inversion layer 215 at 0 degrees. .

2B (ii) illustrates the pillar pattern formation, and the pillar pattern 230 is formed on the interface between the phase shift layer 210 at 180 degrees and the phase shift layer 215 at 0 degrees. The pillar pattern 230 may be formed using a higher energy than the process of forming the contact hole pattern 220 of FIG. 2B (iii).

Here, the chromeless phase inversion mask has a light transmittance of 100% for both the phase inversion layer 210 at 180 degrees and the phase inversion layer 215 at 0 degrees, and between the phase inversion layer 210 at 180 degrees and the phase inversion layer 215 at 0 degrees. Since the phase difference is 180 degrees, light is canceled at the boundary portion where the pattern and the pattern meet, and the light is reinforced at the center of the pattern.

Therefore, the contact hole pattern 220 is formed in both the phase shift layer 210 and the phase shift layer 215 at 180 degrees, or at the interface between the phase shift layer 210 and the phase shift layer 215 at 180 degrees. The pillar pattern 230 is formed.

FIG. 2C illustrates a simulation image using the chromeless phase inversion mask of FIG. 2A. Here, a simulation image in which a pillar pattern is formed is illustrated.

Referring to FIG. 2C, since the X-axis pitch and the Y-axis pitch of the chromeless phase inversion mask are different from each other, an asymmetric pillar pattern in which the up-down diameter is narrower than the left-right diameter, such as 'A', may be formed. have.

As described above, as the pitch is doubled by the use of the chromeless phase inversion mask, fine contact holes, which are not patternable, can be formed. However, since the X-axis pitch and the Y-axis pitch of the chromeless phase inversion mask are different from each other, a circular pattern is not formed and a pattern having unwanted asymmetry is formed. That is, there is a problem that adjustment of the two-dimensional shape of the pattern image is not easy.

The present invention seeks to improve process margins by introducing double exposure using chromeless phase inversion masks and binary masks.

The method of forming a pattern of a semiconductor device according to the present invention

Performing a first exposure process using a chromeless phase reversal mask, and performing a second exposure process using a binary mask,

In the chromeless phase inversion mask, a first phase inversion layer and a second phase inversion layer having a phase difference of 180 degrees are formed in a lattice form.

The binary mask is provided with a light blocking pattern having a line shape, and the light blocking pattern is formed of a chromium layer. In addition, the light blocking pattern of the line shape is characterized in that the X-axis direction or the Y-axis direction in the longitudinal direction.

In addition, the pattern forming method of a semiconductor device according to the present invention

Forming an etched layer and a photoresist film on the semiconductor substrate, performing a first exposure process using a chromeless phase inversion mask, performing a second exposure process using a binary mask, and developing the photoresist film. And forming a photoresist layer pattern by etching the etched layer using the photoresist pattern as a mask.

The chromeless phase inversion mask is characterized in that the first phase inversion layer and the second phase inversion layer are formed in a lattice form.

Here, the first exposure process uses a chromeless phase inversion mask in which a first phase inversion layer and a second phase inversion layer having a phase difference of 180 degrees are formed in a lattice form.

The binary mask is provided with a light blocking pattern having a line shape, and the light blocking pattern is formed of a chromium layer. In addition, the light blocking pattern of the line shape is characterized in that the X-axis direction or the Y-axis direction in the longitudinal direction.

The first exposure process uses a chromeless phase inversion mask in which a first phase inversion layer and a second phase inversion layer having a phase difference of 180 degrees are formed in a lattice form.

In addition, the secondary exposure process uses a binary mask provided with a line-shaped light blocking pattern, and the light blocking pattern is formed of a chromium layer. In addition, the light blocking pattern of the line shape is characterized in that the X-axis direction or the Y-axis direction in the longitudinal direction.

The etched layer pattern may be a contact hole pattern or a pillar pattern.

In the method of forming a semiconductor device according to the present invention, by performing a double exposure using a chromeless phase inversion mask and a binary mask, it is possible to easily change the line width of the X and Y axes of the pattern during pattern formation, thereby improving process margins. It works.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3A to 3C illustrate a method of forming a pattern of a semiconductor device according to the present invention. FIG. 3A illustrates a chromeless phase shift mask, and FIG. 3B illustrates a binary mask. 3c shows an image of a pattern formed by double exposure using a chromeless phase inversion mask and a binary mask.

Referring to Figures 3a to 3c it will be described a pattern forming method.

First, an etched layer (not shown) is formed on a semiconductor substrate (not shown), and a photosensitive film (not shown) is coated on the etched layer (not shown).

Next, a primary exposure process is performed using the chromeless phase inversion mask 300 of FIG. 3A. In the chromeless phase inversion mask 300, the first phase inversion layer 302 and the second phase inversion layer 304 are formed in a lattice form. That is, the first phase inversion layer 302 and the second phase inversion layer 304 are formed adjacent to each other.

The first phase inversion layer 302 and the second phase inversion layer 304 have a phase difference of 180 degrees. For example, the first phase inversion layer 302 is a 180 degree phase inversion region, and the second phase inversion layer 304 is a zero degree phase inversion region.

A contact hole pattern may be formed according to the degree of exposure energy used in the first exposure process, or a pillar pattern in the form of a pillar may be formed. For example, when the exposure process is performed above a certain exposure energy, a large amount of light is transmitted through the first phase inversion layer 302 and the second phase inversion layer 304 to form a contact hole pattern, and the exposure is performed at a predetermined exposure energy or less. When the process is performed, a pillar pattern is formed on the interface between the first phase inversion layer 302 and the second phase inversion layer 304.

Next, the secondary exposure process is performed using the binary mask 310 of FIG. 3B. The binary mask 310 uses a binary mask 310 having a light shielding pattern 312 in the form of a line having the X-axis direction in the longitudinal direction as shown in FIG. 3B (iii) or as shown in FIG. 3B (ii). As described above, a binary mask 310 having a light blocking pattern 314 having a line shape having a Y-axis direction in the longitudinal direction is used.

Next, a development process is performed on the photosensitive film (not shown) subjected to the double exposure process to form a photosensitive film pattern (not shown).

FIG. 3C illustrates an image of a pattern formed through the double exposure process using the mask of FIGS. 3A and 3B. Although only the image of the pillar pattern is illustrated here, the contact hole pattern may be formed according to the degree of exposure energy used in the primary exposure process.

FIG. 3C (iii) shows a pattern image when the binary mask 310 of FIG. 3b (iii) is used. Since the binary mask 310 of FIG. 3B has a light-shielding pattern 312 in the form of a line having the X-axis direction in the longitudinal direction, a pillar having a longer line width in the X-axis direction than the line width in the Y-axis direction is shown. The pattern 320a is formed.

 FIG. 3C (ii) shows a pattern image when the binary mask 310 of FIG. 3B (ii) is used. Since the binary mask 310 of FIG. 3B (ii) includes a light shielding pattern 314 having a line shape in the Y direction, the pillar pattern having a longer line width in the Y direction than the line width in the X axis direction is shown. 320b is formed.

As described above, the process margin can be improved by performing a double exposure using a binary mask provided with a chromeless phase inversion mask and a light blocking pattern in a line shape to adjust line widths of the X and Y axes of the pattern.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A and 1B illustrate a general exposure mask and a pattern forming method using the same.

2A and 2B illustrate a chromeless phase inversion mask and a pattern forming method using the same.

3A to 3C illustrate a method of forming a pattern of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

300: chromeless phase inversion mask 302: first phase inversion layer

304: second phase inversion layer 310: binary mask

312 and 314: Light shielding pattern 320a and 320b: Pillar pattern

Claims (15)

Performing a first exposure process using a chromeless phase inversion mask; And Step of proceeding the second exposure process using a binary mask Pattern forming method of a semiconductor device comprising a. The method of claim 1, The chromeless phase inversion mask is a pattern forming method of a semiconductor device, characterized in that the first phase inversion layer and the second phase inversion layer is formed in a lattice form. The method of claim 2, And the first phase inversion layer and the second phase inversion layer have a phase difference of 180 degrees. The method of claim 1, The binary mask is a pattern forming method of a semiconductor device, characterized in that the line-shaped light-shielding pattern is provided. The method of claim 4, wherein The light shielding pattern is a pattern forming method of a semiconductor device, characterized in that formed by a chromium layer. The method of claim 4, wherein The light blocking pattern in the form of a line is a pattern forming method of a semiconductor device, characterized in that the X-axis direction in the longitudinal direction. The method of claim 4, wherein The light blocking pattern in the form of a line is a pattern forming method of a semiconductor device, characterized in that the Y-axis direction in the longitudinal direction. Forming an etched layer and a photosensitive film on the semiconductor substrate; Performing a first exposure process using a chromeless phase inversion mask; Performing a second exposure process using a binary mask; Developing the photoresist to form a photoresist pattern; And Etching the etched layer using the photoresist pattern as a mask to form an etched layer pattern Pattern forming method of a semiconductor device comprising a. The method of claim 8, The chromeless phase inversion mask is a pattern formation method of a semiconductor device, characterized in that the first phase inversion layer and the second phase inversion layer is formed in a grid form. The method of claim 9, And the first phase inversion layer and the second phase inversion layer have a phase difference of 180 degrees. The method of claim 8, The binary mask is a pattern forming method of a semiconductor device, characterized in that the line-shaped light-shielding pattern is provided. The method of claim 11, The light shielding pattern is a pattern forming method of a semiconductor device, characterized in that formed by a chromium layer. The method of claim 11, The light blocking pattern in the form of a line is a pattern forming method of a semiconductor device, characterized in that the X-axis direction in the longitudinal direction. The method of claim 11, The light blocking pattern in the form of a line is a pattern forming method of a semiconductor device, characterized in that the Y-axis direction in the longitudinal direction. The method of claim 8, The etched layer pattern may be a contact hole pattern or a pillar pattern.
KR1020080113303A 2008-11-14 2008-11-14 Method for forming the pattern in semiconductor device KR20100054392A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298956B2 (en) 2010-12-21 2012-10-30 SK Hynix Inc. Method for fabricating fine pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8298956B2 (en) 2010-12-21 2012-10-30 SK Hynix Inc. Method for fabricating fine pattern

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