KR20100054349A - Generating circuir and control method for internal voltage of semiconductor memory device - Google Patents

Generating circuir and control method for internal voltage of semiconductor memory device Download PDF

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KR20100054349A
KR20100054349A KR1020080113249A KR20080113249A KR20100054349A KR 20100054349 A KR20100054349 A KR 20100054349A KR 1020080113249 A KR1020080113249 A KR 1020080113249A KR 20080113249 A KR20080113249 A KR 20080113249A KR 20100054349 A KR20100054349 A KR 20100054349A
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South Korea
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voltage
external power
power supply
driver
level
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KR1020080113249A
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Korean (ko)
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김명진
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주식회사 하이닉스반도체
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Publication of KR20100054349A publication Critical patent/KR20100054349A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators

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  • Power Engineering (AREA)
  • Dram (AREA)

Abstract

PURPOSE: An internal voltage generating circuit and a control method thereof are provided to improve the current driving capability by controlling the number of driving elements installed in a driver part in a low external power voltage region. CONSTITUTION: A voltage detector(100) detects whether an external power voltage is lower than the normal level. The voltage detector generates a low external power voltage region enable signal when the external power voltage is lower than the normal level. An internal voltage output driver(200) controls the number of driver elements. A comparison part compares a reference voltage(VREFC) and the external power voltage. A control switching part enables the comparison unit. A pre-charge part pre-charges the external supply power source.

Description

GENERATING CIRCUIR AND CONTROL METHOD FOR INTERNAL VOLTAGE OF SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a circuit design in a semiconductor memory device, and more particularly, to an internal voltage generation circuit and a control method capable of improving driving capability.

The semiconductor memory device is used in various fields, but one of them is used to store various kinds of data. Since such semiconductor memory devices are used in various portable devices, including desktop computers and notebook computers, large capacity, high speed, small size, and low power are required.

As a method for designing a semiconductor memory device according to the low power, a technology for minimizing current consumption in a core area of a memory has been proposed. The core region is composed of a memory cell, a bit line, and a word line, and is designed according to an extremely fine design rule. Therefore, in order to design a semiconductor memory device that is extremely fine and high frequency operation, the power supply voltage is basically low.

On the other hand, the semiconductor memory device generates and uses power of a required size inside the device using an external power supply voltage of a predetermined value or less. In particular, in the case of a memory device using a bit line sensing amplifier such as DRAM, a core voltage Vcore is used to detect cell data. When a word line is activated, data of a plurality of memory cells connected to the word line is transferred to the bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines. When these thousands of bitline sense amplifiers operate at the same time, they use pull-up power lines and consume large amounts of current from the core voltage stages used.

FIG. 1 shows a block diagram of an internal voltage generation circuit of a conventional semiconductor memory device, and FIG. 2 shows a detailed block diagram of a conventional internal voltage generation circuit shown in FIG.

The illustrated internal voltage generator circuit is driven by an active enable signal ACT_EN, which compares a reference voltage with a feedback core voltage and generates a value corresponding to the difference, VCORE DETECTOR 21; The driver 22 is driven by an active enable signal ACT_EN and generates a stable core voltage based on the detected value of the core voltage detector 21, and the core voltage output from the driver 22 is used. And a voltage divider (VOLTAGE HALF DIVIDER) 23 for generating a core voltage (1/2 of the output core voltage) to be fed back to the core voltage detector 21.

The internal voltage generation circuit of the semiconductor memory device having the above configuration starts operation when the active enable signal ACT_EN generated when the bank operates is high. The active enable signal is input to the core voltage detector 21, the driver 22, and the voltage divider 23 to control the NMOS transistors connecting the components and the ground power source to the turn-on state. Form a current path to ground power.

The core voltage detector 21 inputs a reference voltage VREFC to an NMOS transistor for a first input and a half core voltage HALF VOCRE LEVEL to an NMOS transistor for a second input.

If the half-core voltage is higher than the reference voltage, the NMOS transistor to which the half-core voltage is input is strongly turned on to lower the level of the A node. When the voltage of the node A decreases, the PMOS transistor M1 is turned on to raise the level of the node B to the supply voltage VDD. In this way, while the B node maintains the supply voltage level, the PMOS transistors in the driver 22 are turned off while the core voltage generation in the driver 22 is blocked.

On the contrary, when the half core voltage is lower than the reference voltage, the NMOS transistor to which the half core voltage is input is weakly turned on, so that the level of the A node is higher than the C node controlled by the reference voltage. As the voltage of the C node decreases, the PMOS transistor M2 is turned on, and the NMOS transistors N1 and N2 are subsequently turned on. As the NMOS transistor N2 is turned on, the level of the node B is lowered. As a result, the PMOS transistor in the driver 22 is turned on to maintain the lowered core voltage level at the normal level.

As described above, the internal voltage generation circuit of the conventional semiconductor memory device is operated to maintain the core voltage level while repeating the turn-on / off operation of the driver 22 until the feedback voltage and the reference voltage are the same. In the conventional core voltage generation circuit operated as described above, the same control is performed regardless of whether the external power supply voltage is higher or lower than the reference power supply voltage. Therefore, the generated core voltage has a problem in that the output level changes when the input external power supply voltage is high and low when the input voltage is high.

In particular, the internal voltage generation circuit of the conventional semiconductor memory device has no method of reinforcing the driver's driving capability reduction when the external power supply voltage is lower than the level to be input in the circuit design. That is, when the external power supply voltage is a low voltage, a problem arises that the target current level of the output voltage falls because the minimum current driving capability required for the operation of the semiconductor memory device is not satisfied. These problems have been developed to reduce the data transfer speed and lower the data sensing ability, thereby causing a defect of the semiconductor memory device.

Accordingly, an object of the present invention is to provide an internal voltage generation circuit and a control method of a semiconductor memory device capable of generating stable core voltage even when an external external power supply voltage is low.

The internal voltage generating circuit of the semiconductor memory device according to the present invention for achieving the above object, detects whether the external power supply voltage is lower than the normal level, when the external power supply voltage is lower than the normal level, low external power supply voltage A voltage detector for generating a region enable signal; When the voltage detector generates a low external power supply voltage region enable signal, the voltage detector includes an internal voltage output driver for controlling the number of driving devices.

In addition, the internal voltage generation circuit of the semiconductor memory device according to another embodiment of the present invention detects whether the external power supply voltage is lower than the normal level and, when the external power supply voltage is lower than the normal level, the low external power supply voltage range. An external power supply voltage detector for generating an enable signal; An internal voltage output driver configured to enlarge and control the number of driving elements when the low voltage source enable signal is generated by the voltage detector; And an internal voltage detector for controlling the operation of the driver to compare the internal voltage generated from the output driver with a reference voltage so that the internal voltage output from the driver maintains a constant level.

The internal voltage generation control method of the semiconductor memory device according to the present invention detects whether the external power supply voltage is lower than the normal level, and when the external power supply voltage is lower than the normal level, the low external power supply voltage area enable signal. Generating a first step; A second step of expanding and controlling the number of driving elements when the low external power supply voltage region enable signal is generated in the first step; A third step of comparing an internal voltage generated through the driving device with a reference voltage; And a fourth step of adjusting the internal voltage compared in the third step to maintain a constant level by using the driving element controlled in the second step.

The present invention expands and controls the number of driving elements configured in the driver unit in the low external power supply voltage range, thereby increasing the current driving capability than in the normal external power supply voltage range. Therefore, the present invention can obtain the effect that it is possible to generate a stable core voltage irrespective of the magnitude of the external power supply voltage. In addition, the present invention prevents a drastic deterioration of the current drive ability even in a low voltage region, thereby reducing the speed of the transmission signal and the DEVELOP TIME for data sensing.

Hereinafter, an embodiment of an internal voltage generation circuit of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention.

As illustrated in FIG. 3, the present invention includes a VDD detector 400 that monitors an external power supply voltage VDD and generates a low external power supply voltage enable signal DVDD according to its magnitude. In addition, the present invention inputs the DVDD which is an enable signal generated in the low external power supply voltage region detected by the VDD detector 400, and further turns on the driving MOS transistor in the low external power supply voltage region to thereby turn on the current drive ability. Driver 200 to increase DRIVABILITY). In addition, the present invention is driven by the active enable signal (ACT_EN) to compare the reference voltage and the feedback core voltage, the core voltage detector (VCORE DETECTOR) (100) for generating a value corresponding to the difference, and the driver 200 And a voltage divider (VOLTAGE HALF DIVIDER; 300) for generating a core voltage (1/2 of an output core voltage) to be fed back to the core voltage detector 100 using the core voltage output from the core voltage detector 100.

According to the above configuration, the internal voltage generation circuit of the present invention first monitors the external power supply voltage VDD input from the VDD detector 400 to generate a low external power supply voltage enable signal DVDD. The VDD detector 400 uses the down-converted DC level as a reference power and enables the DVDD output signal when the level of the input external supply power is lower than the reference power level by comparing the level with the input external power supply. (High level).

The DVDD enable signal generated by the VDD detector 400 is input to the driver 200. The driver 200 further turns on the driving MOS transistor to be used for generating the core voltage by the DVDD enable signal. Therefore, the number of MOS transistors driven in the low external power supply voltage region becomes more than the number of MOS transistors driven in the normal external power supply voltage region. This control causes the driver 200 to increase the current drive ability in the low external power supply voltage range.

When the active enable signal ACT_EN generated when the bank operates is high, the operation starts. The active enable signal is input to the core voltage detector 100, the driver 200, and the voltage divider 300 to control the NMOS transistors connecting the components and the ground power source to the turn-on state, respectively. Form a current path to ground power.

The voltage divider 300 divides the core voltage output from the driver 200. At this time, the divided voltage is determined to be about 1/2 of the output core voltage. The distributed feedback voltage is input to the core voltage detector 100.

The core voltage detector 100 inputs a reference voltage VREFC to an NMOS transistor for a first input and a half core voltage HALF VOCRE LEVEL to an NMOS transistor for a second input.

If the half core voltage is higher than the reference voltage, the level of the node connected to the driver 300 is maintained by the current mirror characteristic. When the voltage of the connection node with the driver 300 is high, core voltage generation in the driver 200 is blocked while driving MOS transistors in the driver 300 are turned off.

On the contrary, when the half core voltage is lower than the reference voltage, the level of the node connected to the driver 300 is kept low due to the current mirror characteristic. When the voltage of the connection node with the driver 300 is low, the driving MOS transistors in the driver 300 maintain the turn-on state and maintain the lowered core voltage level at the normal level again.

In this process, since the number of MOS transistors driven in the driver 300 increases due to the DVDD enable signal provided by the VDD detector 400 in a region where the external power supply voltage is lower than the normal level. It is possible to increase the current drive ability.

Next, the operation process described above will be described in more detail with reference to a detailed circuit diagram of an internal voltage generation circuit of a semiconductor memory device according to the present invention.

FIG. 4 is a detailed circuit diagram of the internal voltage generation circuit shown in FIG. 3, and FIG. 5 monitors the external power supply voltage VDD shown in FIG. 3 and generates a low external power supply voltage enable signal DVDD according to its magnitude. A detailed circuit diagram of the VDD detector is shown.

As shown in Fig. 4, the core voltage detector 100 has a dual current mirror type. And it is configured to be enabled by the active enable signal (ACT_EN) is enabled during the bank operation. The active enable signal is also configured to be applied in duplicate. And it consists of the structure of the comparator which differentially compares the feedback voltage comprised with the half core voltage which is 1/2 level of the core voltage terminal potential, and the reference voltage VREFC (half level of target core voltage; 0.75V).

As shown in FIG. 4, the driver 300 includes a plurality of driving MOS transistors that are driven to generate a core voltage. The driving MOS transistors are composed of PMOS transistors. In the illustrated embodiment, three driving MOS transistors are formed of 247, 248, and 249. Among these, the PMOS transistor 249 can be driven only by a DVDD signal generated in a low external power supply voltage region. That is, when the external power supply voltage level is a normal level, two PMOS transistors 247 and 248 operate as driving MOS transistors, and when the external power supply voltage level is a low level, three PMOS transistors 247, 248 and 249 operate as driving MOS transistors. do. The driver 300 is configured to be enabled by an active enable signal ACT_EN enabled during bank operation.

As shown in FIG. 4, the voltage divider 300 divides a voltage of a core voltage output from the driver 300 and a level 1/2 of the core voltage potential to be used for monitoring the output core voltage. A feedback voltage is generated and transferred to the core voltage detector 100. The voltage divider 300 distributes the voltage using a transistor. In addition, the voltage divider 300 is also enabled by the active enable signal ACT_EN.

The VDD detector 400 is illustrated in FIG. 5. As shown in the drawing, the VDD detector 400 sets the down-converted DC level as a reference power supply, and compares the level with the inputted external supply power supply when the level of the inputted external supply power supply is lower than the reference power supply level. Enable (high level) the output signal. The VDD detector 400 is configured to be enabled by an enable signal TD4SVDET for detecting an external power supply level.

Looking at the detailed configuration of the VDD detector 400 using one level detector 450, the TD4SVDET control signal turns on the NMOS transistor 407 to control the formation of a current path to the ground power source. . A bias voltage may be applied to the gate terminals of the NMOS transistors 405 and 406 connected to the MOS transistor 407. In the VDD detector 400, the reference power input terminal is composed of the NMOS transistor 400, and the input terminal of the external power supply is composed of the NMOS transistor 404. The PMOS transistors 401 and 402 connecting the gate ends of each other are configured in a current mirror type to form a precharge unit, and the detection value of the VDD detector 400 configured as described above is a digital signal through a latch unit consisting of a pair of inverters 412 and 413. Is converted to and printed.

As shown in FIG. 5, the VDD detector 400 may be configured as one level detector as shown at 450, and may be configured in the form of a plurality of level detectors. It may be. In the case where a plurality of level detectors are configured as described above, the DVDD enable signal may be generated at various VDD levels according to the magnitude ratio of the reference voltage level or the MOS transistors. An exemplary diagram simulating this is shown in FIG.

Next, an operation process of the internal voltage generation circuit of the semiconductor memory device having the above configuration will be described.

First, in order for the internal voltage generation circuit to operate in the present invention, it is necessary to detect the level of the input external power supply voltage VDD to determine whether the external power supply voltage is a low level region or a normal level region. The level detection value is represented by a low external power supply voltage enable signal. The driving MOS transistor of the core voltage generating driver is selectively controlled based on the detected level value of the external power supply voltage.

That is, the VDD detector 400 compares the level of the input external power supply voltage by using the DC voltage as a reference voltage. At this time, when the level of the external power supply voltage is lower than the reference voltage, the VDD detector 400 generates a low external power supply voltage region enable signal DVDD having a high level.

The VDD detector 400 generates a DVDD control signal as a high signal, and the generated high level signal controls the PMOS transistor 249 to be turned on through the switch 208 in the driver 200. That is, the PMOS transistor 249 should be set to be turned on by the high level signal supplied from the VDD detector 400. When the high level signal is output from the VDD detector 400, the high level signal is received through the switch 208 and is turned on to provide the supply power supply VDD to the core voltage terminal VCORE. .

Prior to this, the driving MOS transistors 247 and 248 in the driver 200 are controlled to be in a state in which they can be driven while the VDD power is supplied and the active enable signal ACT_EN is applied. Therefore, in the low external power supply voltage region, all of the driving MOS transistors 247, 248, and 249 provided in the driver 200 are in a driving standby state.

On the other hand, when the active enable signal ACT_EN generated when the bank operates is high, the operation starts. The active enable signal is input to the core voltage detector 100, the driver 200, and the voltage divider 300 to control the NMOS transistors connecting the components and the ground power source to the turn-on state, respectively. Form a current path to ground power.

The voltage divider 300 divides the core voltage output from the driver 200. At this time, the divided voltage is determined to be about 1/2 of the output core voltage. The distributed feedback voltage is input to the core voltage detector 100.

The core voltage detector 100 inputs a reference voltage VREFC to the NMOS transistor 203 for the first input and a half core voltage HALF VOCRE LEVEL to the NMOS transistor 224 for the second input. do.

If the half core voltage is higher than the reference voltage, the NMOS transistor 224 to which the half core voltage is input is strongly turned on to lower the level of the E node. When the voltage of the E node decreases, the PMOS transistor 245 is turned on to raise the level of the F node to the supply voltage VDD. In this way, while the F node maintains the supply voltage level, the PMOS transistors 247, 248, and 249, which are the driving MOS transistors in the driver 200, are turned off while the core voltage generation in the driver 200 is blocked.

On the contrary, when the half core voltage is lower than the reference voltage, the NMOS transistor 224 to which the half core voltage is input is weakly turned on, so that the level of the E node is higher than the D node controlled by the reference voltage. The PMOS transistor 240 is turned on as the voltage at the D node is lowered, and the NMOS transistors 220 and 225 are turned on in turn. As the NMOS transistor 225 is turned on, the level of the F node is lowered. As a result, the PMOS transistors 247, 248, and 249 in the driver 200 are turned on to maintain the core voltage level lowered back to the normal level.

As such, the number of driving MOS transistors of the driver 200 in the low external power supply voltage region is greater than the number of driving MOS transistors operating in the normal external power supply voltage region. Therefore, the current drive ability of the core voltage output from the driver 200 is increased.

Next, the VDD detector 400 compares the level magnitude of the input external power supply voltage by using the DC voltage as a reference voltage. At this time, when the level of the external power supply voltage is higher than the reference voltage, the VDD detector 400 controls the low external power supply voltage area control signal to a low state.

When the VDD detector 400 generates the DVDD control signal as a low signal, the low level signal provided through the switch 208 in the driver 200 controls the PMOS transistor 249 to be turned off.

Prior to this, the driving MOS transistors 247 and 248 in the driver 200 are controlled to be in a state in which they can be driven while the VDD power is supplied and the active enable signal ACT_EN is applied. Accordingly, in the normal external power supply voltage region, only the driving MOS transistors 247 and 248 are in a driving standby state among all the driving MOS transistors provided in the driver 200.

When the active enable signal ACT_EN generated when the bank operates is high, the operation starts. The active enable signal is input to the core voltage detector 100, the driver 200, and the voltage divider 300 to control the NMOS transistors connecting the components and the ground power source to the turn-on state, respectively. Form a current path to ground power.

The voltage divider 300 divides the core voltage output from the driver 200. At this time, the divided voltage is determined to be about 1/2 of the output core voltage. The distributed feedback voltage is input to the core voltage detector 100.

The core voltage detector 100 inputs a reference voltage VREFC to an NMOS transistor for a first input and a half core voltage HALF VOCRE LEVEL to an NMOS transistor for a second input.

If the half core voltage is higher than the reference voltage, the NMOS transistor 224 to which the half core voltage is input is strongly turned on to lower the level of the E node. When the voltage of the E node decreases, the PMOS transistor 245 is turned on to raise the level of the F node to the supply voltage VDD. In this way, while the F node maintains the supply voltage level, the PMOS transistors 247 and 248, which are the driving MOS transistors in the driver 200, are turned off while the core voltage generation in the driver 200 is blocked.

On the contrary, when the half core voltage is lower than the reference voltage, the NMOS transistor 224 to which the half core voltage is input is weakly turned on, so that the level of the E node is higher than the D node controlled by the reference voltage. The PMOS transistor 240 is turned on as the voltage at the D node is lowered, and the NMOS transistors 220 and 225 are turned on in turn. As the NMOS transistor 225 is turned on, the level of the F node is lowered. As a result, the PMOS transistors 247 and 248 in the driver 200 are turned on to maintain the core voltage level lowered back to the normal level. As described above, the number of driving MOS transistors of the driver 200 in the normal external power supply voltage region is partially controlled.

The above-described preferred embodiment of the present invention is disclosed for the purpose of illustration, and may be applied to a case where a stable core voltage is generated regardless of a change in an external power supply voltage. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is an internal voltage generation block diagram according to the prior art;

2 is a detailed circuit diagram of an internal voltage according to the prior art;

3 is a block diagram of an internal voltage generation circuit according to the present invention;

4 is a detailed circuit diagram of an internal voltage generation circuit according to an embodiment of the present invention.

5 is a detailed circuit diagram of a VDD detector according to the present invention;

6 is an exemplary diagram simulating a VDD detector.

Explanation of symbols on the main parts of the drawings

100: core voltage detector 200: driver

300: voltage divider 400: VDD detector

Claims (22)

A voltage detector for detecting whether the external power supply voltage is lower than the normal level and generating a low external power supply voltage region enable signal when the external power supply voltage is lower than the normal level; And an internal voltage output driver configured to enlarge and control the number of driving elements when the low voltage source enable signal is generated by the voltage detector. The method of claim 1, The voltage detector may include a comparison unit comparing a reference voltage and an external power supply voltage; A control switching unit for enabling the comparison unit; And a precharge unit configured to precharge an external supply power so that the comparator can operate. The method of claim 2, The voltage detector may detect an external power supply voltage level in various areas according to a reference voltage level input to the comparator. The method of claim 3, wherein The reference voltage level of the comparison unit is a down-converted DC level, the internal voltage generation circuit of the semiconductor memory device. The method of claim 2, The voltage detector is capable of detecting an external power supply voltage level in various areas according to the size of a driving element of the comparator. The method of claim 4, wherein And the MOS transistor is used as a driving element of the comparing unit. The method of claim 2, The voltage detector further comprises a latch unit for latching the output of the comparison unit. The method of claim 1, The driver may include a first driver for generating an internal voltage; And a second driver driven by the low external power supply voltage region enable signal of the voltage detector. The method of claim 8, And the driver further comprises an enable unit for enabling the driver to operate according to a bank active enable signal. The method of claim 8, The second driving unit may include a switch unit configured to perform a switching operation by a low external power supply voltage region enable signal; And a driving element driven by the operation control of the switch unit. The method of claim 10, And the drive element is a PMOS transistor. An external power supply voltage detector for detecting whether the external power supply voltage is lower than the normal level and generating a low external power supply voltage region enable signal when the external power supply voltage is lower than the normal level; An internal voltage output driver configured to enlarge and control the number of driving elements when the low voltage source enable signal is generated by the voltage detector; And an internal voltage detector for controlling the operation of the driver such that the internal voltage output from the driver is maintained at a predetermined level by comparing the internal voltage generated from the output driver with a reference voltage. Internal voltage generator circuit. 13. The method of claim 12, The internal voltage detector may include a comparator configured to compare an internal voltage and a reference voltage; A precharge unit which precharges an external power supply voltage so that the comparison unit can be operated; And an enable unit for enabling the operation of the comparator. The method of claim 13, And the comparing unit is configured as a current mirror type. The method of claim 13, And the enable unit is operated by a bank active enable signal. 13. The method of claim 12, And a voltage divider configured to divide the voltage of the internal voltage generated by the output driver and feed it back to the internal voltage detector. The method of claim 16, The voltage divider may include: a voltage divider configured to voltage divide the output voltage of the driver; And an enable part for enabling the operation of the voltage divider. The method of claim 17, And the enable unit is operated by a bank active enable signal. The method of claim 16, And the voltage divider uses a transistor. The method according to any one of claims 12 to 19, And the internal voltage is a core voltage. A first step of detecting whether the external power supply voltage is lower than the normal level, and generating a low external power supply voltage region enable signal when the external power supply voltage is lower than the normal level; A second step of expanding and controlling the number of driving elements when the low external power supply voltage region enable signal is generated in the first step; A third step of comparing an internal voltage generated through the driving device with a reference voltage; And a fourth step of controlling the internal voltage compared in the third step to maintain a constant level by using the driving element controlled in the second step. . The method of claim 21, And a fifth step of dividing the internal voltage generated through the driving device to provide an internal voltage for comparison with a reference voltage in the third step.
KR1020080113249A 2008-11-14 2008-11-14 Generating circuir and control method for internal voltage of semiconductor memory device KR20100054349A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761317B2 (en) 2014-12-18 2017-09-12 SK Hynix Inc. Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761317B2 (en) 2014-12-18 2017-09-12 SK Hynix Inc. Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof
US10008274B2 (en) 2014-12-18 2018-06-26 SK Hynix Inc. Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof

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