KR20100052060A - Thin film transistor and flat panel display device having the same - Google Patents

Abstract

PURPOSE: A thin film transistor and flat panel display device having the same are provided to have gate electrode formed by aluminum alloy, thereby embodying a surface shape in good condition and providing low resistivity. CONSTITUTION: A gate electrode(12) is formed into aluminum alloy on a substrate. The aluminum alloy comprises nickl and lanthanum which has high stability in heat and chemically. A active layer(14) is insulated from the gate electrode by a gate insulation layer(13). A source electrode(16a) and a drain electrode(16b) is connected to the active layer. A insulation layer is formed between the active layer and the source and drain electrode, and has contact hole. The source and drain electrode is connected to the active layer through the contact hole.

Description

Thin film transistor and flat panel display device having the same {Thin film transistor and flat panel display device having the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a flat panel display device having the same, and more particularly, to a thin film transistor and a flat display device including the same, in which the resistivity of the gate electrode and the wiring can be reduced.

The thin film transistor includes an active layer providing a channel region, a source region, and a drain region, and a gate electrode overlapping the channel region and electrically insulated from the active layer by the gate insulating layer.

In recent years, thin film transistors have been applied to flat panel displays such as liquid crystal displays (LCDs) and organic light emitting displays (AMOLEDs) as well as semiconductor integrated circuits.

However, as the resolution of a flat panel display device increases and becomes larger, it is difficult to stably secure electrical characteristics due to an increase in resistivity of electrodes and wirings of a thin film transistor.

In general, in the flat panel display, the gate electrode of the thin film transistor is formed of a metal such as molybdenum (Mo), aluminum (Al), neodymium (Nd), tungsten (W) or an alloy thereof, but these metals have a specific resistance of 11 Ω. As high as cm and low thermal and chemical stability, it is difficult to secure stable electrical properties and manufacturing process.

An object of the present invention is to provide a thin film transistor having a low resistivity of a gate electrode and a flat panel display device having the same.

Another object of the present invention is to provide a thin film transistor having high thermal and chemical stability of a gate electrode and a flat panel display device having the same.

A thin film transistor according to an aspect of the present invention for achieving the above object is a substrate; A gate electrode formed of an aluminum alloy including nickel and lanthanum on the substrate; An active layer insulated from the gate electrode by a gate insulating layer; And a source electrode and a drain electrode in contact with the active layer.

According to another aspect of the present invention, there is provided a flat panel display device including a thin film transistor connected between a first conductive line and a second conductive line crossing each other, and the first conductive line and the second conductive line. A first substrate having a thin film transistor and a first electrode connected to the thin film transistor; A second substrate disposed to face the first substrate and having a second electrode formed thereon; And a liquid crystal layer injected into a space between the first substrate and the second substrate, wherein the thin film transistor comprises: a gate electrode formed of an aluminum alloy including nickel and lanthanum on the first substrate; An active layer insulated from the gate electrode by a gate insulating layer; And a source electrode and a drain electrode in contact with the active layer.

According to another aspect of the present invention, there is provided a flat panel display device including a thin film transistor, wherein a first conductive line and a second conductive line intersecting each other, and the first conductive line and the second conductive line intersect each other. A first substrate having a connected thin film transistor and an organic light emitting display device connected to the thin film transistor; And a second substrate disposed to face the first substrate, wherein the thin film transistor comprises: a gate electrode formed of an aluminum alloy including nickel and lanthanum on the first substrate; An active layer insulated from the gate electrode by a gate insulating layer; And a source electrode and a drain electrode in contact with the active layer.

The thin film transistor of the present invention has a gate electrode formed of an aluminum alloy containing nickel and lanthanum. Aluminum alloys, including nickel and lanthanum, have good thermal and chemical stability, which results in good surface morphology, ease of manufacture, and low resistivity. Therefore, it is easy to implement a thin film transistor and a large display device having excellent electrical characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided to those skilled in the art to fully understand the present invention, and may be modified in various forms, and the scope of the present invention is limited to the embodiments described below. no.

1A to 1C are cross-sectional views illustrating an embodiment of a thin film transistor according to the present invention, and illustrate a thin film transistor having a bottom gate structure.

Referring to FIG. 1A, a buffer layer 11 is formed on a substrate 10, and a gate electrode 12 is formed on the buffer layer 11. The gate insulating layer 13 is formed on the top including the gate electrode 12, and the active layer 14 is formed on the gate insulating layer 13. The active layer 14 provides a channel region, a source region and a drain region, and the channel region overlaps the gate electrode 12. Source and drain electrodes 16a and 16b are in contact with the active layer 14 of the source and drain regions.

The gate electrode 12 is formed of an aluminum (Al) alloy including nickel (Ni) and lanthanum (La), and the active layer 14 is a semiconductor such as polysilicon (poly-Si) or a compound semiconductor containing oxygen. Is formed.

Although FIG. 1A illustrates a structure in which the source and drain electrodes 16a and 16b are in direct contact with the active layer 14 of the source and drain regions, the insulating layer 15 is disposed over the entire layer including the active layer 14 as shown in FIG. 1B. ) May be formed, and the source and drain electrodes 16a and 16b may be in contact with the active layer 14 of the source and drain regions through the contact holes formed in the insulating layer 15.

In addition, taking the structure of FIG. 1B as an example, at least one of the lower and upper surfaces of the gate electrode 12 as shown in FIG. 1C for stable interface contact with the buffer layer 11 and the gate insulating layer 13. Barrier layers 17a and 17b may be formed. The barrier layers 17a and 17b are formed of a metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW).

2A to 2C are cross-sectional views for describing another embodiment of the thin film transistor according to the present invention, and illustrate a thin film transistor having a top gate structure.

Referring to FIG. 2A, a buffer layer 21 is formed on a substrate 20, and source and drain electrodes 22a and 22b are formed on the buffer layer 21. The active layer 23 is formed on the substrate 20 including the source and drain electrodes 22a and 22b, and the gate insulating layer 25 is formed on the upper portion including the active layer 23. The gate electrode 26 is formed on the gate insulating layer 25 on the active layer 23. The active layer 23 provides a channel region, a source region and a drain region, the source and drain regions are in contact with the source and drain electrodes 22a and 22b, and the channel region overlaps the gate electrode 12. The active layer 23 is formed of a semiconductor such as polysilicon (poly-Si) or a compound semiconductor containing oxygen, and the gate electrode 26 is made of an aluminum (Al) alloy including nickel (Ni) and lanthanum (La). Is formed.

Referring to FIG. 2B, a buffer layer 31 is formed on the substrate 30, and an active layer 32 is formed on the buffer layer 31. The gate insulating layer 33 is formed on the active layer 32, and the gate electrode 34 is formed on the gate insulating layer 33 on the active layer 32. The insulating layer 35 is formed on the entire surface including the gate electrode 34, and the source and drain electrodes 36a and 36b are formed to contact the active layer 32 through the contact hole formed in the insulating layer 35. .

The active layer 32 provides a channel region, a source region and a drain region, the channel region overlaps the gate electrode 34, and the source and drain regions are in contact with the source and drain electrodes 36a and 36b. The active layer 32 is formed of a semiconductor such as polysilicon or a compound semiconductor containing oxygen, and the gate electrode 34 is formed of an aluminum (Al) alloy including nickel (Ni) and lanthanum (La).

In addition, taking the structure of FIG. 2B as an example, at least one of the lower and upper surfaces of the gate electrode 34 as shown in FIG. 2C for stable interface contact with the gate insulating layer 33 and the insulating layer 35. Barrier layers 37a and 37b may be formed. The barrier layers 37a and 37b are formed of a metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW).

In the thin film transistor of the present invention configured as described above, the gate electrodes 12, 26, and 34 are formed of an aluminum (Al) alloy including nickel (Ni) and lanthanum (La). Aluminum (Al) alloys containing nickel (Ni) and lanthanum (La) have excellent thermal properties due to their high thermal and chemical stability, good surface morphology, ease of manufacture, and low resistivity of less than 4.5μΩ㎝. Do.

3A is a surface photograph of an aluminum (Al) thin film heat-treated at a temperature of 350 ° C., since aluminum (Al) expands and contracts at a high temperature, a hillock (part A) is generated due to thermal stress. The surface shape is bad. On the other hand, Figure 3b is a surface photograph of a thin film formed of an aluminum (Al) alloy according to the present invention, the surface shape is good even after heat treatment. Such surface morphology is believed to be due to the thermal stress of aluminum (Al) is reduced by the reaction with nickel (Ni).

In addition, the aluminum (Al) alloy thin film containing only nickel (Ni) exhibits an etch rate of about 120 nm / min with respect to the etchant (TMAH 2.38%), while nickel (Ni) and lanthanum (La) Since the aluminum (Al) alloy thin film having an etching ratio of about 50nm / min, the patterning process is easy due to the reduction of the etching rate of 50% or more, and the damage of the thin film by the etchant may be prevented.

The thin film transistor of the present invention configured as described above may be applied to a flat panel display. Even in a large size flat panel display device, the resistivity of the gate electrode and the wiring is kept low, thereby having excellent electrical characteristics.

FIG. 4 is a perspective view illustrating an exemplary embodiment of a flat panel display including a thin film transistor according to an exemplary embodiment of the present invention, and will be schematically described with reference to the display panel 100 displaying an image.

The display panel 100 includes two substrates 110 and 120 disposed to face each other, and a liquid crystal layer 130 injected into a sealed space between the two substrates 110 and 120.

In the substrate 110, the plurality of gate lines 111 and the data lines 112 intersect each other, and the plurality of pixel regions 113 are defined by the plurality of gate lines 111 and the data lines 112. . In the substrate 110 where the gate line 111 and the data line 112 cross each other, a thin film transistor 114 for controlling a signal supplied to each pixel and a pixel electrode 115 connected to the thin film transistor 114 are provided. Is formed. The thin film transistor 114 may be formed in the structure described with reference to FIGS. 1A to 1C and FIGS. 2A to 2C.

In addition, the color filter 121 and the common electrode 122 are formed on the substrate 120 to face the pixel electrode 115. Polarizers 116 and 123 are formed on the rear surfaces of the substrates 110 and 120, respectively, and a backlight (not shown) is disposed below the polarizer 116 as a light source.

Meanwhile, a driving unit (not shown) for driving the display panel 100 is mounted around the pixel region 113 of the display panel 100. The driver converts an electrical signal provided from the outside into a scan signal and a data signal and supplies the converted electrical signal to the gate line 111 and the data line 112.

In the flat panel display of the above embodiment, the gate line 111 and / or the data line 112 and the pad (not shown) may be formed of nickel (Ni) and lanthanum (La) in the process of forming the gate electrode of the thin film transistor. Since it can be formed of an aluminum (Al) alloy containing a) can be improved electrical properties by the low specific resistance of the wiring.

5A and 5B are a plan view and a cross-sectional view for describing another exemplary embodiment of a flat panel display including a thin film transistor according to the present invention, and will be schematically described with reference to the display panel 200 displaying an image.

Referring to FIG. 5A, the substrate 210 is defined as a pixel region 220 and a non-pixel region 230 around the pixel region 220. In the substrate 210 of the pixel region 220, a plurality of organic light emitting diodes 300 connected in a matrix manner are formed between the scan line 224 and the data line 226, and the substrate of the non-pixel region 230 is formed. In operation 210, a power supply line for operation of the scan line 224 and the data line 226 and the organic light emitting device 300 extending from the scan line 224 and the data line 226 of the pixel region 220 may be formed. Not shown) and a scan driver 234 and a data driver 236 for processing signals supplied from the outside through the pad 228 and supplying them to the scan line 224 and the data line 226 are formed.

Referring to FIG. 6, the organic light emitting display device 300 includes an anode electrode 317 and a cathode electrode 320, and an organic thin film layer 319 formed between the anode electrode 317 and the cathode electrode 320. The organic thin film layer 319 may have a structure in which a hole transport layer, an organic light emitting layer, and an electron transport layer are stacked, and further include a hole injection layer and an electron injection layer. In addition, a thin film transistor for controlling the operation of the organic light emitting device 300 and a capacitor for holding a signal may be further included. The thin film transistor 114 may be formed in the structure described with reference to FIGS. 1A to 1C and FIGS. 2A to 2C.

The organic electroluminescent device 300 including the thin film transistor configured as described above will be described in more detail with reference to FIGS. 5A and 6 as follows. For convenience of explanation, the thin film transistor having the structure shown in FIG. 1B will be described as an example.

The buffer layer 11 is formed on the substrate 210, and the gate electrode 12 is formed on the buffer layer 11 of the pixel region 220. In this case, a scan line 224 connected to the gate electrode 12 is formed in the pixel region 220, and a scan line 224 extending from the scan line 224 of the pixel region 220 in the non-pixel region 230. And a pad 228 for receiving a signal from the outside may be formed.

An active layer 14 which is electrically insulated from the gate electrode 12 by the gate insulating layer 13 and provides a channel region, a source region, and a drain region is formed on the top including the gate electrode 12.

An insulating layer 15 is formed on the active layer 14, and contact holes are formed in the insulating layer 15 to expose source and drain regions of the active layer 14. The source and drain electrodes 16a and 16b are formed on the insulating layer 15 to be in contact with the source and drain regions through contact holes. In this case, data lines 226 connected to the source and drain electrodes 16a and 16b are formed in the pixel region 220, and non-pixel regions 230 extend from the data lines 226 of the pixel region 220. The data line 226 and a pad 228 for receiving a signal from the outside may be formed.

The planarization layer 18 is formed on the top including the source and drain electrodes 16a and 16b, and the via hole is formed on the planarization layer 18 so that the source or drain electrodes 16a or 16b are exposed. An anode electrode 317 connected to the source or drain electrode 16a or 16b is formed through the via hole.

The pixel defining layer 318 is formed on the planarization layer 18 so that a portion of the anode electrode 317 is exposed, the organic thin film layer 319 is formed on the exposed anode electrode 317. The cathode electrode 320 is formed on the pixel defining layer 318 including the organic thin film layer 319.

Referring to FIG. 5B, an encapsulation substrate 400 for encapsulating the pixel region 220 is disposed on the substrate 210 on which the organic light emitting diode 300 is formed as described above, and the encapsulation substrate is formed by the encapsulant 410. 400 is bonded to the substrate 210 to complete the display panel 200.

In the flat panel display of the above embodiment, the scan line 224 and / or data line 226 and the pad 228 are formed of nickel (Ni) and lanthanum (La) in the process of forming the gate electrode of the thin film transistor according to the present invention. Since it can be formed of an aluminum (Al) alloy including a can be improved electrical properties by the low specific resistance of the wiring.

As described above, the preferred embodiment of the present invention has been disclosed through the detailed description and the drawings. The terms are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1A to 1C are cross-sectional views illustrating a thin film transistor according to an exemplary embodiment of the present invention.

2A to 2C are cross-sectional views illustrating a thin film transistor according to another exemplary embodiment of the present invention.

3A and 3B are surface photographs of an aluminum thin film and an aluminum alloy thin film subjected to heat treatment.

4 is a plan view illustrating an exemplary embodiment of a flat panel display including a thin film transistor according to the present invention.

5A and 5B are a plan view and a sectional view for explaining another embodiment of a flat panel display device having a thin film transistor according to the present invention.

FIG. 6 is a cross-sectional view for describing the organic light emitting display device of FIG. 5A. FIG.

<Explanation of symbols for the main parts of the drawings>

10, 20, 30, 110, 120, 210: substrate 11, 21, 31: buffer layer

12, 26, 34: gate electrode 13, 25, 33: gate insulating layer

14, 23, 32: semiconductor layer 15, 35: insulating layer

16a, 22a, 36a: source electrode 16b, 22b, 36b: drain electrode

17a, 17b, 37a, 37b: barrier layer 18: planarization layer

100, 200: display panel 111: gate line

112: data line 113: pixel area

114: thin film transistor 115: pixel electrode

116, 123: polarizer 121: color filter

122: common electrode 130: liquid crystal layer

220: pixel region 224: scan line

226: data line 228: pad

230: non-pixel region 234: scan driver

236: data driver 300: organic light emitting device

317: anode electrode 318: pixel defining film

319: organic thin film layer 320: cathode electrode

400: sealing substrate 410: sealing material

Claims (24)

Board; A gate electrode formed of an aluminum alloy including nickel and lanthanum on the substrate; An active layer insulated from the gate electrode by a gate insulating layer; And And a source electrode and a drain electrode in contact with the active layer. The thin film transistor of claim 1, further comprising an insulating layer formed between the active layer, the source electrode, and the drain electrode and having a contact hole, wherein the source electrode and the drain electrode are in contact with the active layer through the contact hole. The thin film transistor of claim 1, wherein the gate electrode is formed on the active layer. 4. The thin film transistor of claim 3, further comprising an insulating layer formed on the gate electrode and having a contact hole, wherein the source and drain electrodes are in contact with the active layer through the contact hole. The thin film transistor of claim 1, further comprising a barrier layer formed on at least one of a lower surface and an upper surface of the gate electrode. The thin film transistor of claim 5, wherein the barrier layer is formed of one metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW). A first substrate having a first conductive line and a second conductive line crossing each other, a thin film transistor connected between the first conductive line and the second conductive line, and a first electrode connected to the thin film transistor; A second substrate disposed to face the first substrate and having a second electrode formed thereon; And A liquid crystal layer injected into a space between the first substrate and the second substrate, The thin film transistor may include a gate electrode formed of an aluminum alloy including nickel and lanthanum on the first substrate; An active layer insulated from the gate electrode by a gate insulating layer; And And a source electrode and a drain electrode in contact with the active layer. 8. The flat panel display of claim 7, further comprising an insulating layer formed between the active layer, the source electrode, and the drain electrode and having contact holes formed therein, wherein the source electrode and the drain electrode are in contact with the active layer through the contact hole. Device. The flat panel display of claim 7, wherein the gate electrode is formed on the active layer. The flat panel display of claim 9, further comprising an insulating layer formed on the gate electrode and having a contact hole, wherein the source and drain electrodes are in contact with the active layer through the contact hole. The flat panel display of claim 7, further comprising a barrier layer formed on at least one of a lower surface and an upper surface of the gate electrode. The flat panel display of claim 11, wherein the barrier layer comprises one metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW). . The flat panel display of claim 7, wherein at least one of the first conductive line and the second conductive line is made of an aluminum alloy including nickel and lanthanum. The flat panel display of claim 13, further comprising a barrier layer formed on at least one of the lower and upper surfaces of the conductive line. The flat panel display of claim 14, wherein the barrier layer is formed of one metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW). . A first substrate having a first conductive line and a second conductive line crossing each other, a thin film transistor connected between the first conductive line and the second conductive line, and an organic electroluminescent element connected to the thin film transistor; And A second substrate disposed to face the first substrate, The thin film transistor may include a gate electrode formed of an aluminum alloy including nickel and lanthanum on the first substrate; An active layer insulated from the gate electrode by a gate insulating layer; And And a source electrode and a drain electrode in contact with the active layer. The flat panel display of claim 16, further comprising an insulating layer formed between the active layer, the source electrode, and the drain electrode and having a contact hole, wherein the source electrode and the drain electrode are in contact with the active layer through the contact hole. . The flat panel display of claim 16, wherein the gate electrode is formed on the active layer. 19. The flat panel display of claim 18, further comprising an insulating layer formed over the gate electrode and having a contact hole, wherein the source and drain electrodes are in contact with the active layer through the contact hole. The flat panel display of claim 16, further comprising a barrier layer formed on at least one of a lower surface and an upper surface of the gate electrode. The flat panel display of claim 20, wherein the barrier layer is formed of one metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW). . The flat panel display of claim 16, wherein at least one of the first conductive line and the second conductive line is made of an aluminum alloy including nickel and lanthanum. The flat panel display of claim 22, further comprising a barrier layer formed on at least one of the lower and upper surfaces of the conductive line. 24. The flat panel display of claim 23, wherein the barrier layer is formed of one metal selected from the group consisting of titanium (Ti), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), and molybdenum tungsten (MoW). .

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