KR20100044134A - Methods of forming integrated circuit contact pads using electroless plating of diffusion barrier layers - Google Patents

Methods of forming integrated circuit contact pads using electroless plating of diffusion barrier layers Download PDF

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Publication number
KR20100044134A
KR20100044134A KR1020090100346A KR20090100346A KR20100044134A KR 20100044134 A KR20100044134 A KR 20100044134A KR 1020090100346 A KR1020090100346 A KR 1020090100346A KR 20090100346 A KR20090100346 A KR 20090100346A KR 20100044134 A KR20100044134 A KR 20100044134A
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South Korea
Prior art keywords
layer
diffusion barrier
forming
barrier layer
lower bump
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KR1020090100346A
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Korean (ko)
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장우진
조성동
문범기
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삼성전자주식회사
인피니언 테크놀로지스 아게
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Publication of KR20100044134A publication Critical patent/KR20100044134A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming integrated circuit contact pads is provided to prevent the electro-migration from a copper layer by electroless-plating diffusion barrier layers. CONSTITUTION: Copper patterns(102a, 102b) are formed on a semiconductor substrate. A passivation layer is formed on the semiconductor substrate and has an opening which exposes at least part of the upper surface of the copper patterns. A diffusion barrier layer(110) is formed in the opening. The diffusion barrier layer is electroless-plated on the exposed part of the copper patterns. An under bump metallization layer(112a) is deposited on the sidewall of the opening in the passivation layer.

Description

확산 배리어층의 무전해 도금법을 이용한 집적 회로 콘택 패드의 형성 방법 {Methods of forming integrated circuit contact pads using electroless plating of diffusion barrier layers}Methods of forming integrated circuit contact pads using electroless plating of diffusion barrier layer {Methods of forming integrated circuit contact pads using electroless plating of diffusion barrier layers}

본 발명은 집적 회로 조사의 제조 방법에 관한 것으로, 더욱 구체적으로는 콘택 패드가 형성된 집적 회로 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing integrated circuit irradiation, and more particularly, to a method for manufacturing integrated circuit elements having contact pads formed thereon.

집적 회로 칩 상에 콘택 패드를 형성하는 종래의 방법은, 일반적으로 집적 회로 기판을 커버하는 전기적 절연 패시베이션층 상에 전기적 도전성 패드를 형성하는 것을 포함한다. 이러한 전기적 도전성 패드는 금속 배선의 최상부 레벨과 전기적으로 연결될 수 있으며, 하부 반도체 영역 (예를 들어, 반도체 기판) 내부의 전기 소자와 연결될 수 있다. 이러한 종래의 방법 중 몇몇을 도 1a 내지 도 1e에 도시하였다. 특히, 도 1a는 내부에 능동 소자가 형성된 하부 집적 회로 기판(미도시) 상의 상부 절연층으로 형성된 층간 절연층(10)을 도시한다. 일반적인 다마신 기술을 사용하여, 층간 절연층(10) 내에 상부 레벨의 배선 패턴(14) (예를 들어, 구리 패턴)을 형성할 수 있다. 확산 방지층(12) 또한, 패터닝된 리세스를 라이닝하여(line) 형성될 수 있다. 이러한 확산 방지층(12)은 금속층을 사용하여, 금속 원 자(예를 들어, Cu 원자)가 배선 패턴(14)에서 주변의 층간 절연층(10)으로 외확산(out-diffusion)되는 것을 방지할 수 있다. 전기적 절연 캡핑층(16) (예를 들어, SiCN층)은 층간 절연층(10) 상에 형성되고, 산화 패시베이션층(18)은 캡핑층(16) 상에 형성된다.Conventional methods of forming contact pads on integrated circuit chips generally include forming electrically conductive pads on an electrically insulating passivation layer covering the integrated circuit board. Such electrically conductive pads may be electrically connected to the top level of the metal wires and may be connected to electrical elements inside the lower semiconductor region (eg, the semiconductor substrate). Some of these conventional methods are shown in FIGS. 1A-1E. In particular, FIG. 1A illustrates an interlayer insulating layer 10 formed of an upper insulating layer on a lower integrated circuit board (not shown) in which an active device is formed. Using a common damascene technique, an upper level wiring pattern 14 (eg, a copper pattern) can be formed in the interlayer insulating layer 10. The diffusion barrier layer 12 may also be formed by lining the patterned recess. This diffusion barrier layer 12 uses a metal layer to prevent metal atoms (eg, Cu atoms) from out-diffusion from the wiring pattern 14 to the surrounding interlayer insulating layer 10. Can be. An electrically insulating capping layer 16 (eg, SiCN layer) is formed on the interlayer insulating layer 10, and the oxide passivation layer 18 is formed on the capping layer 16.

도 1b를 참조하면, 포토레지스트층(20)은 패시베이션층(18) 상에 증착되고, 이 후, 패터닝하여 내부에 오프닝을 정의한다. 패터닝된 포토레지스트층(20)은, 패시베이션층 및 캡핑층(16)을 관통하여 선택적으로 식각하고, 도 1c에 도시된 바와 같이 배선 패턴(14)의 상부 표면을 노출시키는 콘택홀을 정의하는 공정 동안, 식각 마스크로 사용된다. 이후에, 도 1d 및 도 1e에 도시된 바와 같이, 알루미늄층(22)을 패시베이션층(18) 상에 컨포멀하게 증착하고, 이 후 패터닝된 포토레지스트층(24)을 식각 마스크로, 선택적 식각하여, 알루미늄 패드(22)를 정의한다. 이어서, 알루미늄 패드(22) 상에 전기적 절연 패시베이션층(26)을 형성한다. 상기 패시베이션층(26) 내에 오프닝을 형성하여, 알루미늄 패드(22)의 상부 표면의 일부를 노출시킨다. 이어서, 일반적인 기법을 사용하여 오프닝 내에 솔더 범프(solder bump)를 정의하며, 이는 플립-칩(flip-chip) 패키징에 사용될 수 있다. 또는 상기 오프닝은 알루미늄 패드(22)에 직접 와이어 본딩할 수 있도록 사용될 수도 있다.Referring to FIG. 1B, a photoresist layer 20 is deposited on passivation layer 18 and then patterned to define an opening therein. The patterned photoresist layer 20 is selectively etched through the passivation layer and the capping layer 16 and defines a contact hole exposing the top surface of the wiring pattern 14 as shown in FIG. 1C. Is used as an etch mask. Thereafter, as shown in FIGS. 1D and 1E, the aluminum layer 22 is conformally deposited on the passivation layer 18, and then the patterned photoresist layer 24 is etched with an etching mask. The aluminum pad 22 is defined. Subsequently, an electrically insulating passivation layer 26 is formed on the aluminum pad 22. An opening is formed in the passivation layer 26 to expose a portion of the upper surface of the aluminum pad 22. The general technique is then used to define solder bumps within the opening, which can be used for flip-chip packaging. Alternatively, the opening may be used to directly wire bond to the aluminum pad 22.

플립-팁 본딩에 적합한 콘택 패드를 형성하는 일반적인 방법은 도 2a 내지 2g에 도시하였다. 구체적으로, 도 2a는 복수의 패터닝된 구리층(42a, 42b)을 도시하며, 이들은 일반적인 다마신 공정 기법을 이용하여 층간 절연층(40) 내에 형성될 수 있다. 전기적 절연층의 스택(stack)은, 캡핑층(44), 실리콘 산화막(silicon dioxide layer; 46) 및 실리콘 질화막(silicon nitride layer; 48)을 포함하고, 층간 절연층(40) 상에 형성된다. 도 2b 내지 도 2d를 참고하여, 이어서, 이러한 전기적 절연층의 스택을 사진 식각 공정으로 패터닝하여, 내부에 패터닝된 구리층(42a)의 상부 표면을 노출시키는 콘택 오프닝(49)를 정의한다. 전기적 도전층(50) (예를 들어, TiN 금속층)을 콘택 오프닝(49) 내에 컨포멀하게 증착한다. 화학적 기계적 연마(Chemical Mechanical Polishing; CMP) 단계를 수행하여, 전기적 도전층(50)을 평탄화하고, 이로서 콘택 라이너(50a)를 정의한다.A general method of forming a contact pad suitable for flip-tip bonding is shown in FIGS. 2A-2G. Specifically, FIG. 2A shows a plurality of patterned copper layers 42a and 42b, which can be formed in the interlayer insulating layer 40 using conventional damascene processing techniques. The stack of electrically insulating layers includes a capping layer 44, a silicon dioxide layer 46, and a silicon nitride layer 48, and is formed on the interlayer insulating layer 40. Referring to FIGS. 2B-2D, this stack of electrically insulating layers is then patterned by a photolithography process to define a contact opening 49 exposing the top surface of the patterned copper layer 42a therein. An electrically conductive layer 50 (eg, a TiN metal layer) is conformally deposited within the contact opening 49. A chemical mechanical polishing (CMP) step is performed to planarize the electrically conductive layer 50, thereby defining the contact liner 50a.

이어서, 도 2e 및 도 2f에 도시된 바와 같이, 하부 범프 배선화(UnderBump Metallization; UBM)층(52)을 실리콘 질화막(48) 및 콘택 라이너(50a) 상에 컨포멀하게 증착한다. 도 2f에 도시된 바와 같이, 이어서, 패터닝된 포토레지스트층(54)을 UBM층(52) 상에 형성한다. 패터닝된 포토레지스트층(54)은 콘택 오프닝(49) 내로 확장된 UBM층(52)의 일부를 노출시킨다. 이러한 UBM층(52)은 솔더층(56)을 콘택 오프닝(49) 내로 전기 도금하는데 사용될 수 있다. 도 2g를 참조하여, 이어서, 포토레지스트층(54)을 제거하고, 이어서 솔더층(56)을 식각 마스크로 하여 UBM층(52)을 에치백(etching back)한다. 이어서, 솔더 리플로우 공정(solder reflow step)을 진행하여, 솔더층(56)을 솔더 범프(56a)로 전환시킨다.Subsequently, a lower bump metallization (UBM) layer 52 is conformally deposited on the silicon nitride film 48 and the contact liner 50a, as shown in FIGS. 2E and 2F. As shown in FIG. 2F, a patterned photoresist layer 54 is then formed on the UBM layer 52. Patterned photoresist layer 54 exposes a portion of UBM layer 52 that extends into contact opening 49. This UBM layer 52 can be used to electroplate the solder layer 56 into the contact opening 49. Referring to FIG. 2G, the photoresist layer 54 is subsequently removed, and the UBM layer 52 is etched back using the solder layer 56 as an etch mask. Next, a solder reflow step is performed to convert the solder layer 56 to the solder bumps 56a.

본 발명이 해결하고자 하는 과제는 확산 배리어층의 무전해 도금법을 이용하는 집적 회로 콘택 패드의 형성 방법을 제공하는 것이다.An object of the present invention is to provide a method for forming an integrated circuit contact pad using an electroless plating method of a diffusion barrier layer.

본 발명이 해결하고자 하는 과제들은 이상에서 언급한 과제들로 제한되지 않으며, 언급되지 않은 또 다른 과제들은 아래의 기재로부터 당업자에게 명확하게 이해될 수 있을 것이다.Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

본 발명의 실시예들에 따른 콘택 패드의 제조 방법은, 반도체 기판 상에 구리 패턴을 형성하고, 상기 구리 패턴 상에 패시베이션층을 형성하는 것을 포함한다. 상기 패시베이션층은 상기 구리 패턴의 상부 표면의 적어도 일부를 노출시키는 오프닝을 내부에 가지도록 정의한다. 확산 배리어층을 상기 오프닝 내에 형성하되, 상기 구리 패턴의 상기 상부 표면의 상기 노출된 부분 상에 상기 확산 배리어층을 무전해 도금하여 형성한다. 상기 확산 배리어층은 상기 구리 패턴으로부터 구리의 외확산에 대한 장벽(barrier)으로서의 역할을 한다. 이러한 방법은, 상기 확산 배리어층의 상부 표면 상에, 그리고 상기 패시베이션층 내의 상기 오프닝의 적어도 측벽 상에 하부 범프 배선화층을 컨포멀하게 증착하는 것을 더 포함한다. 이어서, 상기 확산 배리어층의 반대로 확장되는 하부 범프 배선층의 일부 상에 콘택 범프(예를 들어, 솔더 범프)를 도금하는 공정을 수행한다. 본 발명의 이러한 실시예들의 몇몇에 의하면, 콘택 범프를 도금하는 공정 전에, 상기 하부 범프 배선화층 상 에 포토레지스트층을 증착하는 것과, 상기 포토레지스트층을 패터닝하여 상기 확산 배리어층의 반대로 확장하는 하부 범프 배선화층의 일부를 노출하는 오프닝을 내부에 정의하는 것을 포함한다. 또한, 콘택 범프를 도금하는 공정을 진행한 후에, 상기 솔더 범프를 식각 마스크로하여, 상기 하부 범프 배선화층을 선택적으로 에치백하는 공정을 수행할 수 있다.A method of manufacturing a contact pad according to embodiments of the present invention includes forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. The passivation layer is defined to have an opening therein that exposes at least a portion of the upper surface of the copper pattern. A diffusion barrier layer is formed in the opening, wherein the diffusion barrier layer is formed by electroless plating on the exposed portion of the upper surface of the copper pattern. The diffusion barrier layer serves as a barrier to outdiffusion of copper from the copper pattern. The method further includes conformally depositing a lower bump interconnection layer on an upper surface of the diffusion barrier layer and on at least sidewalls of the opening in the passivation layer. Subsequently, a process of plating contact bumps (eg, solder bumps) on a portion of the lower bump wiring layer that extends opposite to the diffusion barrier layer is performed. According to some of these embodiments of the present invention, a process of depositing a photoresist layer on the lower bump interconnection layer prior to the process of plating the contact bumps, and a lower portion of the photoresist layer patterned to extend opposite to the diffusion barrier layer And defining an opening that exposes a portion of the bump wiring layer. In addition, after the process of plating the contact bumps, the process of selectively etching back the lower bump wiring layer using the solder bump as an etching mask may be performed.

본 발명의 다른 실시예들은, 반도체 기판 상에 구리 패턴을 형성하고, 이어서, 내부에 오프닝을 가지는 패시베이션층을 형성하여, 상기 구리 패턴의 상부 표면의 적어도 일부를 노출시킴으로써 콘택 패드를 형성하는 것을 포함한다. 이어서, 무전해 도금법을 수행하여, 상기 구리 패턴의 상기 상부 표면의 상기 노출된 일부의 바로 위에 코발트를 포함하는 확산 배리어층을 형성한다. 본 발명의 몇몇 실시예에 따르면, 상기 확산 배리어층은, 예를 들어 CoWP, CoWPB 또는 CoWB층일 수 있다.Other embodiments of the present invention include forming a contact pad by forming a copper pattern on a semiconductor substrate, and then forming a passivation layer having an opening therein to expose at least a portion of the upper surface of the copper pattern. do. An electroless plating method is then performed to form a diffusion barrier layer comprising cobalt directly over the exposed portion of the upper surface of the copper pattern. According to some embodiments of the present invention, the diffusion barrier layer may be, for example, a CoWP, CoWPB or CoWB layer.

또한, 이러한 방법은, 상기 패시베이션층 상과, 상기 확산 배리어층의 상부 표면 상에 하부 범프 배선화층을 증착하고, 이어서, 상기 확산 배리어층의 반대로 확장되는 상기 하부 범프 배선화층의 일부 상에 솔더 범프를 도금하는 공정을 포함할 수 있다. 이어서, 상기 하부 범프 배선화층을 선택적으로 에치백하여 상기 패시베이션층을 노출시킨다. 이러한 식각 공정 동안, 상기 솔더 범프는 식각 마스크로 사용한다. 상기 하부 범프 배선화층은 티타늄-베이스 확산 배리어층과, 상기 티타늄-베이스 확산 배리어층 상의 금 및/또는 플래티늄 금속층의 조합을 포함할 수 있다. 또한, 상기 패시베이션층은 SiCN 캡핑층, 상기 SiCN 캡핑층 상의 실리콘 산화 절연층, 및 상기 실리콘 산화 절연층 상의 실리콘 질화 절연층의 조합으로 형성될 수 있다.This method also deposits a lower bump interconnection layer on the passivation layer and on an upper surface of the diffusion barrier layer, and then solder bumps on a portion of the lower bump interconnection layer that extends opposite to the diffusion barrier layer. It may include the step of plating. Subsequently, the lower bump interconnection layer is selectively etched back to expose the passivation layer. During this etching process, the solder bumps are used as an etching mask. The lower bump interconnection layer may include a combination of a titanium-based diffusion barrier layer and a gold and / or platinum metal layer on the titanium-based diffusion barrier layer. In addition, the passivation layer may be formed of a combination of a SiCN capping layer, a silicon oxide insulating layer on the SiCN capping layer, and a silicon nitride insulating layer on the silicon oxide insulating layer.

본 발명의 다른 실시예는, 층간 절연층 내에 구리 패턴의 2차원 어레이를 형성하고, 이어서, 상기 구리 패턴의 2차원 어레이를 노출시키는 오프닝을 내부에 가지는 복수 층의 패시베이션층을 형성하여, 콘택 패드를 형성하는 것을 포함한다. 이어서, 무전해 도금 공정을 수행하여, 상기 구리 패턴의 2차원 어레이 상에, 코발트를 포함하는 공간-분리 확산 배리어층의 어레이를 정의한다. 이어서, 상기 구리 패턴의 2차원 어레이 사이에 확장된 층간 절연층의 일부와, 상기 공간-분리 확산 배리어층의 어레이 바로 위에 하부 범프 배선화층을 증착한다. 이어서, 솔더 범프를 상기 하부 범프 배선화층 상에 도금한다.Another embodiment of the present invention provides a contact pad by forming a two-dimensional array of copper patterns in an interlayer insulating layer, and then forming a plurality of passivation layers having an opening therein that exposes the two-dimensional array of copper patterns. It includes forming a. An electroless plating process is then performed to define an array of space-separation diffusion barrier layers comprising cobalt on the two-dimensional array of copper patterns. A lower bump interconnection layer is then deposited over a portion of the interlayer dielectric layer extending between the two-dimensional array of copper patterns and directly over the array of space-separation diffusion barrier layers. Subsequently, a solder bump is plated on the lower bump wiring layer.

본 발명의 기타 구체적인 사항들은 상세한 설명 및 도면들에 포함되어 있다.Other specific details of the invention are included in the detailed description and drawings.

본 발명의 이점 및 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 도면에서 층 및 영역들의 크기 및 상대적인 크기는 설명의 명료성을 위해 과장된 것일 수 있다.Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

소자(elements) 또는 층이 다른 소자 또는 층의 "위(on)" 또는 "상(on)"으로 지칭되는 것은 다른 소자 또는 층의 바로 위뿐만 아니라 중간에 다른 층 또는 다른 소자를 개재한 경우를 모두 포함한다. 반면, 소자가 "직접 위(directly on)" 또는 "바로 위"로 지칭되는 것은 중간에 다른 소자 또는 층을 개재하지 않은 것을 나타낸다. "및/또는"은 언급된 아이템들의 각각 및 하나 이상의 모든 조합을 포함한다.When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle. “And / or” includes each and all combinations of one or more of the items mentioned.

공간적으로 상대적인 용어인 "아래(below)", "아래(beneath)", "하부(lower)", "위(above)", "상부(upper)" 등은 도면에 도시되어 있는 바와 같이 하나의 소자 또는 구성 요소들과 다른 소자 또는 구성 요소들과의 상관관계를 용이하게 기술하기 위해 사용될 수 있다. 공간적으로 상대적인 용어는 도면에 도시되어 있는 방향에 더하여 사용시 또는 동작 시 소자의 서로 다른 방향을 포함하는 용어로 이해되어야 한다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성 요소를 지칭한다.The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. Like reference numerals refer to like elements throughout.

본 명세서에서 기술하는 실시예들은 본 발명의 이상적인 개략도인 평면도 및 단면도를 참고하여 설명될 것이다. 따라서, 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 따라서, 본 발명의 실시예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. 따라서, 도면에서 예시된 영역들은 개략적인 속성을 가지며, 도면에서 예시된 영역들의 모양은 소자의 영역의 특정 형태를 예시하기 위한 것이고, 발명의 범주를 제한하기 위한 것은 아니다.Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device, and is not intended to limit the scope of the invention.

본 명세서에서 기술하는 실시예들은 본 발명의 이상적인 개략도인 평면도 및 단면도를 참고하여 설명될 것이다. 따라서, 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 따라서, 본 발명의 실시예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. 따라서, 도면에서 예시된 영역들은 개략적인 속성을 가지며, 도면에서 예시된 영역들의 모양은 소자의 영역의 특정 형태를 예시하기 위한 것이고, 발명의 범주를 제한하기 위한 것은 아니다.Embodiments described herein will be described with reference to plan and cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. Thus, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device, and is not intended to limit the scope of the invention.

이하, 도 3a 내지 도 3f을 참조하면, 본 발명의 몇몇 실시예들에 따른 콘택 패드의 형성 방법은, 반도체 기판 상에 구리 패턴을 형성하고, 구리 패턴 상에 패시베이션층을 형성하는 것을 포함한다. 도 3a에 도시된 바와 같이, 복수의 패터닝된 구리층(102a, 102b)을, 예를 들어 다마신 패터닝 기술을 이용하여, 층간 절연층(100) 내에 형성할 수 있다. 층간 절연층(100)을 기판(예를 들어, 반도체 기판) 상에 상부 전기적 절연층으로 형성할 수 있다. 이어서, 패시베이션층을 층간 절연층(100) 상에 형성한다. 패시베이션층은, 약 5,000 Å 내지 약 20,000 Å의 범위의 두께를 가질 수 있으며, 복수의 서로 다른 전기적 절연 물질의 혼합으로 형성할 수 있다. 특히, 이러한 패시베이션층은, 층간 절연층(100)의 바로 위(directly on)에 형성된 전기적 절연 캡핑층(104)을 포함할 수 있다. 캡핑층(104)은 약 500 Å 내지 약 5,000 Å 범위의 두께를 가지는 SiCN층으로 형성할 수 있다. 또한, 패시베이션층은 캡핑층(104) 상에 형성된 실리콘 산화 절연층(silicon dioxide insulating layer; 106)과, 실리콘 산화 절연층(106) 상에 형성된 실리콘 질화 절연층(silicon nitride insulating layer; 108)을 포함할 수 있다.3A to 3F, a method of forming a contact pad according to some embodiments of the present disclosure includes forming a copper pattern on a semiconductor substrate and forming a passivation layer on the copper pattern. As shown in FIG. 3A, a plurality of patterned copper layers 102a, 102b may be formed in the interlayer insulating layer 100 using, for example, damascene patterning techniques. The interlayer insulating layer 100 may be formed as an upper electrical insulating layer on a substrate (eg, a semiconductor substrate). Next, a passivation layer is formed on the interlayer insulating layer 100. The passivation layer may have a thickness in the range of about 5,000 kPa to about 20,000 kPa, and may be formed by mixing a plurality of different electrically insulating materials. In particular, this passivation layer may include an electrically insulating capping layer 104 formed directly on the interlayer insulating layer 100. The capping layer 104 may be formed of a SiCN layer having a thickness in the range of about 500 kPa to about 5,000 kPa. In addition, the passivation layer may include a silicon dioxide insulating layer 106 formed on the capping layer 104 and a silicon nitride insulating layer 108 formed on the silicon oxide insulating layer 106. It may include.

도 3b 및 도 3c를 참조하여, 이어서, 사진 식각 공정을 수행하여, 패시베이션층을 관통하여 연장되고 패터닝된 구리층(102a)의 상부 표면을 노출시키는 콘택 오프닝(109)를 정의한다. 이어서, 무전해 도금 공정을 수행하여, 콘택 오프닝(109)에 자기 정렬된(self-aligned) 확산 배리어층(110)을 정의한다. 확산 배리어층(110)은, 패터닝된 구리 층(102a)로부터 구리가 외확산되는 것을 방지할 수 있고, 예를 들어, CoWP, CoWPB 또는 CoWB층일 수 있으며, 약 10 Å 내지 약 5,000 Å 범위의 두께를 가질 수 있다. 또한, 확산 배리어층(110)은 패터닝된 구리층(102a)으로부터 전기 이동(electromigration)을 방지함으로써 상대적 고전류 밀도를 지탱할 수 있다.Referring to FIGS. 3B and 3C, a photolithography process is then performed to define a contact opening 109 extending through the passivation layer and exposing the top surface of the patterned copper layer 102a. An electroless plating process is then performed to define a diffusion barrier layer 110 that is self-aligned to the contact opening 109. The diffusion barrier layer 110 may prevent the copper from diffusing out of the patterned copper layer 102a and may be, for example, a CoWP, CoWPB or CoWB layer, with a thickness in the range of about 10 kPa to about 5,000 kPa. It can have In addition, the diffusion barrier layer 110 can sustain a relatively high current density by preventing electromigration from the patterned copper layer 102a.

그 이후에, 도 3d에 도시된 바와 같이, 하부 범프 배선화층(underbump metallization layer; 112)을 콘택 오프닝(109) 내부와, 확산 배리어층(110) 상에 컨포멀하게 증착한다. 이러한 하부 범프 배선화층(112)은 약 500 Å 내지 2,000 Å 범위의 두께를 가지는 금막(Au layer)으로 형성할 수 있다. 선택적으로, 하부 범프 배선화층(112)은 티타늄-베이스 확산 배리어층 상의 금 및/또는 플라티늄(platinium) 금속층 및 니켈-베이스 확산 배리어층의 조합을 포함할 수 있다. 이어서, 포토레지스트층을 하부 범프 배선화층(112) 상에 형성하고, 패터닝하여, 도 3e에 도시된 바와 같이 오프닝(109)를 노출시키는 패터닝된 포토레지스트층(114)을 정의한다. 이어서, 솔더 범프층(116)을 오프닝(109) 내에 도금한다. 이어서, 패터닝된 포토레지스트층(114)을 제거하고, 리플로우 공정을 진행하여, 도 3f에 도시된 바와 같이 하부 범프 배선화층(112a) 상에 최종 솔더 범프(116a)를 정의한다. 이어 서, 솔더 범프(116a)를 식각 마스크로하여, 노출된 하부 범프 배선화층(112)을 선택적으로 에치백한다. 본 발명의 몇몇 다른 실시예에 따르면, 도 3a 내지 도 3f에 도시된 방법 실시예들을 이용하여 도 4의 솔더 범프(116a)를 정의할 수 있으며, 이들은 무전해 도금으로 형성된 복수의 확산 배리어층(110)에 대응하여, 복수의 (예를 들어, 2 차원 어레이) 패터닝된 구리층(102a)과 전기적으로 연결된다.Thereafter, as shown in FIG. 3D, an underbump metallization layer 112 is conformally deposited inside the contact opening 109 and on the diffusion barrier layer 110. The lower bump interconnection layer 112 may be formed of an Au layer having a thickness in a range of about 500 kV to 2,000 kV. Optionally, lower bump interconnect layer 112 may comprise a combination of a gold and / or platinum metal layer and a nickel-based diffusion barrier layer on the titanium-based diffusion barrier layer. A photoresist layer is then formed on the lower bump interconnection layer 112 and patterned to define a patterned photoresist layer 114 that exposes the opening 109 as shown in FIG. 3E. Subsequently, the solder bump layer 116 is plated into the opening 109. Subsequently, the patterned photoresist layer 114 is removed and a reflow process is performed to define the final solder bumps 116a on the lower bump wiring layer 112a as shown in FIG. 3F. Subsequently, the exposed lower bump wiring layer 112 is selectively etched back using the solder bumps 116a as an etching mask. According to some other embodiments of the present invention, the solder bumps 116a of FIG. 4 may be defined using the method embodiments shown in FIGS. 3A-3F, which are a plurality of diffusion barrier layers formed of electroless plating ( Corresponding to 110, it is electrically connected with a plurality of (eg, two-dimensional array) patterned copper layers 102a.

이상 첨부된 도면을 참조하여 본 발명의 실시예들을 설명하였지만, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자는 본 발명이 그 기술적 사상이나 필수적인 특징을 변경하지 않고서 다른 구체적인 형태로 실시될 수 있다는 것을 이해할 수 있을 것이다. 그러므로 이상에서 기술한 실시예들은 모든 면에서 예시적인 것이며 한정적이 아닌 것으로 이해해야만 한다.Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

도 1a 내지 도 1e는 종래 기술에 따른 콘택 패드 형성 방법을 설명하기 위한 중간 구조물의 단면도들이다.1A to 1E are cross-sectional views of an intermediate structure for explaining a method of forming a contact pad according to the prior art.

도 2a 내지 도 2g는 종래 기술에 따른 콘택 패드 형성 방법을 설명하기 위한 중간 구조물의 단면도들이다.2A to 2G are cross-sectional views of an intermediate structure for explaining a method of forming a contact pad according to the prior art.

도 3a 내지 도 3f는 본 발명의 실시예들에 따른 콘택 패드의 형성 방법을 설명하기 위한 중간 구조물의 단면도들이다.3A to 3F are cross-sectional views of intermediate structures for describing a method of forming a contact pad according to embodiments of the present invention.

도 4는 본 발명의 다른 실시예들에 따른 콘택 패드의 형성 방법을 설명하기 위한 중간 구조물의 단면도들이다.4 is a cross-sectional view of an intermediate structure for explaining a method of forming a contact pad according to other embodiments of the present invention.

(도면의 주요부분에 대한 부호의 설명)  (Explanation of symbols for the main parts of the drawing)

10, 40, 100: 층간 절연층 12: 확산 방지층10, 40, 100: interlayer insulation layer 12: diffusion barrier layer

14: 배선 패턴 16, 104: 전기적 절연 캡핑층14: wiring pattern 16, 104: electrically insulating capping layer

18: 산화 패시베이션층 20: 포토레지스트층18: oxide passivation layer 20: photoresist layer

22: 알루미늄층 24, 54, 114: 패터닝된 포토레지스트층22: aluminum layer 24, 54, 114: patterned photoresist layer

26: 패시베이션층 42a, 42b, 102a, 102b: 패터닝된 구리층26: passivation layer 42a, 42b, 102a, 102b: patterned copper layer

44: 캡핑층 46: 실리콘 산화막44: capping layer 46: silicon oxide film

48: 실리콘 질화막 49, 109: 콘택 오프닝48: silicon nitride film 49, 109: contact opening

50: 전기적 도전층 50a: 콘택 라이너50: electrically conductive layer 50a: contact liner

52: UBM층 56, 116: 솔더층52: UBM layer 56, 116: solder layer

56a, 116a: 솔더 범프 106: 실리콘 산화 절연층56a, 116a: solder bump 106: silicon oxide insulating layer

108: 실리콘 질화 절연층 110: 확산 베리어층108: silicon nitride insulating layer 110: diffusion barrier layer

112, 112a: 하부 범프 배선화층112, 112a: lower bump wiring layer

Claims (17)

반도체 기판 상에 구리 패턴을 형성하고,Forming a copper pattern on the semiconductor substrate, 상기 구리 패턴의 상부 표면의 적어도 일부를 노출시키는 오프닝을 내부에 가지는 패시베이션층을 형성하고,Forming a passivation layer having an opening therein that exposes at least a portion of an upper surface of the copper pattern, 상기 오프닝 내에 확산 배리어층을 형성하되, 상기 구리 패턴의 상부 표면의 상기 노출된 부분 상에 상기 확산 배리어층을 무전해 도금하는 것을 포함하는 콘택 패드의 형성 방법.Forming a diffusion barrier layer in said opening, said method comprising electroless plating said diffusion barrier layer on said exposed portion of an upper surface of said copper pattern. 제1 항에 있어서,According to claim 1, 상기 패시베이션층 상 및 상기 확산 배리어층의 상부 표면 상에 하부 범프 배선화층을 컨포멀하게 증착하는 것을 더 포함하는 콘택 패드의 형성 방법.And conformally depositing a lower bump interconnect layer on the passivation layer and on an upper surface of the diffusion barrier layer. 제2 항에 있어서, 상기 컨포멀하게 증착하는 것은,The method of claim 2, wherein conformally depositing, 상기 하부 범프 배선화층을 상기 패시베이션층 내의 상기 오프닝의 측벽 바로 위에 (directly onto) 증착하는 것을 포함하는 콘택 패드의 형성 방법.Depositing the lower bump interconnection layer directly onto the sidewalls of the opening in the passivation layer. 제3 항에 있어서,The method of claim 3, 상기 확산 배리어층의 반대로 확장되는 하부 범프 배선화층의 일부 상에 콘택 범프를 도금하는 것을 더 포함하는 콘택 패드의 형성 방법.Plating the contact bumps on a portion of the lower bump interconnection layer that extends opposite the diffusion barrier layer. 제4 항에 있어서, 상기 콘택 범프를 도금하기 전에,The method of claim 4, before plating the contact bumps, 상기 하부 범프 배선화층 상에 포토레지스트층을 증착하고,Depositing a photoresist layer on the lower bump interconnection layer, 상기 포토레지스트층을 패터닝하여 내부에 상기 확산 배리어층의 반대로 확장되는 상기 하부 범프 배선화층의 일부를 노출시키는 오프닝을 정의하는 것을 포함하는 콘택 패드의 형성 방법.Patterning the photoresist layer to define an opening therein that exposes a portion of the lower bump interconnection layer that extends opposite the diffusion barrier layer. 제5 항에 있어서, 상기 콘택 범프를 도금하는 것은,The method of claim 5, wherein plating the contact bumps, 상기 하부 범프 배선화층 상에 전기적 도전성의 솔더 범프를 도금하는 것을 포함하는 콘택 패드의 형성 방법.And plating an electrically conductive solder bump on the lower bump interconnection layer. 제6 항에 있어서, 상기 콘택 범프를 도금한 후에,The method of claim 6, after plating the contact bumps, 상기 솔더 범프를 식각 마스크로 하여, 상기 하부 범프 배선화층을 선택적으로 에치백(etching back)하는 공정을 진행하는 것을 포함하는 콘택 패드의 형성 방법.And performing a process of selectively etching back the lower bump interconnection layer using the solder bump as an etch mask. 반도체 기판 상에 구리 패턴을 형성하고,Forming a copper pattern on the semiconductor substrate, 내부에 상기 구리 패턴의 상부 표면의 적어도 일부를 노출시키는 오프닝을 가지는 패시베이션층을 형성하고,Forming a passivation layer having an opening therein exposing at least a portion of the upper surface of the copper pattern, 상기 구리 패턴의 상기 상부 표면의 상기 노출된 부분 바로 위(directly on) 코발트를 포함하는 확산 배리어층을 무전해 도금(eletroless plating)하는 것을 포함하는 콘택 패드의 형성 방법.And electroless plating a diffusion barrier layer comprising cobalt directly on said exposed portion of said top surface of said copper pattern. 제8 항에 있어서, The method of claim 8, 상기 확산 배리어층은 텅스텐을 더 포함하는 콘택 패드의 형성 방법.And the diffusion barrier layer further comprises tungsten. 제9 항에 있어서, 상기 확산 배리어층은 CoWP, CoWPB 및 CoWB으로 이루어진 그룹으로부터 선택된 물질을 포함하는 콘택 패드의 형성 방법.The method of claim 9, wherein the diffusion barrier layer comprises a material selected from the group consisting of CoWP, CoWPB, and CoWB. 제8 항에 있어서,The method of claim 8, 상기 패시베이션층 및 상기 확산 배리어층의 상부 표면 상에 하부 범프 배선화층을 증착하고,Depositing a lower bump interconnection layer on an upper surface of the passivation layer and the diffusion barrier layer, 상기 확산 배리어층의 반대로 확장된 상기 하부 범프 배선화층의 일부 상에 솔더 범프를 도금하는 것을 더 포함하는 콘택 패드의 형성 방법.Plating a solder bump on a portion of the lower bump interconnection layer extending opposite to the diffusion barrier layer. 제11 항에 있어서, The method of claim 11, wherein 상기 솔더 범프를 식각 마스크로 하여, 상기 하부 범프 배선화층을 선택적으로 에치백하여, 상기 패시베이션층을 노출시키는 것을 더 포함하는 콘택 패드의 형성 방법.And etching the lower bump interconnection layer selectively using the solder bump as an etch mask to expose the passivation layer. 제11 항에 있어서,The method of claim 11, wherein 상기 하부 범프 배선화층은 티타늄-베이스 확산 배리어층과, 상기 티타늄-베이스 확산 배리어층 상의 금 및/또는 플래티늄 금속층의 조합을 포함하는 콘택 패드의 형성 방법.And the lower bump interconnection layer comprises a combination of a titanium-based diffusion barrier layer and a gold and / or platinum metal layer on the titanium-based diffusion barrier layer. 제8 항에 있어서, 상기 패시베이션층은,The method of claim 8, wherein the passivation layer, SiCN 캡핑층;SiCN capping layer; 상기 SiCN 캡핑층 상의 실리콘 산화 절연층(silicon dioxide insulating layer); 및A silicon dioxide insulating layer on the SiCN capping layer; And 상기 실리콘 산화 절연층 상의 실리콘 질화 절연층(silicon nitride insulating layer)을 포함하는 콘택 패드의 형성 방법.And forming a silicon nitride insulating layer on the silicon oxide insulating layer. 층간 절연층 내에 구리 패턴의 2차원 어레이를 형성하고,Forming a two-dimensional array of copper patterns in the interlayer insulating layer, 내부에 상기 구리 패턴의 2차원 어레이를 노출하는 오프닝을 포함하는 복수 층의 패시베이션층을 형성하고,Forming a plurality of passivation layers including an opening exposing a two-dimensional array of copper patterns therein, 상기 구리 패턴의 2차원 어레이 상에, 코발트를 포함하는 공간-분리(spaced-apart) 확산 배리어층의 어레이를 무전해 도금하고,Electroless plating an array of spaced-apart diffusion barrier layers comprising cobalt on a two-dimensional array of copper patterns, 하부 범프 배선화층을 상기 공간-분리 확산 배리어층의 어레이와, 상기 구리 패턴의 2차원 어레이 사이로 확장된 상기 층간 절연층의 일부 바로 위에(directly on) 증착하는 것을 포함하는 콘택 패드의 형성 방법.Depositing a lower bump interconnection layer directly on a portion of the interlayer dielectric layer extending between the array of space-separation diffusion barrier layers and the two-dimensional array of copper patterns. 제15 항에 있어서, 상기 공간-분리 확산 배리어층은,The method of claim 15, wherein the space-separation diffusion barrier layer, CoWP, CoWPB 및 CoWB으로 이루어진 그룹으로부터 선택된 물질을 포함하는 콘택 패드의 형성 방법.A method of forming a contact pad comprising a material selected from the group consisting of CoWP, CoWPB and CoWB. 제16 항에 있어서,The method of claim 16, 상기 하부 범프 배선화층 상에 솔더 범프를 도금하는 것을 더 포함하는 콘택 패드의 형성 방법.And forming a solder bump on the lower bump interconnection layer.
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