KR20100041405A - Image sensor and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to improve the electrical connection performance between a wiring and a photodiode by forming a plug which passes through the photodiode to be connected with the wiring. CONSTITUTION: A readout circuit(120) is formed on a substrate(100). A wiring(150) is electrically connected with the readout circuit. An image sensor(210) includes a first conductive layer(214) and a second conductive layer(216). The image sensor is electrically connected with the wiring. A plug(220) is formed in the image sensor and connects the first conductive layer and the wiring. A barrier layer electrically insulates the second conductive layer and the plug.

Description

Image sensor and method for manufacturing

Embodiments relate to an image sensor and a manufacturing method thereof.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) and a CMOS image sensor (CIS).

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

On the other hand, according to the prior art there is a difficulty in the electrical connection between the lead-out circuit and the photodiode properly. For example, according to the related art, a wiring is formed on a lead-out circuit and wafer-to-wafer bonding is performed so that the wiring and the photodiode contact each other. Ohmic contact of photodiodes is difficult. In addition, according to the related art, there is a problem in that short circuit occurs for wiring to be electrically connected to the photodiode.

In addition, according to the related art, since both the source and the drain of the both ends of the transfer transistor are doped with a high concentration of N-type, charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur. In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

The embodiment is to provide an image sensor and a method of manufacturing the same, while shortening does not occur while increasing the electrical connection between the photodiode and the wiring while increasing the fill factor (fill factor).

In addition, the embodiment is to provide an image sensor and a method of manufacturing the same that can increase the charge factor (Charge Sharing) does not occur. In addition, the embodiment of the present invention provides an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by creating a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a manufacturing method.

An image sensor according to an embodiment includes a first substrate on which a readout circuitry is formed; Wiring electrically connected to the lead-out circuit; An image sensing unit including a first conductive type conductive layer and a second conductive type conductive layer and electrically connected to the wiring; And a plug formed in the image sensing unit to electrically connect the first conductivity type conductive layer and the wiring.

In addition, the manufacturing method of the image sensor according to the embodiment comprises the steps of forming a wiring and a lead out circuit on the first substrate; Forming an image sensing unit including a first conductivity type conductive layer and a second conductivity type conductive layer on the wiring; And forming a plug in the image sensing unit to electrically connect the first conductivity type conductive layer and the wiring.

According to the image sensor and the manufacturing method according to the embodiment, the plug is formed through the photodiode and electrically connected to the wiring to improve the electrical connection performance of the wiring and the photodiode, and further formed an insulating layer on the photodiode By doing so, short can be prevented.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source / drain across the transistor Tx, thereby enabling full dumping of the photo charge. In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Hereinafter, an image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and can be applied to all image sensors requiring a photodiode.

(First embodiment)

1 is a cross-sectional view of an image sensor according to a first embodiment.

The image sensor according to the first embodiment includes a first substrate 100 on which a readout circuitry 120 is formed; A wire 150 electrically connected to the readout circuit 120; An image sensing device 210 including a first conductive conductive layer 214 and a second conductive conductive layer 216 and electrically connected to the wiring 150; And a plug 220 formed in the image sensing unit 210 to electrically connect the first conductivity type conductive layer 214 and the wiring 150. The image sensing unit 210 may be a photodiode 210, but is not limited thereto and may be a photogate, a combination of a photodiode and a photogate, and the like.

On the other hand, the embodiment is an example in which the photodiode 210 is formed in the crystalline semiconductor layer, but is not limited to this includes that formed in the amorphous semiconductor layer.

The lead-out circuit 120 of the first substrate 100 may include an electrical junction region 140 formed on the first substrate 100; And a first conductivity type connection region 147 formed on the electrical junction region to be connected to the wiring 150.

Unexplained reference numerals among the reference numerals of FIG. 1 will be described in the following manufacturing method.

Hereinafter, a method of manufacturing the image sensor according to the first embodiment will be described with reference to FIGS. 2 to 8.

First, as shown in FIG. 2, the first substrate 100 having the wiring 150 and the readout circuit 120 is prepared. For example, the isolation layer 110 is formed on the second conductive first substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed.

The forming of the lead-out circuit 120 on the first substrate 100 may include forming an electrical junction region 140 on the first substrate 100 and forming an interconnection on the electrical junction region 140. And forming a first conductivity type connection region 147 connected to 150.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The first substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed so that there is a voltage difference between the source / drain across the transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, in the embodiment, as shown in FIG. 2, the voltage difference between the source / drain across the transistor Tx 121 is formed by forming the electrical junction region 140 on the first substrate 100 on which the readout circuit 120 is formed. This allows full dumping of the photocharge.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the first substrate 100, is P0 / N− / in the 4-Tr APS Reset operation. In Pwell Junction, + voltage is applied to N- (143) and Ground voltage is applied to P0 (145) and Pwell 141. Therefore, P0 / N- / Pwell Double Junction is Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, thereby preventing the charge sharing phenomenon during the Tx On / Off operation.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation ( Saturation) can be prevented and degradation of sensitivity.

To this end, the first embodiment may form a first conductivity type connection region 147 for ohmic contact on the surface of the P0 / N- / P- cushion 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, the width of the first conductive connection region 147 may be minimized in order to minimize the first conductive connection region 147 from becoming a leakage source. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the first substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

Next, as shown in FIG. 3, a crystalline semiconductor layer 210a is formed on the second substrate 200. In the first embodiment, the photodiode 210 is formed on a crystalline semiconductor layer. Thus, according to the first embodiment, the image sensing unit adopts a three-dimensional image sensor positioned above the readout circuit to increase the fill factor while forming the image sensing unit in the crystalline semiconductor layer to prevent defects in the image sensing unit. Can be.

For example, the crystalline semiconductor layer 210a is formed on the second substrate 200 by epitaxial. Thereafter, hydrogen ions are implanted at the boundary between the second substrate 200 and the crystalline semiconductor layer 210a to form the hydrogen ion implanted layer 207a. The implantation of the hydrogen ions may be performed after ion implantation for forming the photodiode 210.

Next, as shown in FIG. 4, the photodiode 210 is formed by ion implantation into the crystalline semiconductor layer 210a. For example, a second conductivity type conductive layer 216 is formed under the crystalline semiconductor layer 210a. For example, a high concentration P-type conductive layer 216 may be formed by implanting ions into the entire surface of the second substrate 200 with a blanket under the crystalline semiconductor layer 210a without a mask.

Thereafter, a first conductivity type conductive layer 214 is formed on the second conductivity type conductive layer 216. For example, a low concentration N-type conductive layer 214 may be formed by implanting ions onto the entire surface of the second substrate 200 without a mask on the second conductive conductive layer 216.

Thereafter, the first embodiment may further include forming a high concentration of the first conductivity type conductive layer 212 on the first conductivity type conductive layer 214. For example, an ion implantation may be performed on the entire surface of the second substrate 200 without a mask on the first conductive type conductive layer 214 to form a high concentration N + type conductive layer 212, thereby contributing to ohmic contact.

Next, as shown in FIG. 5, the first substrate 100 and the second substrate 200 are bonded to each other so that the photodiode 210 and the wiring 150 correspond to each other. In this case, the bonding may be performed by increasing the surface energy of the surface bonded by activation by plasma before bonding the first substrate 100 and the second substrate 200. Meanwhile, in order to improve the bonding force, bonding may be performed through an insulating layer, a metal layer, or the like on the bonding interface.

Thereafter, the hydrogen ion implantation layer 207a may be changed into a hydrogen gas layer (not shown) through heat treatment on the second substrate 200.

Next, as shown in FIG. 6, the photodiode 210 may be exposed by leaving a photodiode 210 based on the hydrogen gas layer and removing a portion of the second substrate 200 using a blade or the like.

Thereafter, the photodiode 210 is partially etched to form a hole h exposing the wiring 150. For example, the photodiode may be partially etched using the first photoresist pattern 310 as an etch mask to expose the wiring 150.

Next, as shown in FIG. 7, a metal filling the hole h may be formed. When filling the hole h, the first photoresist layer pattern 310 may or may not be removed. When the first photoresist layer pattern 310 is not removed, metal is not formed on the non-etched photodiode 210.

Subsequently, a part of the metal filled in the hole h may be etched to form a plug 220 connected to the first conductivity type conductive layer 214. For example, the plug 220 may be formed by performing an etch-out process using the first photoresist pattern 310 as an etch mask.

According to the embodiment, a plug electrically connected to the wiring through the photodiode may be formed to improve electrical connection performance of the wiring and the photodiode.

Next, as shown in FIG. 8, the blocking layer 230 is formed on the plug 220 in the photodiode 210 such that the second conductive conductive layer 216 and the plug 220 do not electrically contact each other. do. For example, the blocking layer 230 may be formed of an insulating film such as an oxide film or a nitride film on the plug 220 of the hole h.

The embodiment can prevent the short by forming a blocking layer of the plug detailed insulating layer on the photodiode.

Subsequently, the photodiode 210 may be etched by pixel, and the etched portion may be filled with an inter-cell insulation layer (not shown). Alternatively, a P-type ion implantation layer may be formed for pixel separation.

Thereafter, a process such as the upper electrode 240 and a color filter (not shown) may be performed.

(2nd Example)

9 is a sectional view of an image sensor according to a second embodiment.

The image sensor according to the second embodiment includes a first substrate 100 on which a readout circuitry 120 is formed; A wire 150 electrically connected to the readout circuit 120; An image sensing device 210 including a first conductive conductive layer 214 and a second conductive conductive layer 216 and electrically connected to the wiring 150; And a plug 220 formed in the image sensing unit 210 to electrically connect the first conductivity type conductive layer 214 and the wiring 150. The image sensing unit 210 may be a photodiode 210, but is not limited thereto and may be a photogate, a combination of a photodiode and a photogate, and the like.

The second embodiment may include an electrical junction region 140 formed on the first substrate 100.

The second embodiment can employ the technical features of the first embodiment.

For example, the second embodiment forms a plug that is electrically connected to the wiring through the photodiode to improve the electrical connection performance of the wiring and the photodiode, and further, to prevent the short by forming an insulating layer on the photodiode. can do.

In addition, according to the second embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transistor Tx, thereby enabling full dumping of the photo charge. In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. You can prevent it.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contacts may be formed in the P0 / N− / P− junction 140, in which the process of forming the N + connection region 148 and the M1C contact 151a may be performed. It can be a Leakage Source. This is because an electric field EF may be generated on the surface of the substrate Si because the reverse bias is applied to the P0 / N- / P-junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and is connected to the N-junction 143. To present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a sectional view of an image sensor according to a first embodiment;

2 to 8 are process cross-sectional views of a method of manufacturing the image sensor according to the first embodiment.

9 is a sectional view of an image sensor according to a second embodiment;

Claims (17)

A first substrate on which a readout circuitry is formed; Wiring electrically connected to the lead-out circuit; An image sensing unit including a first conductive type conductive layer and a second conductive type conductive layer and electrically connected to the wiring; And And a plug formed in the image sensing unit to electrically connect the first conductivity type conductive layer and the wiring. According to claim 1, And a blocking layer formed in the image sensing unit so that the second conductive conductive layer and the plug do not electrically contact each other. According to claim 1, The lead out circuit is An electrical junction region formed in the first substrate, The electrical junction region is A first conductivity type ion implantation region formed on the first substrate; And And a second conductivity type ion implantation region formed on the first conductivity type ion implantation region. The method of claim 3, And a first conductivity type connection region formed on the electrical junction region and electrically connected to the wiring. The method of claim 3, The electrical junction region is Image sensor characterized in that the PNP junction (junction). According to claim 1, The lead out circuit is An image sensor comprising a potential difference between a source and a drain of two sides of a transistor. According to claim 1, The transistor is a transfer transistor, And an ion implantation concentration of the transistor source is lower than an ion implantation concentration of the floating diffusion region. The method of claim 3, And a first conductivity type connection region formed on one side of the electrical junction region to be electrically connected to the wiring. The method of claim 8, The first conductivity type connection region And an electrical junction region in contact with the device isolation region. Forming a wiring and a lead-out circuit on the first substrate; Forming an image sensing unit including a first conductivity type conductive layer and a second conductivity type conductive layer on the wiring; And And forming a plug in the image sensing unit to electrically connect the first conductivity type conductive layer and the wiring. The method of claim 10, And forming a blocking layer on the plug in the image sensing unit such that the second conductive conductive layer and the plug are not in electrical contact with each other. The method of claim 10, Forming the plug, Partially etching the image sensing unit to form a hole exposing the wiring; Filling the hole with metal; And And etching the metal to form a plug that is connected to the first conductive type conductive layer. The method of claim 10, Forming a lead-out circuit on the first substrate comprises forming an electrical junction region on the first substrate, Forming an electrical junction region on the first substrate, Forming a first conductivity type ion implantation region in the first substrate; And And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. The method of claim 13, And forming a first conductive connection region connected to the wiring on the electrical junction region. The method of claim 14, Forming the first conductivity type connection region, The method of manufacturing an image sensor, characterized in that proceeds after the contact etched on the wiring. The method of claim 13, And forming a first conductive connection region connected to the wiring on one side of the electrical junction region. The method of claim 16, The first conductivity type connection region The method of manufacturing an image sensor, characterized in that formed in contact with the device isolation region and the electrical junction region.

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