KR20100041310A - Semiconductor memory device having pad structure for capacitance enlargement - Google Patents

Abstract

PURPOSE: A semiconductor memory device with a pad structure is provided to increase the internal capacitance of pins or pads by grounding a part of a poly silicon layer which configures the pads. CONSTITUTION: A first silicon layer and a second silicon layer and a metal layer(L30) are successively stacked in order to form a pad structure. A ground connection unit parallelly connects capacitances between a second silicon layer and a metal layer. The ground connection unit receives ground voltage through a metal contact(C01) which is formed between a second silicon layer and a metal layer(L31). The metal layers are formed in a same level.

Description

Semiconductor memory device having pad structure for capacitance enlargement

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a pad structure for increasing internal capacitance.

In general, semiconductor memory devices, such as dynamic random access memory, tend to be increasingly high-speed and high-density day by day according to the needs of users. Dynamic random access memory devices having one access transistor and one storage capacitor as unit memory cells are commonly employed as main memory devices of electronic systems.

Referring to FIG. 1, which illustrates a chip configuration of a dynamic random access memory device, data input / output pins 2, 4, a clock pin 10, an address pin, and various types of data may be provided outside the package 100 in which the chip 50 is packaged. Signal input and output pins are formed to connect with other external circuit devices.

In FIG. 1, for example, the data input / output pins 2 are wire bonded with a bonding pad P formed on the chip 50 with lead wires 3 before being packaged. The bonding pad P is connected to a data input / output buffer (not shown) through an electrostatic discharge protection circuit (ESD), and the data input / output buffer is connected to a sense amplifier through a data input / output line, and thus is operable with the memory cell MC. Is connected. Therefore, since the data input / output pin 2 is connected to the bonding pad P for data input / output, it must have an appropriate internal capacitance value accordingly.

After all, the internal capacitance (Cin) refers to the capacitance viewed from the pin of the semiconductor device into the package. Looking at the components of the internal capacitance in turn from the outer pin 2 to the inside, as shown in FIG. 2, the package 100, the wire bonding 4, the pad 52, the metal line 6, and the electrostatic discharge A protection circuit 54 and a circuit element component 58 are included.

In the case of most semiconductor memory devices, the specifications of the internal capacitance required for each of the DQ / DQS / DM, ADDR / CMD, and CK / CKB pins (specifications, also referred to as "specs") are different. The circuit operation including read and write operations is not impeded to be satisfied.

The adjustment of the internal capacitance for each pin is largely determined by the parasitic capacitances created by the pad structure. For example, a first capacitance formed by an interlayer insulating layer existing between a metal layer forming a word line or a bit line of a semiconductor memory device in a pad structure and a plate polysilicon layer of a storage capacitor, and the plate polysilicon layer and a memory cell transistor. Internal capacitance is formed by the connection of the second capacitance formed by the interlayer insulating film existing between the gate polysilicon layers forming the gate, and the third capacitance formed by the gate oxide layer existing between the gate polysilicon layer and the substrate. Decisions are made in large part, and the fine adjustment is determined by the number of fingers of the electrostatic discharge transistor connected to the rear end of the pad (the active region of the transistor in the form of a finger).

However, if the target capacitance value does not reach the minimum specification of the internal capacitance when the number of fingers of the transistor is not sufficiently secured, the internal capacitance of the corresponding pin does not meet the specified specification. .

Accordingly, an object of the present invention is to provide a semiconductor memory device having an increased internal capacitance of a pin or pad.

Another object of the present invention is to provide a semiconductor memory device capable of adjusting internal capacitance even with a minimum number of fingers of a control transistor.

It is still another object of the present invention to provide a method that can solve the lack of internal capacitance of a semiconductor memory device.

Still another object of the present invention is to provide a semiconductor memory device that can easily adjust the internal capacitance even if the option clamp transistor is reduced or the parasitic capacitance is small per finger.

It is a further object of the present invention to provide an improved pad structure which can increase the internal capacitance relatively simply without complicating the manufacturing process.

A semiconductor memory device according to an aspect of the present invention,

A pad structure in which first and second silicon layers and metal layers are sequentially stacked through an interlayer insulating film;

And a ground connection to ground the second silicon layer to selectively form a parallel connection with the capacitance formed between the second silicon layer and the metal layer.

In an embodiment of the present invention, the ground connection part receives a ground voltage through a metal contact formed between the second silicon layer and a metal layer formed at the same level as the metal layer.

Further, the second silicon layer may be formed at the time of manufacture of the plate polysilicon layer of the semiconductor memory cell, and the first silicon layer may be formed at the time of manufacture of the gate polysilicon layer of the semiconductor memory cell.

Preferably, a second metal layer may be further formed on the metal layer via a via layer, and an electrostatic discharge protection circuit may be connected to a rear end of the pad structure.

According to another aspect of an exemplary embodiment of the present invention,

A pad structure in which a gate polysilicon layer, a plate polysilicon layer, and a metal layer are sequentially stacked via an interlayer insulating film;

In order to increase the internal capacitance capacity, the first capacitance existing between the plate polysilicon layer and the metal layer and the second capacitance existing between the plate polysilicon layer and the gate polysilicon layer selectively form a parallel connection structure with each other. And a ground connection for grounding the plate polysilicon layer.

Preferably, the ground connection unit receives a ground voltage through a metal contact formed between the plate polysilicon layer and a metal layer formed at the same level as the metal layer, and the second capacitance is the gate polysilicon layer and the gate polysilicon. The third capacitance existing between the lower layers of the layer may form a series connection structure with each other.

In an exemplary embodiment of the present invention, electrostatic discharge protection transistors are connected to a rear end of the pad structure, and detailed control of internal capacitance may be implemented by adding or subtracting the number of fingers of the electrostatic discharge protection transistors.

According to the exemplary configuration of the present invention as described above, by grounding a part of the polysilicon layer constituting the pad, the internal capacitance of the pin or pad is increased. Therefore, it is possible to adjust the internal capacitance even with the minimum number of fingers of the control transistor, and there is an advantage that the adjustment of the internal capacitance can be easily performed even if the option clamp transistor for adjustment is reduced or the parasitic capacitance per finger is small. .

Hereinafter, an embodiment of a semiconductor memory device having a pad structure for increasing internal capacitance according to an embodiment of the present invention will be described with reference to the accompanying drawings.

Although many specific details are set forth in the following examples by way of example and in the accompanying drawings, it is noted that this has been described without the intent to assist those of ordinary skill in the art to provide a more thorough understanding of the present invention. shall. However, it will be understood by those skilled in the art that the present invention may be practiced without these specific details. Known manufacturing processes and interlayer structures and the formation of parasitic capacitors, the operation of dynamic random access memory, and the functional circuits associated therewith have not been described in detail in order not to obscure the present invention.

Conventional techniques will be briefly described with reference to FIG. 3 only as an intention for a more thorough distinction from the embodiments of the invention described below.

Referring to FIG. 3, which shows a pad structure of a chip according to convention technology in a conventional DRAM, in the layer structure constituting the pad structure of FIG. The three capacitors C1, C2 and C3 are connected in series with each other in circuit. Therefore, the internal capacitance Cin, which becomes the total capacitance, is smaller than the respective capacitances of the 1,2,3 capacitors C1, C2, C3. That is, 1 / Cin = 1 / C1 + 1 / C2 + 1 / C3 when the capacitors are connected in series. In the case of FIG. 3, the first capacitor C1 is formed by an interlayer insulating film existing between the metal layers L30 and MET1 forming the word line or the bit line and the plate polysilicon layers L20 and PP of the storage capacitor. Become,

The second capacitance C2 is formed by the interlayer insulating layer between the plate polysilicon layer L20 and the gate polysilicon layers L10 and GP forming the gate of the memory cell transistor.

In addition, a third capacitance C3 is formed by the gate oxide layer between the gate polysilicon layer L10 and a substrate not shown. Since the first, second, and third capacitances C1, C2, and C3 have a structure connected in series with each other, the total capacitance value becomes smaller than the value of each capacitance.

In general, the specification condition of the internal capacitance is satisfied by the number of fingers of the transistors constituting the electrostatic discharge circuit at the rear end of the pad, which is a problem when the minimum value of the internal capacitance is not satisfied even though all the ESD transistors are used.

Therefore, in the embodiment of the present invention, the plate polysilicon layer L20 is grounded through the metal contact L31 to increase the internal capacitance. Details of this will be described with reference to FIGS. 4 and 5.

4 is a diagram illustrating a pad structure of a chip according to an exemplary embodiment of the present invention. 4, a pad structure in which a gate polysilicon layer L10, a plate polysilicon layer L20, and a metal layer L30 are sequentially stacked through an interlayer insulating film;

In order to increase the internal capacitance capacity, the first capacitance C1 existing between the plate polysilicon layer L20 and the metal layer L30 and the plate polysilicon layer L20 and the gate polysilicon layer L10 are present. It is shown that the ground connection parts CO1 and L31 are provided to ground the plate polysilicon layer L20 in order to allow the existing second capacitance C2 to form a parallel connection structure with each other.

The metal contact CO1 constituting the ground connection part is a metal contact formed between the second silicon layer L20 and the metal layer L31 formed at the same level as the metal layer MET1, and preferably, the metal layer L31. It is grounded through to receive the ground voltage.

Here, the second silicon layer L20 is a conductive layer which may be formed together when the plate polysilicon layer of the semiconductor memory cell is manufactured, and the first silicon layer L10 is formed of the gate polysilicon layer of the semiconductor memory cell. Can be formed together at the time of manufacture.

In FIG. 4, a second metal layer L50 is further formed on the metal layer L30 via the via layer L40, and an electrostatic discharge protection circuit ESD as shown in FIG. 5 at the rear of the pad structure. ) May be connected.

FIG. 5 shows an equivalent circuit for a circuit component including a clamp transistor used to fine tune internal capacitance in the pad structure of FIG. 4. In FIG. 5, reference numeral 2 is a pin, reference letter C_PKG denotes a parasitic capacitance of the package, R_PKG denotes a parasitic resistance of the package, and L_PKG denotes a parasitic reactance of the package, and a transistor type diode connected between the node ND1 and the power voltage ( D1) functions as a power clamp, and the transistor type diode D2 connected between the node ND1 and the ground voltage serves as a ground clamp. The unexplained reference character C_COMP indicates the capacitance exhibited by the circuit component.

4 again, as shown in the pad structure of FIG. 4, when grounding the plate polysilicon (PP) layer, the internal capacitance Cin is greatly increased. That is, in such a structure, since the first and second capacitors C1 and C2 form a parallel connection with each other, Cin = C1 + C2 // C3. Therefore, in the case of FIG. 4, the internal capacitance Cin, which is the total capacitance, is greatly increased compared to the series structure of FIG. 3.

In the case of adjusting the internal capacitance (Cin) to the number of fingers of the ESD transistor, if the Cin is insufficient, a larger number of fingers are required. When applying the embodiment of the present invention to ground the polysilicon layer, the lack of internal capacitance is required. Can be solved. Thus, it is possible to reduce the option clamp transistor and to adjust the internal capacitance even if the parasitic capacitance per finger is small. In this manner, by grounding the plate polysilicon layer, the insufficient internal capacitance can be increased to maintain the desired internal capacitance.

Although the plate polysilicon layer PP has been described with respect to increasing internal capacitance, it is also possible to plate the gate polysilicon layer GP instead of the plate polysilicon layer or to ground both silicon layers together. to be.

In the above description, the embodiments of the present invention have been described with reference to the drawings. will be. For example, if the matter is different, the layer structure of the pad and the parallel connection configuration of the capacitor may be different without departing from the technical spirit of the present invention.

In addition, although the case of DRAM is exemplified, the technical idea of the present invention may be widely applied to other volatile memories such as SRAM and the like or nonvolatile memories such as NVM.

1 is a chip configuration diagram of a conventional semiconductor memory device

FIG. 2 illustrates internal capacitance components of the chip of FIG. 1. FIG.

3 illustrates a pad structure of a chip according to convention technology.

4 is a pad structure diagram of a chip according to an embodiment of the present invention;

FIG. 5 is an equivalent circuit diagram of a circuit component including a clamp transistor used for fine adjustment of internal capacitance in the pad structure of FIG. 4. FIG.

Claims (10)

A pad structure in which first and second silicon layers and metal layers are sequentially stacked through an interlayer insulating film; And a ground connection connected to the ground of the second silicon layer to selectively form a capacitance and a parallel connection between the second silicon layer and the metal layer. The semiconductor memory device of claim 1, wherein the ground connection unit receives a ground voltage through a metal contact formed between the second silicon layer and a metal layer formed at the same level as the metal layer. 2. The semiconductor memory device according to claim 1, wherein said second silicon layer is formed during fabrication of a plate polysilicon layer of a semiconductor memory cell. 4. The semiconductor memory device according to claim 3, wherein the first silicon layer is formed during fabrication of the gate polysilicon layer of the semiconductor memory cell. The semiconductor memory device of claim 4, wherein a second metal layer is further formed on the metal layer via a via layer. The semiconductor memory device of claim 1, wherein an electrostatic discharge protection circuit is connected to a rear end of the pad structure. A pad structure in which a gate polysilicon layer, a plate polysilicon layer, and a metal layer are sequentially stacked via an interlayer insulating film; In order to increase the internal capacitance capacity, the first capacitance existing between the plate polysilicon layer and the metal layer and the second capacitance existing between the plate polysilicon layer and the gate polysilicon layer selectively form a parallel connection structure with each other. And a ground connection for grounding the plate polysilicon layer. The semiconductor memory device of claim 7, wherein the ground connection unit receives a ground voltage through a metal contact formed between the plate polysilicon layer and a metal layer formed at the same level as the metal layer. 10. The semiconductor memory device of claim 8, wherein the second capacitance forms a series connection structure with a third capacitance existing between the gate polysilicon layer and a lower layer of the gate polysilicon layer. The semiconductor memory device of claim 9, wherein electrostatic discharge protection transistors are connected to a rear end of the pad structure, and detailed control of internal capacitance is implemented by adding or subtracting the number of fingers of the electrostatic discharge protection transistors.

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