KR20100040551A - Semiconductor device and method for forming the same - Google Patents

Abstract

PURPOSE: A semiconductor and a method for forming the same are provided to prevent the bridge between storage electrodes by directly contacting a storage electrode and the contact of the storage electrode. CONSTITUTION: One word line(15) is overlapped with the center of an active region(13). A bit line(23) is connected to the one side of the active region. A storage electrode is connected to the other side of the active region. The bit line connects the one sides of a plurality of active regions. The storage electrode with a longitudinal axis toward the bit line direction is formed with a rectangular plane shape.

Description

Semiconductor device and its formation method {SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a structure for forming one gate and one capacitor on one active region.

As the demand for memory devices of semiconductor devices increases rapidly, various techniques have been proposed to obtain high capacity capacitors.

The capacitor has a structure in which a dielectric film is interposed between the storage electrode as the lower electrode and the plate electrode as the upper electrode.

The capacitance of the capacitor is proportional to the electrode surface area and the dielectric constant of the dielectric film, and inversely proportional to the spacing between the electrodes, that is, the thickness of the dielectric film. Therefore, a method of using a dielectric film having a high dielectric constant, a method of reducing the thickness of the dielectric film, a method of increasing the surface area of the lower electrode, or a method of reducing the distance between the electrodes has been developed to manufacture a capacitor having high capacitance.

However, due to the increase in the degree of integration of semiconductor devices, it is increasingly difficult to manufacture capacitors capable of securing sufficient capacitance due to the size of devices being gradually reduced.

Accordingly, researches to improve the structure of the lower electrode have been steadily made. As a solution, a concave type or a cylinder type capacitor having a three-dimensional structure has been developed.

Recently, a new type of cylindrical capacitor that uses an internal area as well as an external area as an electrode area is more preferred than a concave capacitor using only an internal area as an electrode area.

In addition, in order to solve the degree of integration due to high integration, the capacitors were laid out in a zigzag planar structure to form capacitors.

However, since two capacitors share one active region, a neighbor gate effect is induced, an Ioff fail is generated.

In addition, the storage electrodes of the capacitor are misaligned, causing a bridge between the storage electrodes.

An object of the present invention is to provide a semiconductor device in which one transistor and one capacitor are formed in one active region, and a method of forming the same.

The semiconductor device according to the present invention,

Unit active area,

One word line overlapping the unit active area;

A bit line connected to one side of the unit active area;

A storage electrode connected to the other side of the unit active region;

The word line overlapped with a central portion of a unit active area;

The bit line has a planar structure connecting one side of the unit active region,

The major axis directions of the bit line and the word line are formed in a planar structure with an angle of β, provided that 0 <β <90 °

The storage electrode is formed in the shape of a square or a rectangle having the same direction as the long axis and short axis direction of the unit active region,

Forming the storage electrode in a square overlapping with the bit line;

The storage electrode is not overlapped with the bit line and is formed in the shape of a rectangle formed in the long axis direction of the bit line.

In addition, the method of forming a semiconductor device according to the present invention,

Forming an isolation layer defining an active region on the semiconductor substrate;

Forming a word line overlapping the active region;

Forming a bit line by connecting one side of the active region;

Forming a storage electrode connected to the other side of the active region;

The storage electrode may be formed in a planar structure having a rectangular shape having a long axis in the bit line direction.

A semiconductor device and a method of forming the same according to the present invention,

The present invention provides a structure for forming one gate and one capacitor on one active region to improve operating characteristics of a semiconductor device, simplify a process, and prevent bridges between storage electrodes.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

The principle of the present invention is to provide a structure in which the size of the active region is reduced and arranged in a zigzag form to form one gate and a capacitor on one active region.

This makes it possible to directly connect the storage electrode and the storage electrode contact without misalignment, thereby solving a problem such as a bridge between the storage electrodes in the prior art. In addition, since only one storage electrode contact is used in a structure in which two storage electrode contacts are used, the process can be simplified, and since the layout is such that only one transistor exists in the center of one active region, the prior art shared two transistors. It is possible to solve problems such as deterioration of electrical characteristics due to neighboring gate effects. In addition, the bit line may be at an acute angle with respect to the word line to increase the contact area between the storage electrode contact and the landing plug contact, thereby lowering the contact resistance, thereby improving characteristics of the cell transistor.

Here, the layout of the semiconductor device according to the present invention is as follows.

1. The active region is laid out so that a long axis is formed in the cell array in a direction perpendicular to the word line direction, and one word line is laid out on one active region.

2. The landing plug contact (LPC) is laid out on the active area of the bit line contact and the storage electrode contact, and the bit line contact is laid out on the LPC.

3. Lay out the bit line contact so that the bit line is acute with the word line, but increase the spacing between adjacent bit lines to increase the size of the storage electrode contact formed in the subsequent process. It is possible to reduce the contact resistance between the contact and the storage resistance at the upper end.

4. Layout the storage electrode contacts on the LPC and layout the storage electrodes on the storage electrode contacts.

Hereinafter, a semiconductor device and a method of forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

1 to 7 are plan views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the present invention.

Referring to FIG. 1, an isolation layer 11 defining an active region 13 is formed in a cell array. The device isolation film 11 is formed by forming a pad insulating film on a semiconductor substrate and forming a trench by etching the pad insulating film and the semiconductor substrate by a photolithography process using a device isolation mask, and then filling the trench and removing the pad insulating film. It is.

In this case, the active region 13 is formed such that the long axis direction is perpendicular to the word line, and a word line is formed at the center of the active region to form the active region 13 in a zigzag form based on the word lines of the same width.

Here, the long axis of the active region 13 is formed in a size of 60 to 300 nm, the short axis of the active region 13 in the word line direction is formed to a size of 20 to 100 nm.

In addition, the spacing between the short axis directions of the active regions 13 is preferably equal to about 20 to 100 nm, which is the short axis size of the active region 13.

In addition, the interval between the major axis directions of the active region 13 is preferably 20 to 100 nm in size to equalize the interval between the active regions 13 in the word line direction.

Referring to FIG. 2, the word line 15 is formed in a direction perpendicular to the long axis direction of the active region 13. The word line 15 is formed by forming a stacked structure of a gate oxide film, a word line conductive layer, and a hard mask layer on a semiconductor substrate, and patterning the same by a photolithography process using a word line mask. In a subsequent process, an insulating layer may be deposited on the sidewall of the word line 15 and anisotropically etched to form a spacer.

At this time, the word line 15 is formed in the center of the active region 13, the line width of the word line 15 is formed in the size of 20 ~ 100 nm, the spacing between the word line 15 is also formed in the size of 20 ~ 100 nm. Therefore, it is preferable to equalize the word line line width and the spacing between word lines.

Referring to FIG. 3, a landing plug contact (hereinafter referred to as LPC) formed on the active region 13 is formed. The LPC forms an interlayer insulating film on the entire surface after the process of FIG. 2 and forms a landing plug contact hole exposing the active area by a self-aligned contact process using an active area mask. Next, a conductive layer filling the same is formed on the entire surface and formed by flattening etching. In this case, the planarization etching process is performed to expose the hard mask layer of the word line 15 so as to be separated into the bit line LPC 17 and the storage electrode LPC 19.

At this time, the LPC is formed of a bit line LPC 17 and a storage electrode LPC 19, and they are preferably formed in a size of 20 to 100 nm.

Although not shown here, it is also preferable to increase the margin for subsequent bit line contacts by forming the horizontal and vertical sizes of the bitline LPC 17 in different sizes, that is, in the form of a rectangle.

Of course, it is also possible to form the LPC 19 for the storage electrode in the form of a rectangle.

For reference, the spacing between the LPCs 17 and 19 is preferably formed in a size of 20 to 100 nm.

Referring to FIG. 4, a bit line contact 21 is formed on the bit line LPC 17. More specifically, after forming the interlayer insulating film on the entire surface after the process of Figure 3 by etching the interlayer insulating film by a photolithography process using a bit line contact mask to expose the bit line LPC (17) After forming, the bit line contact material filling the bit line contact material is formed on the entire surface, and the bit line contact 21 is formed by flattening etching or etching back to expose the interlayer insulating layer.

In this case, the bit line contacts 21 may be formed to have a width and length of about 20 to 100 nm, respectively, and the width and length may have the same or different shapes.

Here, since the bit line contacts 21 are formed in the LPC region for the storage electrode every other cell and in each cell, the bit line contacts 21 are arranged diagonally.

Referring to FIG. 5, a bit line 23 connected to the bit line contact 21 is formed. In more detail, the bit line material connected to the bit line contact 21 is formed on the entire surface and patterned by a photolithography process using a bit line mask to form the bit line 23.

In this case, the bit line 23 may be formed to form a predetermined angle β with respect to the word line 15 so as not to pass over the storage electrode LPC 19.

In addition, the bit line 23 may be formed to have an acute angle with respect to the word line 15, and the bit line 23 may have a line width having a size of 20 to 100 nm, and the interval between the bit lines 23 may be 20. It is preferable to form in a size of ˜150 nm.

Here, in order to increase the contact area between the storage electrode contact formed in the subsequent process and the storage electrode LPC 19, the width of the bit line 23 may be reduced, and the gap between the bit lines 23 may be formed larger. Do.

Referring to FIG. 6, the storage electrode contact 25 is formed on the storage electrode LPC 19. In more detail, an interlayer insulating film is formed on the entire surface including the bit line 23 and a storage electrode contact hole for exposing the storage electrode LPC 19 is formed by a photolithography process using a storage electrode contact mask. Next, the storage electrode contact material filling the same is formed on the entire surface, and the storage electrode contact 25 is formed by flattening etching or etching back.

At this time, the storage electrode contacts 25 are formed in a horizontal and vertical size of about 20 to 100 nm.

In addition, since the bit line 23 forms an acute angle with the word line 15, the distance between the bit lines 23 increases, so that the size of the storage electrode contact 25 can be increased, so that the bit line 23 can be largely aligned with the storage electrode LPC 19. By reducing the contact resistance, it is possible to improve the characteristics of the cell transistor.

Referring to FIG. 7, the storage electrode 27 is formed on the storage electrode contact 25. In more detail, the storage electrode 27 is formed in a structure that can increase the surface area, such as a stack, a cylinder, a concave, or a fin connected to the storage electrode contact 25. An example of a cylinder is as follows. First, a stacked structure of an etch barrier layer, a sacrificial insulating film for a storage electrode, and a hard mask layer is formed on a structure on which a storage electrode contact 25 is formed, and the stacked structure is etched by a photolithography process using a storage electrode mask. A storage electrode region exposing the storage electrode 25, and then a conductive layer for the storage electrode to be connected to the storage electrode contact 25 is formed on the entire surface, and a planarized insulating film filling the storage electrode region, for example, an oxide film or a photoresist film. Is formed over the entire surface and planarized to expose the sacrificial insulating film for the storage electrode. Then, the insulating film buried in the storage electrode region is removed to form a concave type storage electrode, and the storage electrode is subjected to a dip out process. The sacrificial insulating film is removed to form a cylindrical storage electrode.

At this time, the storage electrode 27 is preferably formed in a planar structure in the horizontal or vertical direction of 50 to 200 nm size or 50 to 150 nm size, respectively.

In addition, the spacing between the storage electrodes 27 is preferably about 10 ~ 150 nm.

In addition, the storage electrode 27 is formed in a square or rectangular shape, and is formed in an on-axis shape on a storage electrode contact at a lower end thereof, thereby forming a bridge between the storage electrode contacts in the prior art. It provides the effect of reducing the problem.

Therefore, one unit cell may form one transistor and one capacitor in one active region to increase process margin and may be used in a highly integrated DRAM technology of 80 nm or less.

8 is a plan view illustrating a method of forming a semiconductor device in accordance with a second embodiment of the present invention.

After the process of FIG. 6, the storage electrode 28 connected to the storage electrode contact 25 is formed. The storage electrode 28 may be formed in the same manner as the storage electrode 27 of FIG. 7.

In this case, the storage electrode 28 may be formed in a square or rectangular shape parallel to the bit line 23, thereby increasing the area of the storage electrode 28 by the distance between the bit lines 23. .

Here, the storage electrode 28 has a size of about 20 to 150 nm in the direction of the bit line 23, the spacing between the storage electrodes 28 adjacent in the direction of the bit line 23 is about 20 to 100 nm, and the bit line ( The spacing between the storage electrodes 28 adjacent to each other in the direction perpendicular to 23 is preferably formed in a size of 20 to 100 nm.

1 to 7 are plan views illustrating a method of forming a semiconductor device in accordance with a first embodiment of the present invention.

8 is a plan view showing a method of forming a semiconductor device according to the second embodiment of the present invention.

Claims (9)

Unit active area, One word line overlapping the unit active area; A bit line connected to one side of the unit active area; And a storage electrode connected to the other side of the unit active region. The method according to claim 1, And the word line overlaps a central portion of a unit active region. The method according to claim 1, And the bit line has a planar structure connecting one side of the unit active region. The method according to claim 1, The long axis direction of the bit line and the word line is a semiconductor device, characterized in that formed in a planar structure of β angle. (Where 0 <β <90 °) The method according to claim 1, The storage electrode is a semiconductor device, characterized in that formed in the shape of a square (square) or rectangle (rectangle) in the same direction of the long axis and short axis direction of the unit active region. The method according to claim 1, The storage electrode is a semiconductor device, characterized in that formed in the square (square) not overlapping with the bit line. The method according to claim 1, The storage electrode is non-overlapping with the bit line, the semiconductor device characterized in that formed in the form of a rectangle (long) formed in the long axis direction of the bit line. Forming an isolation layer defining an active region on the semiconductor substrate; Forming a word line overlapping the active region; Forming a bit line by connecting one side of the active region; Forming a storage electrode connected to the other side of the active region. The method according to claim 8, The storage electrode is a semiconductor device forming method, characterized in that formed in a planar shape of a rectangle (long rectangle) having a long axis in the bit line direction.

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