KR20100036612A - Method for forming via of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a via of a semiconductor device is provided to prevent plasma damage generation in forming a via. CONSTITUTION: Patterning is performed after forming a metal wiring in a lower lawyer(S201). A interlayer dielectric layer is formed on a lower-layer and a metal wiring through patterning(S203). A barrier layer is formed on the interlayer dielectric layer(S209). A hard mask pattern is located on the barrier layer and defines a via region(S211). A wet etching is performed by using the hard mask pattern as an etching mask(S213). The wet etching selectively removes the open area of the barrier layer.

Description

Via formation method of semiconductor device {METHOD FOR FORMING VIA OF SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a via of a semiconductor device, and more particularly, to a method of forming a via for electrical connection of a metal wiring included in a semiconductor device.

Among the semiconductor devices, CMOS image sensor has an integrated circuit including hundreds of thousands to millions of pixels that convert light energy into an electrical signal. Is a semiconductor device that converts and outputs an electrical signal.

The CMOS image sensor is composed of a plurality of pixels, each pixel including a photo diode and at least one transistor (eg, a MOSFET) according to its structure. When light is incident on the photodiode, which is a light receiving unit, light energy is converted into an electrical signal through the photodiode, and the electrical signal is output through the transistor. To this end, it includes a plurality of metal wires for transmitting the electrical signal and the control signals for controlling the operation of each transistor. The metal wiring is formed at a position that does not overlap with the photodiode formed on the semiconductor substrate to prevent light incident to the photodiode from being externally blocked by the metal wiring.

On the other hand, when comparing the characteristics of the CMOS image sensor, three characteristics are compared. The dark signal, the dark defect, and the white signal. However, one of the dark defects, which indicates a measure of an abnormal pixel signal at low light, is affected by the via formation process for metallization.

1 is a cross-sectional view of a semiconductor device in which vias are formed by a via formation method according to the prior art, and FIG. 2 is a flowchart illustrating a via formation method according to the prior art.

A via forming method of a semiconductor device according to the prior art will be described with reference to FIGS. 1 and 2 as follows.

First, metal wirings 13, 15, and 17 are formed on a lower layer 11 such as a semiconductor substrate or an oxide film. The metal wires 13, 15, and 17 are, for example, a metal layer 15 on which aluminum (Al) is deposited, and a lower barrier layer 13 and an upper barrier on which a titanium film (Ti) / titanium nitride film (TiN) is sequentially deposited. It is formed into a film 17. Thereafter, the upper barrier layer 17, the metal layer 15, and the lower barrier layer 13 are etched using the photosensitive layer pattern to pattern the metal lines 13, 15, and 17 (S31).

In addition, an IMD (Inter Metal Dielectric) film 19 used as an interlayer insulating film is formed on the lower layer 11 and the metal wirings 13, 15, and 17 exposed by patterning (S33), and chemical mechanical polishing (Chemical) Mechanical Polishing (CMP) is performed to planarize the IMD film 19 (S35).

Subsequently, for example, a silicon nitride film (SiN) is deposited on the flattened IMD film 19 to protect the device from external moisture and scratches (S37).

Next, a photoresist pattern 23 defining a via region is formed on the barrier layer 21 (S39), and a reactive ion etching (RIE) process using the photoresist pattern 23 as an etching mask is performed. The barrier layer 21 and the IMD layer 19 which are opened by the photoresist layer pattern 23 are sequentially dry-etched to form the vias 25 (S41).

As described above, according to the method of forming a via of a semiconductor device according to the related art, it can be seen that a reactive ion etching process is performed to etch films on the metal wiring to form a via.

However, according to the related art, plasma damage occurs during reactive ion etching, and thus dark defects may occur. This has a problem of decreasing the characteristics of the semiconductor device, in particular the sensitivity of the CMOS image sensor.

The present invention has been proposed to solve the problems of the prior art, and improves the characteristics of the semiconductor device by blocking the generation of plasma damage by applying wet etching to the etching process for forming vias without using reactive ion etching.

In the method of forming a via of a semiconductor device according to an embodiment of the present invention, a method of forming a via is formed by forming a metal wiring on a lower layer, and forming an interlayer insulating film on the lower layer and the metal wiring exposed by the patterning. Forming a barrier layer on the barrier layer, forming a hard mask pattern defining a via region on the barrier layer, and wet etching using the hard mask pattern as an etch mask to selectively select an open region of the barrier layer. And removing the open regions of the hard mask pattern and the interlayer insulating layer through wet etching to form vias that reach the metal wiring.

The forming of the interlayer insulating film may include forming a first IMD film planarized to a height of the metal wiring on the lower layer, and forming a second IMD film on the first IMD film and the metal wiring. It includes.

The forming of the hard mask pattern may include forming an oxide layer on the barrier layer and opening the via region through wet etching of the oxide layer using a photoresist pattern.

In the forming of the hard mask pattern, the hard mask pattern is formed of the same material as the interlayer insulating layer.

In the forming of the via, an etchant having a higher etching rate of the hard mask pattern is used in a relative etching rate of the hard mask pattern and the barrier layer.

The step of selectively removing the open area of the barrier layer uses an etchant having a higher etch rate of the barrier layer in an etching rate relative to the hard mask pattern and the barrier layer.

According to the present invention, wet etching is applied to the etching process for forming vias to prevent plasma damage by applying wet etching to improve the characteristics of the semiconductor device. In particular, the CMOS image sensor has an effect of improving the sensitivity by blocking the occurrence of dark defects that may be caused by plasma damage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

3A to 3E are cross-sectional views of a semiconductor device for describing a method of forming a via according to the present invention, and FIG. 4 is a flowchart illustrating a method of forming a via according to the present invention.

Referring to FIG. 4, a process flow of a method of forming a via according to an embodiment of the present invention is illustrated by forming and patterning a metal wiring on a lower layer (S201), and forming a first IMD layer used as a first interlayer insulating layer on a lower layer. Step S203, planarizing the first IMD film to the height of the metal wiring (S205), forming a second IMD film on the first IMD film and the metal wiring (S207), and on the second IMD film After forming the barrier layer (S209) and forming a hard mask on the barrier layer using the same material as the second IMD layer, the hard mask pattern is defined by opening the via region through wet etching of the hard mask using the photoresist pattern. (S211) and the wet etching using the hard mask pattern as an etching mask using an etching solution having a higher etching rate of the barrier film in the etching rate relative to the hard mask pattern and the barrier film. After the barrier layer is selectively removed, the hard mask pattern and the open area of the interlayer insulating layer are removed by wet etching using an etchant having a higher etching rate of the hard mask pattern in the relative etching rate to the barrier layer. To form vias up to the metallization (S213).

Referring to FIGS. 3A to 3E, the manufacturing process of the semiconductor device by the via forming method according to the present invention will be described.

Referring to FIG. 3A, metal wirings 103, 105, and 107 are formed on a lower layer 101 such as a semiconductor substrate or an oxide film. The metal wires 103, 105, and 107 may be formed of, for example, a double layer in which a metal film 105 on which aluminum (Al) is deposited, and a double film in which a titanium film (Ti) / titanium nitride film (TiN) is sequentially deposited are formed on the lower barrier film (103). The upper barrier layer 107 may be formed. Thereafter, the upper barrier layer 107, the metal layer 105, and the lower barrier layer 103 are etched using the photosensitive layer pattern to pattern the metal lines 103, 105, and 107 (S201).

Referring to FIG. 3B, a first IMD film 109 used as a first interlayer insulating film is formed on the lower layer 101 and the metal wirings 103, 105, and 107 exposed by patterning (S203). For example, the first IMD film 109 is formed by depositing an oxide film such as a USG (Undoped Silicate Glass) film. The first IMD film 109 is planarized by performing a chemical mechanical polishing process until the upper barrier film 107 is exposed. That is, the first IMD film 109 planarized to the height of the metal wirings 103, 105, and 107 is formed on the lower layer 101 (S205).

In this case, the upper barrier layer 107 may be damaged by the chemical mechanical polishing process, and thus the buffer layer may be formed on the lower layer 101 and the metallization lines 103, 105, and 107 before the first IMD layer 109 is formed. May be omitted).

Referring to FIG. 3C, a second IMD film 110 used as a second interlayer insulating film is formed on the planarized first IMD film 109 and the metal wires 103, 105, and 107 (S207). The second IMD film 110 is preferably formed of the same material as that of the first IMD film 109. For example, the second IMD film 110 is formed by depositing an oxide film such as a USG film with a thickness of 2,700 kPa to 3,300 kPa.

Meanwhile, the present embodiment has been described in the case where the IMD film used as the interlayer insulating film is formed by dividing it into step S203 and step S207. However, after forming the same thickness as the thickness formed twice, the step S205 is formed at once. May be performed.

Referring to FIG. 3D, a barrier film 111 is formed on the second IMD film 110 to protect the device from external moisture and scratches (S209). The barrier film 111 is preferably formed to have the same thickness as that of the second IMD film 110. For example, the barrier film 111 is formed by depositing a nitride film such as silicon nitride (SiN) to a thickness of 2,700 kPa to 3,300 kPa.

A hard mask pattern 113 defining a via region is formed on the barrier layer 111 (S211). The hard mask pattern 113 may be formed of a different material when the etching characteristic thereof is compared with that of the barrier layer 111, and may be formed of the same material when compared with the material of the second IMD layer 110. For example, the second IMD film 110 is formed by depositing an oxide film such as a USG film to a thickness of 3,600 kPa to 4,400 kPa, and opening the via region through wet etching of the oxide film using the photosensitive film pattern. In this case, for example, dilute hydrofluoric acid (buffered HF) is used as the etching solution. Since the etching rate of the USG film is very high in the relative etching rates of the USG film and the silicon nitride film, the hard mask pattern 113 is ideally formed. . In addition, when the hard mask pattern 113 is completed, the photoresist pattern is removed by cleaning or the like.

Referring to FIG. 3E, wet etching using the hard mask pattern 113 as an etching mask is performed to selectively remove the open region of the barrier layer 111. In this case, for example, phosphoric acid (H ₃ PO ₄ ) is used as an etchant. Since the etching rate of the silicon nitride film is very high in the relative etching rates of the USG film and the silicon nitride film, the open area of the barrier film 111 is increased. Ideally it is removed.

Next, the open area of the hard mask pattern 113 and the second IMD layer 110 on the barrier layer 111 are removed by wet etching to complete the vias 115 extending to the metal lines 103, 105, and 107. (S213). At this time, for example, dilute hydrofluoric acid is used as the etching solution. Since the etching rate of the USG film is very high in the etching rate relative to the USG film and the silicon nitride film, the via 115 is ideally formed.

It has been described so far limited to one embodiment of the present invention, it is obvious that the technology of the present invention can be easily modified by those skilled in the art. Such modified embodiments should be included in the technical spirit described in the claims of the present invention.

1 is a cross-sectional view of a semiconductor device in which vias are formed by a via forming method according to the prior art;

2 is a flowchart illustrating a method of forming a via according to the prior art;

3A to 3E are cross-sectional views of a semiconductor device for describing a method of forming a via according to the present invention;

4 is a flow chart illustrating a method of forming a via in accordance with the present invention.

<Explanation of symbols for the main parts of the drawings>

101: lower layer 103: lower barrier film

105: metal film 107: upper barrier film

109: first IMD film 110: second IMD film

111: barrier film 113: hard mask pattern

115: Via

Claims (6)

Patterning after forming the metallization on the lower layer; Forming an interlayer insulating film on the lower layer and the metal wiring exposed by the patterning; Forming a barrier film on the interlayer insulating film; Forming a hard mask pattern defining a via region on the barrier layer; Selectively removing the open area of the barrier layer by performing wet etching using the hard mask pattern as an etching mask; Removing vias of the hard mask pattern and the interlayer insulating layer through wet etching to form vias that reach the metal wirings; Via forming method of a semiconductor device comprising a. The method of claim 1, Forming the interlayer insulating film, Forming a first IMD (Inter Metal Dielectric) film planarized to the height of the metal wiring on the lower layer; Forming a second IMD film on the first IMD film and the metal wiring; Via forming method of a semiconductor device comprising a. The method of claim 1, Forming the hard mask pattern, Forming an oxide film on the barrier film; Opening the via region by wet etching the oxide layer using a photoresist pattern Via forming method of a semiconductor device comprising a. The method of claim 1, Forming the hard mask pattern, Forming the hard mask pattern of the same material as the interlayer insulating film A method of forming vias in semiconductor devices. The method according to claim 1 or 4, Forming the vias, In the etching rate relative to the hard mask pattern and the barrier layer, an etchant having a higher etching rate of the hard mask pattern is used. A method of forming vias in semiconductor devices. The method of claim 1, Selectively removing the open area of the barrier film, In the etching rate relative to the hard mask pattern and the barrier layer, an etchant having a higher etching rate of the barrier layer is used. Method for forming vias in semiconductor device.

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