KR20100035233A - Circuit for generating pumping voltage of semiconductor memory apparatus - Google Patents

Circuit for generating pumping voltage of semiconductor memory apparatus Download PDF

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Publication number
KR20100035233A
KR20100035233A KR1020080094477A KR20080094477A KR20100035233A KR 20100035233 A KR20100035233 A KR 20100035233A KR 1020080094477 A KR1020080094477 A KR 1020080094477A KR 20080094477 A KR20080094477 A KR 20080094477A KR 20100035233 A KR20100035233 A KR 20100035233A
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KR
South Korea
Prior art keywords
signal
oscillator
pumping
enabled
oscillator signal
Prior art date
Application number
KR1020080094477A
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Korean (ko)
Inventor
최영경
최향화
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주식회사 하이닉스반도체
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Priority to KR1020080094477A priority Critical patent/KR20100035233A/en
Publication of KR20100035233A publication Critical patent/KR20100035233A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

PURPOSE: A pumping voltage generating circuit of a semiconductor memory device is provided to enable a pumping voltage to rapidly reach a target level by generating an oscillator signal according to a first and a second frequency based on a predetermined time. CONSTITUTION: A pumping operation control part(100) generates an oscillator signal if a pump enable signal is enabled. The pumping operation control part generates the oscillator signal of the first frequency during designated time if the pumping enable signal(pump_en) is enabled. The pumping operation control part generates the oscillator signal of the secondary frequency after the designated time. A pumping part(300) executes a pumping operation in response to the oscillator signal. The pumping part executes the pumping voltage through the pumping operation.

Description

Circuit for Generating Pumping Voltage of Semiconductor Memory Apparatus}

The present invention relates to a semiconductor memory device, and more particularly to a pumping voltage generation circuit.

In general, in DRAM, the internal power source is separately made in order to reduce the current consumption without being affected by the external voltage change. Among these internal power supplies, the pumping voltage has a higher voltage level than the external voltage.

As shown in FIG. 1, a general pumping voltage generation circuit includes an oscillator 10 and a pumping unit 20.

The oscillator 10 generates an oscillator signal osc when the pump enable signal pump_en is enabled. In this case, the pump enable signal pump_en is a signal generated by a pumping voltage detector. When the level of the pumping voltage VPP is lower than a target level, the pump enable signal pump_en is enabled. Let's do it.

The pumping unit 20 performs a pumping operation in response to the oscillator signal osc, and generates the pumping voltage VPP by the pumping operation.

The pumping voltage VPP is generated through the pumping operation at a voltage level higher than an external voltage. Therefore, several pumping operations must be performed for the pumping voltage VPP to reach a target level.

Since the oscillator signal osc is a signal that has a constant frequency and repeatedly transitions from a high level to a low level, the pumping unit 20 performing the pumping operation by the oscillator signal osc is the pumping voltage VPP. Constant time is required to reach the target level.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problem, and an object thereof is to provide a pumping voltage generation circuit of a semiconductor memory device capable of reaching a pumping voltage at a target level faster than a general pumping voltage generation circuit.

The pumping voltage generation circuit of the semiconductor memory device according to an embodiment of the present invention generates an oscillator signal when the pump enable signal is enabled, and generates the oscillator signal of the first frequency for a predetermined time when the pump enable signal is enabled. And a pumping operation controller configured to generate the oscillator signal at a second frequency after a predetermined time, and a pumping unit configured to perform a pumping operation in response to the oscillator signal, and generate the pumping voltage through the pumping operation.

The pumping voltage generation circuit of the semiconductor memory device according to the present invention can reach the target voltage faster than the general pumping voltage generation circuit, thereby increasing the voltage stability of the semiconductor memory device and reliability of the semiconductor memory operation in which the pumping voltage is used. It is effective to increase.

As illustrated in FIG. 2, the pumping voltage generation circuit of the semiconductor memory device according to an exemplary embodiment of the present invention includes an oscillator period control unit 100, a variable period oscillator 200, and a pumping unit 300. In this case, the oscillator period control unit 100 and the period variable oscillator 200 may be referred to as a pumping operation control unit. This is because the pumping frequency of the pumping unit 300 is controlled.

The pumping operation controller generates an oscillator signal osc when the pump enable signal pump_en is enabled, and generates the oscillator signal osc of the first frequency for a predetermined time when the pump enable signal pump_en is enabled. And generate the oscillator signal osc of the second frequency after a predetermined time. In this case, the first frequency is higher than the second frequency.

The oscillator period control unit 100 generates a control signal ctrl that is enabled for a predetermined time when the pump enable signal pump_en is enabled.

The variable period oscillator 200 generates an oscillator signal osc when the pump enable signal pump_en is enabled, and disables the control signal ctrl when the control signal ctrl is enabled. It produces the oscillator signal osc at a higher frequency than it is.

The pumping unit 300 performs a pumping operation in response to the oscillator signal osc and generates a pumping voltage VPP through the pumping operation.

As shown in FIG. 3, the oscillator period controller 100 includes a first inverter IV11, a delay, and a first NOR gate NOR11. The first inverter IV11 receives the pump enable signal pump_en. The delay unit receives an output signal of the first inverter IV11. The first NOR gate NOR11 receives the pump enable signal pump_en and an output signal of the delay and outputs the control signal ctrl.

When the pump enable signal pump_en is enabled, the oscillator period controller 100 generates the control signal ctrl that is enabled for a predetermined time, that is, for a delay time of the delay, thereby generating a pulse. It can also be called wealth.

As illustrated in FIG. 4, the periodic variable oscillator 200 includes a signal inverting unit 210 and a variable delay unit 220.

When the pump enable signal pump_en is enabled, the signal inverting unit 210 inverts the delay oscillator signal osc_dl and outputs the oscillator signal osc.

The signal inverting unit 210 includes a second NOR gate NOR21 and second to fifth inverters IV21 to IV24. The second NOR gate NOR21 receives the pump enable signal pump_en and the delay oscillator signal osc_dl. The second inverter IV21 receives the output signal of the second NOR gate NOR21. The third inverter IV22 receives the output signal of the second inverter IV21. The fourth inverter IV23 receives the output signal of the third inverter IV22. The fifth inverter IV24 receives the output signal of the fourth inverter IV23 and outputs the oscillator signal osc.

When the control signal ctrl is enabled, the variable delay unit 220 delays the oscillator signal osc with a shorter delay time than when it is disabled and outputs the delayed oscillator signal osc_dl.

The variable delay unit 220 includes second to fourth NOR gates NOR22 to NOR24, and sixth to tenth inverters IV25 to IV29. The sixth inverter IV25 receives the control signal ctrl. The third NOR gate NOR22 receives an output signal of the sixth inverter IV25 and the oscillator signal osc. The fourth NOR gate NOR23 receives the control signal ctrl and the oscillator signal osc. The seventh inverter IV26 receives the output signal of the fourth NOR gate NOR23. The eighth inverter IV27 receives the output signal of the seventh inverter IV26. The ninth inverter IV28 receives the output signal of the eighth inverter IV27. The tenth inverter IV29 receives the output signal of the ninth inverter IV28. The fifth NOR gate NOR24 receives the output signal of the third NOR gate NOR22 and the output signal of the tenth inverter IV29, and outputs the delay oscillator signal osc_dl.

The operation of the periodic variable oscillator 200 configured as described above will be described briefly as follows. In this case, it is assumed that the pump enable signal pump_en is a signal enabled at a low level.

When the control signal ctrl is enabled at the high level, the sixth inverter IV25 outputs a low level signal to the third NOR gate NOR22. Accordingly, the third NOR gate NOR22 may invert and output the oscillator signal osc. When the control signal ctrl is enabled at the high level, the fourth NOR gate NOR23 outputs only a low level signal regardless of the level of the oscillator signal osc. The seventh to tenth inverters IV26 to IV29 are output from the fourth NOR gate NOR23 because an even number is connected in series between the fourth NOR gate NOR23 and the fifth NOR gate NOR24. The level of the signal is transferred to the fifth NOR gate NOR24 as it is. Accordingly, the fifth NOR gate NOR24 that receives the output signal of the tenth inverter IV29 outputting the low level signal inverts the output signal of the third NOR gate NOR22 so that the delay oscillator signal osc_dl Output as

As a result, when the control signal ctrl is enabled, the oscillator signal osc is output as the delay oscillator signal osc_dl through the second and fourth NOR gates NOR22 and NOR24.

When the control signal ctrl is disabled at a low level, the third NOR gate NOR22 receives a high level signal and outputs only a low level signal regardless of the level of the oscillator signal osc. When the control signal ctrl is disabled at the low level, the fourth NOR gate NOR23 may invert and output the oscillator signal osc. The output signal of the fourth NOR gate NOR23 is input to the fifth NOR gate NOR24 via the seventh to tenth inverters IV26 to IV29. Accordingly, the fifth NOR gate NOR24 receiving the output signal of the third NOR gate NOR22 and the output signal of the tenth inverter IV29 inverts the output signal of the tenth inverter VI29 to delay the delay. It outputs as an oscillator signal osc_dl.

As a result, when the control signal ctrl is disabled, the oscillator signal osc is the fourth NOR gate NOR23, the seventh to tenth inverters IV26 to IV29, and the fifth NOR gate NOR24. The delay oscillator is output as the delay oscillator signal osc_dl.

When the control signal ctrl is enabled, the variable delay unit 220 delays the oscillator signal osc by outputting the delayed oscillator signal osc_dl by shortening a delay time than when disabled.

The signal inverting unit 210 receives the delay oscillator signal osc_dl and inverts it to output the oscillator signal osc.

The periodic variable oscillator 200 including the signal inverting unit 210 and the variable delay unit 220 may have the oscillator signal having a shorter period than when it is disabled when the control signal ctrl is enabled. osc) can be generated.

The pumping voltage generation circuit of the semiconductor memory device according to the embodiment configured as described above operates as follows.

First, the pump enable signal pump_en is a signal generated by the pumping voltage detector and is enabled when the pumping voltage VPP is lower than the target level.

When the pump enable signal pump_en is enabled because the pumping voltage VPP is lower than the target level, the pump enable signal pump_en is enabled and the control signal ctrl is enabled.

When both the pump enable signal pump_en and the control signal ctrl are enabled, the oscillator signal osc may only display the control signal ctrl of the pump enable signal pump_en and the control signal ctrl. The frequency is higher than when enabled.

The pumping unit 300 that receives the oscillator signal osc and performs a pumping operation has a higher pumping frequency than when the oscillator signal osc having a low frequency is input due to the oscillator signal osc having a higher frequency.

As a result, the pumping unit 300 may increase the voltage rising rate of the pumping voltage VPP during the period in which the control signal ctrl is enabled.

Therefore, the pumping voltage generation circuit of the semiconductor memory device according to the present invention enables the pumping voltage to reach the target level faster than the general pumping voltage generation circuit, thereby improving voltage stability of the semiconductor memory device and operating the semiconductor memory in which the pumping voltage is used. It has the effect of increasing the reliability of.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a configuration diagram of a pumping voltage generation circuit of a general semiconductor memory device;

2 is a configuration diagram of a pumping voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a detailed circuit diagram of the oscillator period control unit of FIG. 2;

4 is a detailed circuit diagram of the periodic variable oscillator of FIG. 2.

<Description of the symbols for the main parts of the drawings>

100: oscillator period control unit 200: period variable oscillator

300: pumping part

Claims (6)

A pimp that generates an oscillator signal when a pump enable signal is enabled, and generates the oscillator signal at a first frequency for a predetermined time when the pump enable signal is enabled and generates the oscillator signal at a second frequency after a predetermined time. An operation controller; And And a pumping unit configured to perform a pumping operation in response to the oscillator signal and to generate the pumping voltage through the pumping operation. The method of claim 1, And the first frequency is higher than the second frequency. The method of claim 1, The pumping operation control unit An oscillator period controller configured to generate a control signal enabled for a predetermined time when the pump enable signal is enabled, and And a periodic variable oscillator generating the oscillator signal when the pump enable signal is enabled, and generating the oscillator signal with a shorter period than when disabled when the control signal is enabled. Pumping voltage generation circuit of the memory device. The method of claim 3, wherein The oscillator period control unit And a pulse generator configured to generate the control signal enabled for a predetermined time when the pump enable signal is enabled. The method of claim 3, wherein The periodic variable oscillator A signal inverting unit inverting a delay oscillator signal and outputting the delay oscillator signal when the pump enable signal is enabled, and And a variable delay unit configured to delay the oscillator signal with a delay time shorter than when disabled when the control signal is enabled and output the delayed oscillator signal as the delay oscillator signal. The method of claim 1, And a pumping voltage detector for enabling the pump enable signal when the pumping voltage is lower than a target level.
KR1020080094477A 2008-09-26 2008-09-26 Circuit for generating pumping voltage of semiconductor memory apparatus KR20100035233A (en)

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KR1020080094477A KR20100035233A (en) 2008-09-26 2008-09-26 Circuit for generating pumping voltage of semiconductor memory apparatus

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Application Number Priority Date Filing Date Title
KR1020080094477A KR20100035233A (en) 2008-09-26 2008-09-26 Circuit for generating pumping voltage of semiconductor memory apparatus

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KR20100035233A true KR20100035233A (en) 2010-04-05

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