KR20100032190A - Nonvolatile memory device and memory system including the same - Google Patents

Abstract

PURPOSE: A non-volatile memory device and a memory system thereof are provided to reduce the influence of coupling by reducing the number of cell strings influencing the coupling. CONSTITUTION: A memory cell array(210) comprises a first or a sixth cell strings(CS1~CS6), a switching circuit(211) and ground selection transistor(GST). Each cell string comprises a plurality of memory cells which are serially connected. Memory cells are connected to word lines. The switching circuit selectively electrically connects a first and a second cell strings to a first bit line(BL1). The third and the fourth cell strings are selectively electrically connected to a second bit line(BL2). The fifth and the sixth cell strings are selectively electrically connected to a third bit line(BL3). The switching circuit operates according to signals delivered through a first and a second control lines(CL1,CL2).

Description

A nonvolatile memory device and a memory system including the same {NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME}

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device and a memory system including the same.

A semiconductor memory device is a memory device that stores data and can be read out when needed. Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

Volatile memory devices lose their stored data when their power supplies are interrupted. Volatile memory devices include SRAM, DRAM, SDRAM, and the like. Nonvolatile memory devices are memory devices that do not lose their stored data even when their power supplies are interrupted. Nonvolatile memory devices include ROM, PROM, EPROM, EEPROM, flash memory devices, PRAM, MRAM, RRAM, FRAM, and the like. Flash memory devices are roughly divided into NOR type and NAND type.

It is an object of the present invention to provide a nonvolatile memory device which reduces the influence of the coupling and a memory system comprising the same.

In an embodiment, a nonvolatile memory device may include first to fourth cell strings sequentially arranged in a row direction; And a switch circuit for selectively electrically coupling the first to fourth cell strings to first and second bit lines, the switch circuit configured to connect the first and fourth cell strings in a first mode of operation. And electrically connect the first and second bit lines, respectively, and electrically connect the second and third cell strings to the first and second bit lines, respectively, in a second mode of operation.

In example embodiments, the switch circuit may include a transistor connected between the first cell string and the first bit line and controlled by a first control line; And a transistor connected between the second cell string and the first bit line and controlled by a second control line. The switch circuit is coupled between the third cell string and the second bit line, the transistor being controlled by the second control line; And a transistor connected between the fourth cell string and the second bit line and controlled by the first control line.

In an embodiment, during a read operation, a bias voltage for a read operation is alternately applied to the first and second bit lines.

In an embodiment, in a read operation, a bias voltage for a read operation is simultaneously applied to the first and second bit lines.

According to at least one example embodiment of the inventive concepts, a method of operating a nonvolatile memory device including first to fourth cell strings sequentially arranged in a row direction may include the first and fourth cell strings and the first cell string when a program operation is performed. Alternately performing program operations on the second and third cell strings.

In an embodiment, the first and second cell strings are selectively electrically connected to a first bit line, and the third and fourth cell strings are selectively electrically connected to a second bit line. In a read operation, a bias voltage for a read operation is simultaneously applied to the first and second bit lines. In a read operation, a bias voltage for a read operation is alternately applied to the first and second bit lines.

In an embodiment, a memory system may include a nonvolatile memory device; And a controller for controlling the nonvolatile memory device, wherein the nonvolatile memory device comprises: first to fourth cell strings sequentially arranged along a row direction; And a switch circuit for selectively electrically coupling the first to fourth cell strings to first and second bit lines, the switch circuit configured to connect the first and fourth cell strings in a first mode of operation. Electrically connect first and second bit lines, respectively, and electrically connect the second and third cell strings to the first and second bit lines, respectively, in a second mode of operation.

In an embodiment, the nonvolatile memory device and the controller are integrated into one semiconductor device.

In an embodiment, the nonvolatile memory device and the controller form a memory card.

In an embodiment, the nonvolatile memory device and the controller form a semiconductor disk device.

In an embodiment, the controller communicates with an external host.

According to the present invention, only one cell string of adjacent cell strings is programmed. That is, since the number of cell strings affecting the coupling is reduced, the influence of the coupling is reduced.

The nonvolatile memory device according to an embodiment of the present invention selectively electrically connects the first to fourth cell strings and the first to fourth cell strings to the first and second bit lines sequentially arranged along the row direction. A first switch circuit for connecting, the first switch circuit electrically connecting the first and fourth cell strings to the first and second bit lines, respectively, in the first mode of operation, and in the second mode of operation. The second and third cell strings are electrically connected to the first and second bit lines, respectively. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

1 is a block diagram illustrating a memory system 10 according to an exemplary embodiment of the inventive concept. Referring to FIG. 1, a memory system 10 according to an embodiment of the present invention includes a nonvolatile memory device 200 and a controller 100.

The controller 100 is connected to a host and the nonvolatile memory device 200. The controller 100 transfers data read from the nonvolatile memory device 200 to the host, and stores data transferred from the host in the nonvolatile memory device 200.

Controller 100 will include well known components such as RAM, processing unit, host interface, and memory interface. The RAM will be used as the operating memory of the processing unit. The processing unit will control the overall operation of the controller 100. The host interface will include a protocol for performing data exchange between the host and the controller 100. In exemplary embodiments, the controller 100 may include one of various interface protocols such as USB, MMC, PCI-E, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, SCSI, ESDI, and Integrated Drive Electronics (IDE). It will be configured to communicate with the outside (host) through one. The memory interface will interface with the nonvolatile memory device 200. The controller 100 may further include an error correction block. The error correction block detects and corrects an error of data read from the nonvolatile memory device 200.

The nonvolatile memory device 200 may include a memory cell array for storing data, a read / write circuit for writing and reading data to the memory cell array, and an address for decoding an address transmitted from an external source and transmitting the decoded address to a read / write circuit. It may include a decoder, control logic for controlling general operations of the nonvolatile memory device 200, and the like. The nonvolatile memory device 200 is described in more detail with reference to FIGS. 2 and 3.

The controller 100 and the nonvolatile memory device 200 may be integrated into one semiconductor device. In exemplary embodiments, the controller 100 and the nonvolatile memory device 200 may be integrated into one semiconductor device to constitute a memory card. For example, the controller 100 and the nonvolatile memory device 200 may be integrated into one semiconductor device such that a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM / SMC), a memory stick, and a multimedia device are provided. Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD), universal flash storage (UFS) and the like.

As another example, the controller 100 and the nonvolatile memory device 200 may be integrated into one semiconductor device to form a solid state disk / drive (SSD). When the memory system 10 is used as the semiconductor disk SSD, the operating speed of the host connected to the memory system 10 may be improved.

As another example, memory system 10 may be a PDA, portable computer, web tablet, wireless phone, mobile phone, digital music player, or information. It will be applied to devices that can transmit and receive in a wireless environment.

As another example, the nonvolatile memory device 200 or the memory system 10 may be mounted in various types of packages. For example, the nonvolatile memory device 200 or the memory system 10 may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) It will be packaged and implemented in the same way as a Wafer-Level Processed Stack Package (WSP).

FIG. 2 is a block diagram illustrating the nonvolatile memory device 200 of FIG. 1. 2, a nonvolatile memory device 200 according to an embodiment of the present invention includes a memory cell array 210, a read / write circuit 220, an address decoder 230, and a control logic 240. do.

The memory cell array 210 is connected to the read / write circuit 220 through the bit lines BL and to the address decoder 230 through the word lines WL. The memory cell array 210 includes a plurality of memory cells for storing data transferred from the read / write circuit 220. In exemplary embodiments, the memory cells may be arranged in a matrix, and the memory cells may be connected to the word lines WL and the bit lines BL.

The read / write circuit 220 is connected to the memory cell array 210 through the bit lines BL. The read / write circuit 220 operates under the control of the control logic 240. The read / write circuit 220 receives data DATA from the outside and stores the data DATA in the memory cell array 210. The read / write circuit DATA reads data DATA from the memory cell array 210 and transfers the data DATA to the outside. In exemplary embodiments, the read / write circuit 220 may exchange data DATA with the controller 100 of FIG. 1.

In exemplary embodiments, the read / write circuit 220 may include well-known components, such as a column select gate, a page buffer, a data buffer, and the like. As another example, read / write circuit 220 may include well-known components, such as column select gates, write drivers, sense amplifiers, data buffers, and the like.

The address decoder 230 is connected to the memory cell array 210 through word lines WL. The address decoder 230 operates under the control of the control logic 240. The address decoder 230 receives and decodes an address ADDR from the outside. The address decoder 230 selects word lines WL by decoding the row address. The address decoder 230 decodes the column addresses and transfers them to the read / write circuit 220, and the read / write circuit 220 selects the bit lines BL in response to the decoded column address. In exemplary embodiments, the address decoder 230 may receive an address ADDR from the controller 100 of FIG. 1. As an example, the address decoder 230 may include well known components such as a row decoder, column decoder, address buffer, and the like.

The control logic 240 is connected to the read / write circuit 220 and the address decoder 230. The control logic 240 controls overall operations of the nonvolatile memory device 200 in response to the control signal CTRL. In exemplary embodiments, the control signal CTRL may be provided from the controller 100 of FIG. 1.

Hereinafter, with reference to an example of a flash memory device, the technical spirit of the present invention will be described in more detail. However, it will be understood that the technical idea of the present invention is not limited to the flash memory device. For example, the technical spirit of the present invention may be applied to nonvolatile memory devices such as ROM, PROM, EPROM, EEPROM, flash memory devices, PRAM, MRAM, RRAM, FRAM, and the like, and volatile memory devices such as SRAM, DRAM, SDRAM, and the like. It will be appreciated that it can be applied.

3 is a circuit diagram illustrating the memory cell array 210 of FIG. 2 in more detail. Referring to FIG. 3, a memory cell array 210 according to an embodiment of the present invention is connected between cell strings CS1 to CS6, cell strings CS1 to CS6, and bit lines BL1 to BL3. Ground switch transistors GST are connected between the switch circuit 211, the cell strings CS1 to CS6, and the common source line CSL.

Each cell string includes a plurality of memory cells connected in series. The memory cells are connected to the word lines WL1 to WLn. In FIG. 3, the memory cell array 210 is illustrated as including six cell strings CS1 to CS6. However, it will be understood that the number of cell strings CS1 to CS6 is not limited.

The switch circuit 211 selectively electrically connects the cell strings CS1 and CS2 to the bit line BL1, selectively electrically connects the cell strings CS3 and CS4 to the bit line BL2, The cell strings CS5 and CS6 are selectively electrically connected to the bit line BL3. The switch circuit 211 operates in response to signals transmitted through the control lines CL1 and CL2.

The switch circuit 211 includes a transistor T2 electrically connected to the cell strings CS1 and CS2, respectively. Gates of the transistors T2 are connected to the control lines CL1 and CL2, respectively. The switch circuit 211 further includes depletion transistors T1 electrically connected to the cell strings CS1 and CS2, respectively. The depletion transistor T1 has a threshold voltage lower than the ground voltage. That is, the depletion transistor T1 will remain on. Therefore, when the activated signal is transmitted to the control line CL1, the cell string CS1 is electrically connected to the bit line BL1, and when the activated signal is transmitted to the control line CL2, the cell string CS2 is bitwise transmitted. Will be connected to line BL1.

The switch circuit 211 includes a transistor T2 electrically connected to the cell strings CS3 and CS4, respectively. Gates of the transistors T2 are connected to the control lines CL1 and CL2, respectively. The switch circuit 211 further includes depletion transistors T1 electrically connected to the cell strings CS3 and CS4, respectively. The depletion transistor T1 has a threshold voltage lower than the ground voltage. That is, the depletion transistor T1 will remain on. Accordingly, the cell string CS4 is electrically connected to the bit line BL2 when the activated signal is transmitted to the control line CL1, and the cell string CS3 is bitified when the activated signal is transmitted to the control line CL2. Will be connected to line BL2.

The switch circuit 211 includes a transistor T2 electrically connected to the cell strings CS5 and CS6, respectively. Gates of the transistors T2 are connected to the control lines CL1 and CL2, respectively. The switch circuit 211 further includes depletion transistors T1 electrically connected to the cell strings CS5 and CS6, respectively. The depletion transistor T1 has a threshold voltage lower than the ground voltage. That is, the depletion transistor T1 will remain on. Accordingly, the cell string CS5 is electrically connected to the bit line BL3 when the activated signal is transmitted to the control line CL1, and the cell string CS6 is bited when the activated signal is transmitted to the control line CL2. Will be connected to line BL3.

In an access operation of the memory cell array 210 of the nonvolatile memory device 200 (see FIGS. 1 and 2), two cell strings (for example, BL2) connected to one bit line (eg, BL2) may be used. For example, access will be performed alternately for CS3, CS4). For example, a program / read / write operation may be performed on the cell string CS3, and a program / read / write operation may be performed on the cell string CS4. As another example, a program / read / write operation may be performed on the cell string CS3, and a program / read / write operation may be performed on the cell string CS4.

For example, two cell strings (eg, CS3 and CS4) connected to one bit line (eg, BL2) may be an even cell string (eg, CS3) and an odd cell string (eg, a cell line). For example, it may be understood as CS4).

4 is a timing diagram illustrating bias voltages applied to the memory cell array 210 of FIG. 3 during a program operation. 3 and 4, the voltage Vcc at the bit lines BL1 to BL3, the control lines CL1 and CL2, the ground select line GSL, and the common source line CSL at a time t4. Is applied. That is, since the voltage Vcc is supplied to the cell strings CS1 to CS6 through the bit lines BL1 to BL2 and the voltage Vcc is supplied through the common source line CSL, the cell strings CS1 to CS6. The channel voltage of CS6 will be precharged to a preset voltage (for example, the difference between the voltage Vcc and the threshold voltages of the transistors T2 and GST).

At time t2, the pass voltage Vpass is applied to the selected word line (eg, WL1), and the pass voltage Vpass is applied to the unselected word lines (eg, WL2 to WLn). At this time, the channel voltages of the precharged cell strings CS1 to CS6 will be boosted to the voltage Vboost.

At time t3, the ground voltage Vss is provided to the control lines CL1 and CL2 and the ground select line GSL. That is, since the transistors T2 and the ground select transistors GST are turned off, the channel voltages of the cell strings CS1 to CS6 will maintain the voltage Vboost.

At time t4, the ground voltage Vss is applied to the bit lines BL1 to BL3 and the common source line CSL. Since the transistors T2 and the ground select transistor GST are turned off, the channel voltages of the cell strings CS1 to CS6 will maintain the voltage Vboost.

At time t5, voltage Vcc is applied to control line CL2. That is, the cell strings CS2, CS3, and CS6 are electrically connected to the bit lines BL1 to BL3, respectively. Since the ground voltage Vss is applied to the bit lines BL1 to BL3, the channel voltages of the cell strings CS2, CS3, and CS6 are set to the ground voltage Vss.

In this case, the channel voltages of the cell strings CS2, CS3, and CS6 are ground voltages Vss, and the channel voltages of the cell strings CS1, CS4, and CS5 maintain voltages Vboost. That is, the cell strings CS1, CS4, and CS5 are program inhibited, and the cell strings CS2, CS3, and CS6 are programmable. That is, even cell strings (eg, CS2, CS3, CS6) are programmed, and odd cell strings (eg, CS1, CS4, CS5) are program inhibited.

As another example, when time t5, the ground voltage Vss is applied to the control line CL2, and the voltage Vcc is applied to the control line CL1, the even cell strings (eg, CS2, The channel voltages of CS3 and CS6 will be program inhibited because they maintain the voltage Vboost. The channel voltage of the odd cell strings (e.g., CS1, CS4, CS5) will be programmed since it is the ground voltage Vss.

That is, when even cell strings (eg, CS2, CS3, CS6) are selected for the program among the cell strings CS1 to CS6, the voltage Vcc is applied to the control line CL1 at a time t5. Will be authorized. When odd cell strings (eg, CS1, CS4, CS5) are selected for a program among the cell strings CS1 to CS6, a voltage Vcc is applied to the control line CL2 at a time t5. will be.

For example, if even cell strings (eg, CS2, CS3, CS6) are selected to be programmed, a cell string that is prohibition of program among the even cell strings (eg, CS2, CS3, CS6) exists. The corresponding bit line will maintain voltage Vcc even after time t4. For example, when the cell string CS2 is program inhibited, the bit line BL1 voltage will maintain the voltage Vcc even after the time t4. At this time, the voltage Vcc is applied to the gate of the transistor T2 connected to the cell string CS2, and the voltage Vcc and the voltage Vboost are applied to the source and drain regions of the transistor T2. Vboost is a voltage at a level higher than the voltage Vcc. Therefore, since the transistor T2 maintains the turn-off state, the channel voltage of the cell string CS2 will maintain the voltage Vboost. That is, the cell string CS2 will be program inhibited.

Similarly, when the cell string CS3 is program inhibited, the bit line BL2 voltage will maintain the voltage Vcc even after the time t4. When the cell string CS4 is program inhibited, the bit line BL3 voltage may maintain the voltage Vcc even after the time t4. If odd cell strings (e.g., CS1, CS4, CS5) are selected to be programmed and some of the odd cell strings (e.g., CS1, CS4, CS5) are program inhibited, odd cell strings (e.g., For example, it will be appreciated that the bit line voltage corresponding to the program inhibited cell strings among CS1, CS4, CS5 maintains the voltage Vcc even after the time t4.

At time t6, the program voltage Vpgm is applied to the select word line (eg, WL1). At this time, the cell strings whose channel voltage is the voltage Vboost among the cell strings CS1 to CS6 are not programmed, and the cell strings whose channel voltage is the ground voltage Vss will be programmed. Then, at time t7 all bias voltages are set to ground voltage Vss.

At time t5, selected cell strings (eg, even cell strings) of odd cell strings (eg, CS1, CS4, CS5) and even cell strings (eg, CS2, CS3, CS6) (CS2, CS3, CS6) is provided with a ground voltage through the bit lines (BL1 ~ BL3). In addition, the channel voltage of the unselected cell strings (eg, odd cell strings CS1, CS4, and CS5) maintains a voltage Vboost. When the ground voltage Vss is applied to the selected cell strings CS2, CS3, and CS6, the channel voltages of the unselected cell strings CS1, CS4, and CS5 are changed due to channel to channel coupling. Will be reduced from the voltage Vboost. That is, since the efficiency of boosting for program prohibition is lowered, program disturb will occur.

In the conventional case, even cell strings and odd cell strings are alternately arranged along the row direction of the memory cell array. In other words, if the n (n is positive integer) th cell string along the row direction is an even cell string, the n + 1 and n-1 th cell strings along the row direction are odd cell strings. That is, an odd cell string is disposed between two even cell strings, and an even cell string is disposed between two odd cell strings. Therefore, if the ground voltage Vss is provided to the even cell strings at time t5, the odd cell string is affected by the coupling from two adjacent even cell strings. Similarly, if the ground voltage Vss is provided to the odd cell strings at time t5, the even cell string is affected by coupling from two adjacent odd cell strings.

According to an embodiment of the present invention for solving the above-described problems, the first and fourth cell strings and the first and fourth cell strings may be used during a program operation on the first to fourth cell strings sequentially arranged along the row direction. Alternately performing program operations on the second and third cell strings. That is, when the program operation is performed on the even cell strings CS2, CS3, and CS6, the odd cell strings CS1, CS4, and CS5 are set to prohibit program.

At this time, the odd cell string CS1 is affected by the coupling from the adjacent even cell string CS2. The odd cell string CS4 is affected by the coupling from the adjacent even cell string CS3. The odd cell string CS5 is affected by the coupling from the adjacent even cell string CS6. That is, in the program operation of the nonvolatile memory device 200 (refer to FIG. 2) according to an exemplary embodiment of the present disclosure, non-selected cell strings among even and odd cell strings may be affected by coupling from one adjacent selected cell string. Receive. Since the number of cell strings affecting coupling is reduced, the influence of coupling is reduced and program disturb is reduced / prevented.

Similarly, when a program operation is performed on the odd cell strings CS1, CS4, CS5, the even cell strings CS2, CS3, CS6 are set to prohibit program. At this time, the even cell string CS2 is affected by the coupling from the adjacent odd cell string CS1. The even cell string CS3 is affected by the coupling from the adjacent odd cell string CS4. The even cell string CS6 is affected by the coupling from the adjacent odd cell string CS5. That is, since the number of cell strings affecting the coupling is reduced, the influence of the coupling is reduced and program disturb is reduced / prevented.

Read operations are also performed alternately on even cell strings (eg, CS2, CS3, CS6) and odd cell strings (CS1, CS4, CS5). When an active signal is applied to the control line CL1, odd cell strings (eg, CS1, CS4, CS5) will be selected for the read operation. The read / write circuit 220 (see FIG. 2) will set up the bit lines BL1 to BL3 to the voltage Vbl. The voltage Vbl may be provided to odd cell strings (eg, CS1, CS4, CS5) through the switch circuit 211.

When an active signal is applied to the control line CL2, even cell strings (eg, CS2, CS3, CS6) will be selected for the read operation. The read / write circuit 220 (see FIG. 2) will set up the bit lines BL1 to BL3 to the voltage Vbl. The voltage Vbl may be provided to even cell strings (eg, CS2, CS3, CS6) through the switch circuit 211.

If the memory cell selected for the read operation is a non-programmed memory cell, the channel voltage of the corresponding cell string will be lowered from voltage Vbl to ground voltage Vss. If the memory cell selected for the read operation is a programmed memory cell, the channel voltage of the corresponding cell string will maintain the voltage Vbl. If a cell string in which the channel voltage is lowered to the ground voltage Vss and a cell string in which the channel voltage maintains the voltage Vbl are disposed adjacent to each other, coupling will occur between the two cell strings.

By way of example, assume that even cell strings (eg, CS2, CS3, CS6) are selected for a read operation. Further, it is assumed that memory cells corresponding to the cell strings CS2 and CS3 among the memory cells selected for the read operation are logic states '0' and '1', respectively.

In this case, since the memory cell of the cell string CS2 selected for the read operation is a programmed memory cell, the channel voltage of the cell string CS2 will maintain the voltage Vbl. Since the memory cell of the cell string CS3 selected for the read operation is an unprogrammed memory cell, the channel voltage of the cell string CS3 will be lowered from the voltage Vbl to the ground voltage Vss.

However, the cell strings CS2 and CS3 are disposed adjacent to each other. That is, the cell strings will be affected by the coupling between each other. Therefore, the channel voltage of the cell string CS2 will be lower than the voltage Vbl due to the influence of the coupling. In addition, the channel voltage of the cell string CS3 may be higher than the ground voltage Vss due to the influence of the coupling. That is, it will be understood that read disturb may occur in the cell strings CS2 and CS3.

In order to prevent the above-described problem, the nonvolatile memory device 200 (see FIG. 2) according to an embodiment of the present invention will set up the bit lines to the voltage Vbl alternately along the row direction. For example, the bit lines BL1 and BL3 may be set to the voltage Vbl, and the bit line BL2 may be set to the ground voltage Vss. A read operation may be performed on the cell strings CS1 / CS2 and CS5 / CS6 connected to the bit lines BL1 and BL3. Thereafter, the bit lines BL1 and BL3 will be set to the ground voltage Vss and the bit line B2 will be set to the voltage Vbl. A read operation may be performed on the cell strings CS3 / CS4 connected to the bit line BL2.

For example, the nonvolatile memory device 200 (refer to FIG. 2) according to an embodiment of the inventive concept may include the bit lines BL1 to BL3 as even bit lines (for example, BL2) and odd bit lines BL1. It may be understood that the operation is divided into BL3), and alternate read operations are performed on even and odd bit lines.

An embodiment of the present invention has been described with reference to FIGS. 2 to 4 and an example of a flash memory device. However, it will be understood that the technical idea of the present invention is not limited to the flash memory device. For example, the technical idea of the present invention includes a volatile memory device such as SRAM, DRAM, SDRAM, and the like, and a nonvolatile memory device such as a ROM, PROM, EPROM, EEPROM, flash memory device, PRAM, MRAM, RRAM, FRAM, or the like. It will be appreciated that it can be applied to various storage devices.

In FIG. 4, it is described that the power source Vcc is applied to the common source line CSL between the times t1 to t4. However, it will be understood that a voltage having a ground voltage Vss or other level may be applied to the common source line CSL instead of the power supply Vcc.

FIG. 5 is a block diagram illustrating an embodiment of a computing system 300 including the memory system 10 of FIG. 1. Referring to FIG. 5, a computing system 300 according to an embodiment of the present invention may include a central processing unit 310, a random access memory (RAM) 320, a user interface 330, a power source 340, and a memory. System 10.

The memory system 10 is electrically connected to the CPU 310, the RAM 320, the user interface 330, and the power source 340 through the system bus 350. Data provided through the user interface 330 or processed by the central processing unit 310 is stored in the memory system 10. The memory system 10 includes a controller 100 and a flash memory device 100.

When the memory system 10 is mounted as a semiconductor disk device (SSD), the booting speed of the computing system 300 may be dramatically increased. Although not shown in the drawings, it will be understood by those skilled in the art that the system according to the present invention may further include an application chipset, a camera image processor, and the like.

In the detailed description of the present invention, specific embodiments have been described, but it is obvious that various modifications can be made without departing from the scope and spirit of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the claims of the following.

1 is a block diagram illustrating a memory system according to an example embodiment of the disclosure.

FIG. 2 is a block diagram illustrating a nonvolatile memory device of FIG. 1.

3 is a circuit diagram illustrating the memory cell array of FIG. 2 in more detail.

4 is a timing diagram illustrating bias voltages applied to the memory cell array of FIG. 3 during a program operation.

Claims (14)

First to fourth cell strings sequentially arranged along the row direction; And A switch circuit for selectively electrically connecting the first to fourth cell strings to first and second bit lines; The switch circuit electrically connects the first and fourth cell strings to the first and second bit lines, respectively, in a first mode of operation and connects the second and third cell strings in a second mode of operation. And a nonvolatile memory device electrically connected to the first and second bit lines, respectively. The method of claim 1, The switch circuit A transistor connected between the first cell string and the first bit line and controlled by a first control line; And And a transistor coupled between the second cell string and the first bit line, the transistor being controlled by a second control line. The method of claim 2, The switch circuit A transistor connected between the third cell string and the second bit line and controlled by the second control line; And And a transistor coupled between the fourth cell string and the second bit line and controlled by the first control line. The method of claim 1, The nonvolatile memory device of claim 1, wherein a bias voltage for a read operation is alternately applied to the first and second bit lines. The method of claim 1, The nonvolatile memory device of claim 1, wherein a bias voltage for a read operation is simultaneously applied to the first and second bit lines. A method of operating a nonvolatile memory device including first to fourth cell strings sequentially arranged along a row direction: And performing a program operation on the first and fourth cell strings and the second and third cell strings alternately during a program operation. The method of claim 6, And the first and second cell strings are selectively electrically connected to a first bit line, and the third and fourth cell strings are selectively electrically connected to a second bit line. The method of claim 7, wherein And applying a bias voltage for a read operation to the first and second bit lines simultaneously in a read operation. The method of claim 7, wherein And applying a bias voltage for a read operation to the first and second bit lines in a read operation. Nonvolatile memory devices; And A controller for controlling the nonvolatile memory device, The nonvolatile memory device First to fourth cell strings sequentially arranged along the row direction; A switch circuit for selectively electrically connecting the first to fourth cell strings to first and second bit lines; The switch circuit electrically connects the first and fourth cell strings to first and second bit lines, respectively, in a first mode of operation and respectively connects the second and third cell strings in a second mode of operation. And a memory system electrically connected to the first and second bit lines. The method of claim 10, And the nonvolatile memory device and the controller are integrated into one semiconductor device. The method of claim 10, And the nonvolatile memory device and the controller form a memory card. The method of claim 10, And the nonvolatile memory device and the controller form a semiconductor disk device. The method of claim 10, The controller is in communication with an external host.

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