KR20100028970A - Demultiplexer of semiconductor memory device - Google Patents

Abstract

PURPOSE: The demultiplexer of a semiconductor memory device is provided to reduce the swing voltage of a decoder to be lower than a supply voltage by adding a plurality of transistors on the pull-up part of the decoder. CONSTITUTION: An accumulator outputs parallel data by converting serial data. A comparator converts the parallel data into binary data. A decoder(100) includes a pull-down transistor(120) and a pull-up transistor(110). The decoder decodes the binary data to binary parallel data. A flip-flop synchronizes the binary parallel data by a clock signal and outputs the data.

Description

Demultiplexer of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a demultiplexer of a semiconductor memory device implementing a decoder by applying a low-swing technique.

As semiconductor memory devices are highly integrated and large in capacity, there is a demand for higher chip operating speeds. As a result, the amount of data to be processed increases and the data transfer speed increases.

Recently, as the use of portable devices increases, a technology that can process data at high speed but consumes little power is required.

Meanwhile, a 1: 8 demultiplexer is a circuit that converts binary data serially input into parallel binary data and outputs the data, and is an important component for processing data.

The 1: 8 demultiplexer has a decoder, and when the large amount of data is processed at high speed in the 1: 8 demultiplexer, the decoder frequently operates.

1 is a circuit diagram illustrating a general 1: 8 demultiplexer, and serial data input to the demultiplexer is output as eight parallel data. For this purpose, the demultiplexer has eight integrators, and the decoders included in all the integrators have a chain structure. That is, the output of the nth decoder is input to the n + 1th decoder, and the n + 1th decoder performs decoding using the reference voltage referring to the output of the nth decoder. Here, 1≤n≤7 is an integer, and the output of the eighth decoder is input to the first decoder.

FIG. 2 is a circuit diagram showing one integrator in a typical 1: 8 demultiplexer. The integrator includes an accumulator, a comparator, a decoder, and a flip flop. The accumulator outputs one bit in parallel when serial data is input. That is, one bit output from the accumulator is input to the comparator for outputting the high signal and the comparator for outputting the low signal, respectively.

The two comparators convert the input data into binary data and output the binary data.

The decoder is the nth decoder of the demultiplexer, which decodes the outputs of the two comparators as inputs and then decodes the correct parallel data using the reference voltage referenced to the outputs of the n-1th decoders.

The flip-flop is a D-flip-flop, and the flip-flop outputs the parallel data output from the nth decoder in synchronization with a clock signal.

3 is a circuit diagram illustrating one decoder in a general 1: 8 demultiplexer, and includes an OR gate, an AND gate, and an inverter having a general CMOS structure.

In the case of using the decoder having the conventional general CMOS structure as described above, the swing voltage of the decoder is equal to the supply voltage VDD. In other words, the decoder's supply voltage VDD becomes the swing voltage of the decoder. This is a major factor in power consumption.

The degree of power consumption is shown in Equation 1 below.

In Equation 1, C _L is a node capacitor of the decoder output terminal, VDD is a supply voltage of the decoder, and Vdd is a swing voltage of the decoder.

However, in recent years, since the amount of data transmission increases and the speed of transmission increases, the operation of the decoder will frequently occur in the demultiplexer according to the prior art, and thus the data transition will also occur frequently. Accordingly, there is a demand for a method for reducing power consumption of the decoder.

SUMMARY OF THE INVENTION An object of the present invention is to provide a demultiplexer for a semiconductor memory device in which a decoder applies a low-swing technique, and in particular, lowers a supply voltage and outputs the low-swing technology.

Another object of the present invention is to provide a demultiplexer of a semiconductor memory device that lowers the swing voltage of a decoder by adding a plurality of transistors to a pull-up part in a general CMOS structure.

The demultiplexer of the semiconductor memory device according to the present invention for achieving the above object is characterized by: an accumulator for converting serial data into parallel data and outputting; a comparator for converting the parallel data output from the accumulator into binary data; A decoder including a pull-down transistor and a pull-up transistor to decode the binary data converted by the comparator into binary parallel data, and a flip to output the binary parallel data output from the decoder in synchronization with a clock signal. A pull-down transistor of the decoder having a plurality of NMOS transistors connected to an input terminal, wherein the pull-up transistor includes a first PMOS transistor connected to a power supply terminal and a supply voltage through the power supply terminal; Multi-level NM that outputs the swing voltage down to the first output An OS transistor is provided.

Preferably, the first PMOS transistor and the multi-stage NMOS transistors are connected in parallel between the power supply terminal and the first output terminal, and a gate of the first PMOS transistor is connected to an output terminal of the pull-down transistor to connect the pull. It is turned on at the turn-on of the -down transistor.

Preferably, the multi-stage NMOS transistors are composed of first to second NMOS transistors, the source and the gate of the first NMOS transistor of the multi-stage NMOS transistors are connected to the power supply in parallel, the multi-stage NMOS The gate of the second NMOS transistor of the transistors is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor is connected to the drain of the first PMOS transistor, the drain of the second NMOS transistor is the first It is connected to the output terminal.

Preferably, the pull-down transistor of the decoder further comprises a plurality of NMOS transistors having an inverted input and an input of the plurality of NMOS transistors connected to an input terminal, wherein the pull-up transistor of the decoder is in parallel with the first PMOS transistor. A multi-stage outputting a swing voltage of the supply voltage is lowered to the second output stage when the second PMOS transistor connected to the power supply stage and the second PMOS transistor is turned on (Turn on) An NMOS transistor is further provided. Here, the multi-stage NMOS transistors for outputting a swing voltage having the supply voltage lowered to the second output terminal may include third to four NMOS transistors, and a source and a gate of the third NMOS transistor may be parallel to the power supply terminal. Is coupled to a drain of a third NMOS transistor, a source of the fourth NMOS transistor is connected to a drain of the second PMOS transistor, and a drain of the fourth NMOS transistor is connected to the drain of the fourth NMOS transistor. Is connected to the second output terminal. The gate of the third NMOS transistor is connected to the power supply terminal in common with the second NMOS transistor.

According to the present invention, the low-swing technique is applied to add a multi-stage transistor to the pull-up portion of the decoder, thereby lowering the decoder's swing voltage below the supply voltage. Accordingly, power consumption can be reduced compared to using a decoder having a general CMOS structure.

In addition, by applying the decoder used in the present invention to the 1: 8 demultiplexer, it is possible to reduce power consumption while maintaining high-speed data processing of the demultiplexer.

In particular, since the power consumption is reduced as described above, it is advantageous for portable equipments that require high data throughput and need to further reduce the power consumption of the battery.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described by at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.

Hereinafter, exemplary embodiments of a demultiplexer of a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

The present invention is configured by applying a low-swing technique to a decoder for reducing power consumption of a demultiplexer used in a semiconductor memory device. In particular, in the following description, for convenience of explanation, the 1: 8 demultiplexer is described as an example and is not limited to the 1: 8 demultiplexer of the present invention.

4 is a circuit diagram illustrating one decoder in a demultiplexer according to the present invention.

Referring to FIG. 4, the demultiplexer according to the present invention is a 1: 8 demultiplexer that converts serial data into parallel binary data and outputs the same.

The demultiplexer has eight integrators, all of which have an accumulator, a comparator, a decoder, and a flip-flop. In the present invention, since the operation of the accumulator, the comparator, and the flip flop is general, they are not shown in FIG. 4. However, their operation will be described with respect to the decoder 100.

The demultiplexer according to the present invention converts the input serial data into a plurality of parallel data and outputs the same. The 1: 8 demultiplexer converts the input serial data into eight parallel data and outputs it. However, in the present invention, the demultiplexer processes data at a lower voltage.

The accumulator converts serial data input to the demultiplexer into parallel data and outputs the parallel data. Specifically, the accumulator outputs one bit in parallel when serial data is input. For that purpose, the output of the accumulator is connected to two inputs of a comparator for outputting a high signal and a comparator for outputting a low signal.

The comparator converts the parallel data output from the accumulator to binary data and outputs the binary data. As described above, the comparator includes a comparator for outputting a high signal and a comparator for outputting a low signal.

The flip flop is a D flip-flop, which outputs the binary parallel data output from the decoder in synchronization with the clock signal CLK. That is, the flip-flop outputs the final binary parallel data at the rising edge of the clock signal CLK.

On the rising edge of the clock, it goes out as an output through the D flip-flop.

Decoders included in all integrators have a chain structure. That is, the output of the nth decoder is applied to the n + 1th decoder, and the n + 1th decoder performs decoding using the reference voltage referring to the output of the nth decoder. Here, 1≤n≤7 is an integer, and the output of the eighth decoder is applied to the first decoder.

The decoder 100 includes a pull-up transistor 110 and a pull-down transistor 120. The decoder 100 decodes the binary data converted in the comparator into binary parallel data. When the decoder 100 is an n (n = 3) -th decoder, the n-th decoder takes the output of the comparator as an input and the output of the n-1th decoder as an input. Here, the nth decoder uses a reference voltage referring to the output of the n-1th decoder in decoding.

,

)을 갖는 다수 NMOS 트랜지스터들(N8,N9,N10)을 더 구비한다. 따라서, 다수 NMOS 트랜지스터들(N5,N6,N7)와 다수 NMOS 트랜지스터들(N8,N9,N10)은 교번하여 동작한다.The pull-down transistor 120 of the decoder 100 includes a plurality of NMOS transistors N5, N6, and N7 connected to an input terminal, and inputs H, N, and N7 of the transistors N5, N6, and N7. L) and inverted input (

,

And a plurality of NMOS transistors N8, N9, and N10. Therefore, the plurality of NMOS transistors N5, N6, N7 and the plurality of NMOS transistors N8, N9, N10 operate alternately.

,

)을 위해 본 발명에서는 풀-다운 트랜지스터(120)의 입력단에 인버터를 더 구비할 수 있다. 다수 NMOS 트랜지스터들(N5,N6,N7) 중 N6는 접지(GND)되며, 다수 트랜지스터들(N5,N6,N7) 중 N9과 N10은 병렬로 접지(GND)된다.Inverted input (

,

In the present invention, an inverter may be further provided at an input terminal of the pull-down transistor 120. N6 of the plurality of NMOS transistors N5, N6 and N7 is grounded GND, and N9 and N10 of the plurality of transistors N5, N6 and N7 are grounded GND in parallel.

)가 인가된다. 그에 따라, 풀-다운 트랜지스터(120)는 두 개의 출력을 갖는데, 그 두 개의 출력은 크로스커플 연결 구조로 풀-업 트랜지스터(110)에 인가된다.The output of the comparator is applied to the gates of N5 and N6 among the NMOS transistors N5, N6, and N7, and the output P of the previous decoder is applied to the gate of N7. In addition, an inverted input is applied to the gates of N8 and N9 among the plurality of NMOS transistors N8, N9, and N10, and an inverted signal of the output P of the previous decoder is applied to the gate of N10.

) Is applied. Accordingly, pull-down transistor 120 has two outputs, which are applied to pull-up transistor 110 in a cross-coupled connection structure.

The pull-up transistor 110 of the decoder 100 includes a first PMOS transistor P1 operating in a cross-coupled connection with a plurality of NMOS transistors N5, N6, and N7 and multiple NMOS transistors N1 and N2. In addition, a second PMOS transistor (P2) and a multi-stage NMOS transistor (N3, N4) and cross-coupled to the plurality of NMOS transistors (N8, N9, N10) is provided. As the plurality of NMOS transistors N5, N6, and N7 and the plurality of NMOS transistors N8, N9, and N10 operate alternately, the first PMOS transistor P1 and the second PMOS transistor P2 are alternately turned on. (turn on)

)을 갖는다. 그에 따라, 디코더(100)는 제1 및 2 출력단(OUT,

)을 통해 페어(Pair)로 이진 병렬 데이터를 출력한다. 한편, 플립플롭에서는 디코더(100) 제1 출력단(

)의 출력이 유효한 경우 제2 출력단(OUT)의 출력을 무시하며, 그 반대의 경우는 제1 출력단(

)의 출력을 무시하여 처리한다.Decoder 100 of the present invention is the first and second output terminal (OUT,

Has Accordingly, the decoder 100 may output the first and second output terminals OUT,

Outputs parallel parallel data in pairs. Meanwhile, in the flip-flop, the first output terminal of the decoder 100 (

) Output is valid, the output of the second output terminal (OUT) is ignored, and vice versa

Ignore the output of) and process it.

)으로 출력한다. The source of the first PMOS transistor P1 is connected to the power supply terminal VDD, and the multi-stage NMOS transistors N1 and N2 receive a swing voltage that lowers the supply voltage through the power supply terminal VDD. First output stage (

)

) 사이에 병렬 연결되며, 제2 PMOS 트랜지스터(P2)와 다단의 NMOS 트랜지스터들(N8,N9,N10)은 전원 공급단(VDD) 및 제2 출력단(OUT) 사이에 병렬 연결된다. 그에 따라, 제1 PMOS 트랜지스터(P1)의 게이트가 풀-다운 트 랜지스터(120)의 출력단에 연결되어 풀-다운 트랜지스터(120)의 다수 NMOS 트랜지스터들(N5,N6,N7)이 턴온(Turn on)될 시에 턴온되며, 제2 PMOS 트랜지스터(P2)의 게이트가 풀-다운 트랜지스터(120)의 출력단에 연결되어 풀-다운 트랜지스터(120)의 다수 NMOS 트랜지스터들(N8,N9,N10)이 턴온(Turn on)될 시에 턴온된다.In addition, a source of the second PMOS transistor P2 is connected to the power supply terminal VDD, and the multi-stage NMOS transistors N3 and N4 have a swing voltage obtained by lowering a supply voltage through the power supply terminal VDD. ) Is output to the second output terminal OUT. Here, the second PMOS transistor P2 is connected to the power supply terminal VDD in parallel with the first PMOS transistor P1. In addition, the first PMOS transistor P1 and the multi-stage NMOS transistors N5, N6, and N7 have a power supply terminal VDD and a first output terminal (

) Are connected in parallel, and the second PMOS transistor P2 and the multi-stage NMOS transistors N8, N9, and N10 are connected in parallel between the power supply terminal VDD and the second output terminal OUT. Accordingly, the gate of the first PMOS transistor P1 is connected to the output terminal of the pull-down transistor 120 such that the plurality of NMOS transistors N5, N6, and N7 of the pull-down transistor 120 are turned on. When turned on, the gate of the second PMOS transistor P2 is connected to the output terminal of the pull-down transistor 120 so that the plurality of NMOS transistors N8, N9, and N10 of the pull-down transistor 120 are connected. It is turned on when turned on.

As described above, in the present invention, between the first and second PMOS transistors P1 and P2 connected to the power supply terminal VDD and the grounded plurality of transistors N5, N6, N7, or the plurality of transistors N8, N9, N10. Equipped with multiple stages of NMOS transistors N1 and N2 or multiple stages of NMOS transistors N3 and N4.

)에 연결된다.FIG. 4 shows an example in which the NMOS transistors N1 and N2 of the multi-stage are composed of the first to second NMOS transistors N1 and N2, and a source and a gate of the first NMOS transistor N1 are supplied in parallel. Is connected to the stage VDD, the gate of the second NMOS transistor N2 is connected to the drain of the first NMOS transistor N1, and the source of the second NMOS transistor N2 is the drain of the first PMOS transistor P1. The drain of the second NMOS transistor N2 is connected to the first output terminal (

)

In addition, FIG. 4 shows an example in which the other multi-stage NMOS transistors N3 and N4 are configured with the third to fourth NMOS transistors N3 and N4. The source and gate of the third NMOS transistor N3 are shown in FIG. It is connected to the power supply terminal (VDD) in parallel, the gate of the fourth NMOS transistor (N4) is connected to the drain of the third NMOS transistor (N3), the source of the fourth NMOS transistor (N4) is the second PMOS transistor ( It is connected to the drain of P2, the drain of the fourth NMOS transistor (N4) is connected to the second output terminal (OUT).

The gate of the third NMOS transistor N3 and the second NMOS transistor N2 are commonly connected to a power supply terminal VDD.

According to the above configuration, when the first PMOS transistor P1 is turned on by the output of the plurality of cross-coupled NMOS transistors N5, N6, N7, the first PMOS transistor P1 is connected to the first PMOS transistor P1. The connected multi-stage NMOS transistors N1 and N2 operate on a reference voltage and also deliver a reduced swing voltage vvd to the output stage. Here, the reference voltage may be determined by referring to the output of the n−1th decoder, which is the previous decoder.

In addition, when the second PMOS transistor P2 is turned on by the output of the cross-coupled NMOS transistors N8, N9, N10, the multi-stage NMOS connected to the second PMOS transistor P2. The transistors N3 and N4 operate by the reference voltage and also transfer the swing voltage vvd reduced in the supply voltage through the power supply terminal VDD to the output terminal. Here, the reference voltage may be determined by referring to the output of the n−1th decoder, which is the previous decoder.

The reference voltage mentioned above is the number n of the multi-stage NMOS transistors N5, N6, N7 or the multi-stage NMOS transistors N8, N9, N10 and the threshold voltages of the respective NMOS transistors N5-N10. V _THn ) is determined as in Equation 2 below.

In the above, VDD is a supply voltage through the power supply terminal, n is the number of NMOS transistors N5, N6, N7 or NMOS transistors N8, N9, N10 in multiple stages, and V _THn is each NMOS transistor. Threshold voltages of the fields N5 to N10. In the case of the decoder illustrated in FIG. 4, since NMOS transistors are configured in two stages, n = 2.

In the present invention, the total power consumption due to the reduced swing voltage of the decoder configured as described above is represented by Equation 3 or 4.

According to the present invention, the swing voltage output from the decoder 100 is reduced by the threshold voltage V _THn of the NMOS transistor at the supply voltage VDD, and the reduction width thereof varies depending on the number of NMOS transistors forming the stage.

While the preferred embodiments of the present invention have been described so far, those skilled in the art may implement the present invention in a modified form without departing from the essential characteristics of the present invention.

Therefore, the embodiments of the present invention described herein should be considered in a descriptive sense, not in a limiting sense, and the scope of the present invention is shown in the appended claims rather than the foregoing description, and all differences within the scope are equivalent to the present invention. Should be interpreted as being included in.

1 is a circuit diagram illustrating a typical 1: 8 demultiplexer.

2 is a circuit diagram showing one integrator in a typical 1: 8 demultiplexer.

3 is a circuit diagram illustrating one decoder in a typical 1: 8 demultiplexer.

4 is a circuit diagram illustrating one decoder in a demultiplexer according to the present invention.

Claims (6)

An accumulator for converting serial data into parallel data and outputting the parallel data; A comparator for converting the parallel data output from the accumulator into binary data; A decoder including a pull-down transistor and a pull-up transistor to decode the binary data converted in the comparator into binary parallel data; And And a flip-flop outputting the binary parallel data output from the decoder in synchronization with a clock signal. The pull-down transistor of the decoder includes a plurality of NMOS transistors connected to an input terminal, and the pull-up transistor includes a first PMOS transistor connected to a power supply terminal and a swing voltage that lowers a supply voltage through the power supply terminal. and a multiple stage NMOS transistor for outputting a swing voltage to a first output stage. The transistor of claim 1, wherein the first PMOS transistor and the multi-stage NMOS transistors are connected in parallel between the power supply terminal and the first output terminal, and a gate of the first PMOS transistor is connected to an output terminal of the pull-down transistor. And turned on at turn-on of the pull-down transistor. The multi-stage NMOS transistors of claim 1, wherein the multi-stage NMOS transistors include first to second NMOS transistors, and a source and a gate of a first NMOS transistor of the multi-stage NMOS transistors are connected to the power supply terminal in parallel. The gate of the second NMOS transistor of the multi-stage NMOS transistors is connected to the drain of the first NMOS transistor, the source of the second NMOS transistor is connected to the drain of the first PMOS transistor, and the drain of the second NMOS transistor is And a demultiplexer of the semiconductor memory device. 2. The decoder of claim 1, wherein the pull-down transistor of the decoder further comprises a plurality of NMOS transistors having an inverted input and an input of the plurality of NMOS transistors connected to an input terminal, wherein the pull-up transistor of the decoder is the first PMOS transistor. In parallel with the second PMOS transistor connected to the power supply stage and the swing voltage (swing voltage) is lowered to the second output stage when the supply voltage through the power supply stage when the turn on (Turn on) of the second PMOS transistor A demultiplexer for semiconductor memory devices, characterized by further comprising an output multistage NMOS transistor. 5. The multi-stage NMOS transistors of claim 4, wherein the multi-stage NMOS transistors outputting a swing voltage of the supply voltage to the second output terminal are configured with third to four NMOS transistors. The fourth NMOS transistor is connected to the drain of the third NMOS transistor, the source of the fourth NMOS transistor is connected to the drain of the second PMOS transistor, and the fourth NMOS transistor is connected to the power supply terminal. The drain of the demultiplexer of the semiconductor memory device, characterized in that connected to the second output terminal. 6. The demultiplexer of claim 5, wherein a gate of the third NMOS transistor is connected to the power supply terminal in common with the second NMOS transistor.

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