KR20100026307A - Photomask and method for expousing wafer using the same - Google Patents

Photomask and method for expousing wafer using the same Download PDF

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Publication number
KR20100026307A
KR20100026307A KR1020080085270A KR20080085270A KR20100026307A KR 20100026307 A KR20100026307 A KR 20100026307A KR 1020080085270 A KR1020080085270 A KR 1020080085270A KR 20080085270 A KR20080085270 A KR 20080085270A KR 20100026307 A KR20100026307 A KR 20100026307A
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KR
South Korea
Prior art keywords
pattern
peripheral circuit
circuit pattern
cell
disposed
Prior art date
Application number
KR1020080085270A
Other languages
Korean (ko)
Inventor
이전규
전진혁
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020080085270A priority Critical patent/KR20100026307A/en
Publication of KR20100026307A publication Critical patent/KR20100026307A/en

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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70058—Mask illumination systems
    • G03F7/70091—Illumination settings, i.e. intensity distribution in the pupil plane or angular distribution in the field plane; On-axis or off-axis settings, e.g. annular, dipole or quadrupole settings; Partial coherence control, i.e. sigma or numerical aperture [NA]
    • G03F7/701—Off-axis setting using an aperture
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: A photo-mask and a method for exposing a wafer using the same are provided to prevent a side lobe by forming an auxiliary space pattern to induce destructive interference with a photometry which flows through the side of a peripheral circuit pattern. CONSTITUTION: A cell pattern is arranged on a substrate. A first peripheral circuit pattern(200) is expanded in the expanded direction of the cell pattern. A second peripheral circuit pattern(210) is expanded in the perpendicular direction of the first peripheral circuit pattern. An auxiliary pattern(220) is inserted into the center of the expended direction of the second peripheral circuit pattern. The auxiliary pattern prevents a side lobe by inducing destructive interference with a photometry which flows through the side of the second peripheral circuit pattern.

Description

Photomask and Method for Exposing Wafer Using the Same

The present invention relates to a photomask and a wafer exposure method, and more particularly, to a photomask applicable to an asymmetric lighting system and a wafer exposure method using the same.

As semiconductor memory devices are highly integrated, the unit area is reduced, and the pitch size between patterns is gradually decreasing. Accordingly, in order to improve the high resolution and the depth of focus in the photolithography process, an Off Asix Iillumination system that deforms the aperture is used. Such incident lighting systems include annular, quadruple, dipole, and cross pole apertures.

In particular, the dipole illumination system, as shown in FIG. 1, has a circular light blocking region 110 and a pair of openings that are light transmitting regions, that is, dipoles 120. At this time, the dipoles 120 are disposed to face each other in the horizontal X direction or the vertical Y direction. The dipole illumination system has a directionality according to the direction in which the dipole 120 is disposed. Therefore, when the exposure process is performed using an illumination system in which the dipole 120 is disposed in the X direction of FIG. 1, the pattern formed on the wafer increases in the resolution of the Y direction pattern perpendicular to the dipole 120. The resolution of the X-direction pattern parallel to the dipole 120 is rather degraded.

For example, referring to a layout of a photomask for forming a DRAM or a flash device, as shown in FIG. 2, the cell pattern 130 formed in the cell region may have a constant direction, for example, a Y direction. As shown in FIG. 3, the peripheral circuit pattern formed in the peripheral circuit region is formed in the vertical direction 140 formed in the same Y direction as the cell and in the X direction orthogonal to the cell. The horizontal patterns 141 are arranged in isolation in various orientations.

Specifically, looking at the patterns of the peripheral circuit area subjected to the exposure process through the dipole illumination system of FIG. 1, in the case of the vertical pattern 140, the intensity of light irradiated to the vertical pattern 140 and transmitted to the wafer is measured. As a result, as shown in FIG. 4, the intensity of light at the center portion a and the edge portion b of the vertical pattern 140 is recognized as 0.00, indicating that the light is degraded to the same depth. can see. On the other hand, in the case of the horizontal pattern 141, as a result of measuring the intensity of the light irradiated to the horizontal pattern 141 and delivered to the wafer, the horizontal pattern 141 is diffracted in the horizontal pattern 141 side to the light blocking region in which the horizontal pattern 141 is formed. As shown in FIG. 5 by the flowing metering, the degradation of the light perceived at the center portion a and the edge portion b of the horizontal pattern 141 is compared with the vertical pattern (140 in FIG. 4). You can see the difference. That is, the intensity of light at the edge portion b of the horizontal pattern 141 is recognized as 0.00, but the intensity of light at the central portion a of the horizontal pattern 141 is recognized as 1.00, thereby causing a difference in light degradation.

As such, when the exposure process is performed using a dipole illumination system, light that is relatively larger at the center portion a than the edge portion b in a specific pattern, that is, in a pattern parallel to the dipole, is transferred to the wafer, thereby Generate a sidelobe in the center. These side lobes are more severe as the defocus increases during wafer exposure.

A photomask according to the present invention includes a cell pattern disposed on a substrate; A first peripheral circuit pattern disposed to extend in the extending direction of the cell pattern; And a second peripheral circuit pattern disposed to extend in a direction orthogonal to the first peripheral circuit pattern. And a secondary space pattern inserted into a central portion of the direction in which the second peripheral circuit pattern extends to induce photometry and extinction interference flowing into the side surface of the second peripheral circuit pattern to prevent side lobes.

The cell pattern may be formed of a dense pattern of lines and spaces, and the first and second peripheral circuit patterns may be formed of an isolated pattern having a line width relatively larger than the cell patterns.

The auxiliary space pattern may be disposed to extend in a line shape in a direction in which the second peripheral circuit pattern extends.

The auxiliary space pattern may be disposed in a dot shape spaced apart from each other in a direction in which the second peripheral circuit pattern extends.

 A wafer exposure method using a photomask according to the present invention includes a cell pattern arranged to extend in one direction on a substrate, a first peripheral circuit pattern, and an extension arranged in a direction orthogonal to the cell pattern and the peripheral circuit pattern. Preparing a photomask including a peripheral circuit pattern, the photomask having a secondary space pattern is inserted into the center portion of the direction in which the second peripheral circuit pattern extends to induce photometry and extinction interference flowing into the side surface of the second peripheral circuit pattern. step; And transferring the cell pattern, the first peripheral circuit pattern, and the second peripheral circuit pattern onto a wafer using a dipole illumination system in which poles are disposed in a direction parallel to the cell pattern.

The photomask according to the embodiment of the present invention has a specific size (size) in which the intensity of light is relatively larger than the pattern edge portion at the center of the pattern orthogonal to the cell pattern, that is, the direction parallel to the direction of the illumination system, in an exposure process using an asymmetric illumination system. ) May be introduced in the process for reducing the intensity of light. A photomask according to an embodiment of the present invention is a binary mask in which a light blocking film pattern is formed on a transparent substrate, or a phase shift mask in which a light blocking film pattern and a phase inversion pattern are formed on a transparent substrate. It can be made of).

On the other hand, the photomask according to an embodiment of the present invention includes a cell region and a peripheral circuit region, the drawings presented in the present invention, for convenience of description, only a portion of the peripheral circuit region is presented.

6 is a diagram illustrating a layout of a peripheral circuit pattern in which an auxiliary space pattern is inserted into a photomask according to the present invention.

Referring to FIG. 6, a photomask according to an embodiment of the present invention may include a first peripheral circuit pattern 200 on a substrate to form a memory device such as a DRAM or a flash device. And an auxiliary space pattern in which the second peripheral circuit patterns 210 are disposed and inserted into the center of the second peripheral circuit pattern. At this time, the cell pattern is disposed on the substrate. The cell pattern, the first peripheral circuit pattern 200, and the second peripheral circuit pattern 210 may be formed of a light shielding pattern such as chromium (Cr), but is not limited thereto.

As shown in the layout of FIG. 2, the cell pattern may be formed of a dense pattern extending in one direction, for example, in the Y-axis direction. The first peripheral circuit pattern 200 is disposed in the direction in which the cell pattern extends, that is, the Y axis direction, and the second peripheral circuit pattern 210 is in a direction perpendicular to the direction in which the cell pattern extends, that is, the X axis direction. It may be made of an isolated pattern extending to. In this case, the first peripheral circuit patterns 200 and the second peripheral circuit patterns 210 may be disposed to have a relatively larger line width than the cell patterns.

The auxiliary space pattern 220 is inserted in the center of the second peripheral circuit pattern 210 so that the line shape extends in the direction in which the second peripheral circuit pattern 210 extends, that is, in the X-axis direction. Can be. The auxiliary space pattern 220 may be inserted into a dot shape spaced apart from each other in a direction in which the second peripheral circuit pattern 210 extends, or the second peripheral circuit pattern 210 may be separated from the second peripheral circuit pattern 210. 210 may be inserted to both ends of the extending direction.

The auxiliary space pattern 220 is a light transmission region through which the substrate portion is exposed, and serves to induce extinction interference in an exposure process using an asymmetric illumination system. Specifically, the light passing through the region of the auxiliary space pattern 220 may exhibit extinction interference with light that is relatively high at the center portion (a) of FIG. 5, in which light diffracted from the side of the second peripheral circuit pattern flows. Induction is suppressed to reduce the difference in the light of the central portion (a) and the edge portion (b) of the second peripheral circuit pattern (210). As a result, it is possible to prevent sidelobe generated at the center of the wafer pattern formed in the direction parallel to the dipole on the wafer. Therefore, both the vertical pattern in the direction perpendicular to the dipole and the horizontal pattern in the direction parallel to the pole can increase the resolution.

In the wafer exposure method using the photomask according to the embodiment of the present invention, as shown in FIG. 6, the cell pattern, the first peripheral circuit pattern 200, the cell pattern, and the first pattern are disposed to extend in one direction on the substrate. And a second peripheral circuit pattern 210 disposed to extend in a direction orthogonal to the peripheral circuit pattern 200, and inserted into a central portion of the direction in which the second peripheral circuit pattern 210 extends. A photomask including an auxiliary space pattern 220 for inducing photometry and extinction interference flowing into the side surface is prepared.

Next, an exposure process using an asymmetric illumination system is performed to transfer the cell patterns, the first peripheral circuit patterns 200, and the second peripheral circuit patterns 210 of the photomask onto the wafer. Here, the dipole illumination system uses an illumination system in which poles are arranged in parallel with the direction in which the cell pattern extends. For example, when the cell pattern is disposed in the Y axis direction, the dipole 120 of FIG. 1 uses an illumination system disposed in the X axis direction, and when the cell pattern is disposed in the X axis direction, the pole is in the Y axis direction. It is possible to use a dipole illumination system arranged.

In this case, the cell patterns, the first peripheral circuit pattern 200, and the second peripheral circuit pattern 210 become light shielding areas from which light is blocked, and the second peripheral circuit pattern 210 and the first peripheral circuit pattern 200 are separated from each other. The transparent substrate portion exposed by the light source becomes a light transmitting area, and the auxiliary space pattern 220 area also becomes a light transmitting area. Therefore, when the exposure process is performed, light is transmitted to the auxiliary space pattern 220, and the transmitted light induces an extinction interference with photometry flowing into the side surface of the second peripheral circuit pattern 210.

Specifically, as a result of measuring the intensity of light transmitted to the wafer through the second peripheral circuit pattern 210 having the auxiliary space pattern inserted therein by performing the exposure process using the dipole illumination system of FIG. 1, as shown in FIG. 7, The intensity of the light is recognized as 0.00 at the center portion a of the second peripheral circuit pattern 210, that is, the auxiliary space pattern region, and the edge portion b of the second peripheral circuit pattern 210, and thus the light has the same depth. This deterioration can be seen. That is, the light passing through the auxiliary space pattern region induces photometric and extinction interference induced in the center of the pattern of FIG. 4, whereby the center a and the edge of the second peripheral circuit pattern 210 in a direction parallel to the dipole are formed. The difference in light fall of (b) can be suppressed. Accordingly, the resolution of the second peripheral circuit pattern in the direction parallel to the pole as well as the cell pattern and the first peripheral circuit pattern in the direction perpendicular to the dipole can be improved to prevent side lobes generated in the center of the wafer pattern.

Further, when defocuss occur during the exposure process, as shown in FIG. 8, even if the deviation distance from the focus position of the exposure light source position, that is, the defocus value increases from 0.00 to 0.30, the pattern It can be seen that there is no difference in the degradation of light in the central portion and the pattern edge portion. As described above, according to the present invention, by inserting an auxiliary space pattern which prevents side lobes by causing extinction interference in the middle of the horizontal pattern in the direction parallel to the pole, that is, the second peripheral circuit pattern, The difference in degradation of light can be suppressed. Accordingly, the yield of the semiconductor device can be improved by improving the resolution of the pattern formed on the wafer.

As mentioned above, although the preferred embodiment of the present invention has been described in detail, the present invention is not limited to the above embodiment, and various modifications may be made by those skilled in the art within the preferred technical spirit of the present invention. Of course.

1 is a view showing a dipole illumination system.

2 and 3 illustrate a pattern layout in a photomask.

4 and 5 are diagrams showing the intensity of light incident on a wafer by light irradiated in a vertical pattern and a horizontal pattern in the photomask.

6 is a diagram illustrating a layout of a peripheral circuit pattern in which an auxiliary space pattern is inserted into a photomask according to the present invention.

7 and 8 illustrate the intensity of light incident on a wafer by light irradiated in a horizontal pattern in a photomask according to the present invention.

Claims (5)

A cell pattern disposed on the substrate; A first peripheral circuit pattern disposed to extend in the extending direction of the cell pattern; And A second peripheral circuit pattern disposed to extend in a direction orthogonal to the first peripheral circuit pattern; And a secondary space pattern inserted into a central portion of the direction in which the second peripheral circuit pattern extends to induce photometry and extinction interference flowing into the side surface of the second peripheral circuit pattern to prevent side lobes. The method of claim 1, The cell pattern includes a dense pattern of lines and spaces, and the first peripheral circuit pattern and the second peripheral circuit pattern comprise an isolated pattern having a line width relatively larger than the cell patterns. The method of claim 1, The auxiliary space pattern may be disposed to extend in a line shape in a direction in which the second peripheral circuit pattern extends. The method of claim 1, The auxiliary space pattern may be disposed in a dot shape spaced apart at regular intervals in a direction in which the second peripheral circuit pattern extends.  A second peripheral circuit pattern disposed on the substrate and extending in one direction; a first peripheral circuit pattern; and a second peripheral circuit pattern extending in a direction orthogonal to the cell pattern and the peripheral circuit pattern. Preparing a photomask having an auxiliary space pattern inserted into a central portion of the direction in which the pattern extends and inducing side-lighting and extinction interference flowing into the side surface of the second peripheral circuit pattern; And transferring the cell pattern, the first peripheral circuit pattern, and the second peripheral circuit pattern onto the wafer using a dipole illumination system in which poles are disposed in a direction parallel to the cell pattern.
KR1020080085270A 2008-08-29 2008-08-29 Photomask and method for expousing wafer using the same KR20100026307A (en)

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Application Number Priority Date Filing Date Title
KR1020080085270A KR20100026307A (en) 2008-08-29 2008-08-29 Photomask and method for expousing wafer using the same

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Application Number Priority Date Filing Date Title
KR1020080085270A KR20100026307A (en) 2008-08-29 2008-08-29 Photomask and method for expousing wafer using the same

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KR20100026307A true KR20100026307A (en) 2010-03-10

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