KR20100023123A - A 2phase pipelining buffer management of idwt for the reusage of convolved products - Google Patents

Abstract

PURPOSE: A two phase pipelining and buffer management method of IDWT for the reuse of convolution products is provided to improve processing performance by two phase pipeline operation and to reduce buffer storage space, computing time, and power consumption by storing only necessary multiplication results in a buffer among generated multiplication results and reusing duplicated multiplication results. CONSTITUTION: A two phase pipelining and buffer management method of IDWT for the reuse of convolution products includes the following method: a method of pipeline operation for the increase of processing amounts; a method of buffer management which reduces buffer size and power consumption by not storing and reusing unnecessary multiplication result; a method for storing generated multiplication results by re-arranging the results in a buffer in order that sequential search of multiplication results required in an addition operator is possible.

Description

A two-phase pipelining buffer management of IDWT for the reusage of convolved products}

The present invention relates to the structure of the VLSI of the backward discrete wavelet transformer, and stores only the multiplication result (Product) necessary for the convolution based backward discrete wavelet transform and reuses the redundant multiplication result (Product) in the buffer storage space and It is a method to increase the processing performance by reducing the computation time and power consumption, and increasing the utilization efficiency of the multi-line pipeline of multi-line, multiplication, storage, retrieval and addition.

Recently, multimedia field has been introduced to consumers in various forms such as VOD, HDTV, DVD, etc., and the amount of data required is far exceeding analog. Therefore, compression is very important in the processing of video signals to be used more efficiently in many areas such as data storage and transmission. Among them, the discrete wavelet transform has been recognized for its superiority in the field of image compression and is used in many fields such as JPEG2000 and MPEG-4. However, due to the complexity of the conversion method, discrete wavelet transform requires not only hardware implementation but also low hardware cost, power consumption, and fast processing speed for real-time processing of images in portable digital devices.

First, as shown in FIG. 1, the basic operation of the convolution-based 2D discrete wavelet transform is performed after the high-band and low-band filter operations in the horizontal direction with respect to the input data of the still image, followed by a downsampling process. If the same operation is repeated in the vertical direction again, one-level two-dimensional discrete wavelet transform is completed. If the above operation is repeated twice for L ₁ L ₁ , the two-dimensional discrete wavelet transform up to three levels is completed. And the basic operation of the convolution-based 2D inverse discrete wavelet transform is shown in FIG . The three-level subbands L ₃ L ₃ , L ₃ H ₃ , H ₃ L ₃ , and H ₃ H ₃ are input and subjected to up-sampling, followed by a low-band and high-band filter operation in the vertical direction. In addition, two subbands that have undergone low / high band filter operations are added to form a single subband, thereby completing vertical conversion. If the same operation is repeated in the horizontal direction again, the three-level two-dimensional inverse discrete wavelet transform is completed. L ₂ L ₂ , L ₂ H ₂ , H ₂ L ₂ , and H ₂ H ₂ generated here can be repeated twice to obtain the final reconstructed image.

Looking at the existing structure of the discrete wavelet converter, it is divided into a convolution based structure and a lifting based structure. Lifting-based structures can reduce the amount of multiplication compared to convolution-based structures, while the hardware structure is complex. In addition, the lifting-based structure has a long critical path, which results in a long initial delay and a slow calculation speed. Convolution-based structures have more multiplication operations than lifting-based structures, but their computation time is faster due to the shorter delay time. The convolution-based cascaded structure speeds up computation by processing multiple levels or line units simultaneously. However, each processing unit must have a multiply-add operator equal to the filter coefficient length, thereby increasing hardware complexity. Convolution-based non-cascaded structures operate at the level or line level as a single processing unit. Although the calculation speed is slower than the convolution-based cascaded structures, the control and hardware structure is simple. Convolution-based non-cascaded structures are subdivided into systolic and parallel structures. The systolic structure is faster than the parallel structure, but the delay time is long and the pipeline operation is difficult. However, parallel architectures have slower computational speeds than systolic ones, but have lower latency, relatively simple hardware complexity, and easier pipeline operation.

First, among the convolution-based discrete wavelet converters, the non-cascaded parallel structure is suitable for high-speed computation because of its small size, simple structure, and efficient pipeline operation. First, as shown in FIG. 3 , the convolution filter operation is composed of a multiplication operation of input pixel data and a filter coefficient and addition operation thereof. The convolution filter operation generates a multiplication result by the filter coefficients per pixel data and a multiplication operation, and performs a filter operation by the addition operation of the generated multiplication results. Therefore, the convolution filter operation is suitable for the line-level two-stage pipeline operation between multiplication and addition.

Secondly, as described above, the convolution-based two-dimensional inverse discrete wavelet transformer operates as a line-by-line two-stage pipeline of multiplication, storage, retrieval, and addition. Therefore, we need a buffer to store the multiplication results. In the convolution operation, among the Daubechies (9/7) filters, the high-band filter performs 9 multiplications with the pixel data, and the low-band filter performs 7 multiplications with the pixel data. Therefore, when the line size is N, the required buffer size is 7 * N for the low pass filter operation and 9 * N for the high pass filter operation. Therefore, there is a problem that the size of the buffer becomes too large, so a method that can effectively reduce the size of the buffer is needed.

Third, as described above, in order to improve the processing performance of the discrete wavelet transform, it operates as a line-level two-stage pipeline of multiplication & storage and retrieval & addition. In the multiplication & storage step, the necessary multiplication products (Product) are generated by one parallel multiplication with the filter coefficient per pixel data. Therefore, the multiplication amount is reduced from 7/9 to 1 parallel multiplication in the low and high band filter operations. However, since the amount of addition remains unchanged, the speed of the addition operation greatly affects the performance of the entire pipeline. In order to increase the processing speed of the add operator, parallelization of the add operator is required. In addition, the parallelized adder must be able to retrieve multiplication results quickly.

In order to solve the above problems, the present invention improves processing performance by a line-by-line two-stage pipeline operation of multiplication, storage, retrieval, and addition in a convolution-based backward discrete wavelet converter, and multiplies through reuse of a product. The purpose of the present invention is to provide a buffer and buffer management technique for reducing the size, power consumption, and processing time of a buffer by avoiding duplication of operations.

In order to perform the above-described first problem, the multi-stage pipeline operation between the multiplication operation and the addition operation, a buffer for storing the multiplication result is required. In addition, two buffers are configured for interleaving operation. First, the pixel data in line unit is multiplied in parallel with the filter coefficients to generate the multiplication results and store them in the buffer. The multiplication results stored in the buffer are retrieved and the convolution operation is completed by the addition operation. At the same time, the new line-by-line pixel data is parallel-multiplied and interleaved in another buffer. Thus, multi-line pipeline operation of multiplication, storage, retrieval, and addition is possible, which improves computational processing power.

To solve the above-mentioned second problem, we need to look at the filter used in the operation. In the case of inverse discrete wavelet transform, among the Daubechies (9/7) filters, the low band filter is 7 taps and the high band filter is 9 tabs. And, as shown in Fig. 4, if the products are reused using the symmetry of the filter coefficients, the products to be stored in the buffer are 7 → 4 for the low pass filter operation and 9 for the high pass filter operation → Reduced to five. As shown in FIG. 5, the pixel data added by upsampling during low-band filter operation has a value of zero. Therefore, it is unnecessary for the addition operation. Therefore, only the multiplication result necessary for the operation is stored in the buffer. Therefore, the result of multiplying the odd-numbered pixel data p (2i + 1) and the filter coefficients is always 0 and thus is not stored in the buffer. Only the multiplication result of the even-numbered pixel data p (2i) and the filter coefficients is stored in the buffer. As shown in FIG. 6, pixel data added by upsampling during high-band filter operation has a value of zero. Therefore, it is unnecessary for the addition operation. Therefore, only the multiplication result necessary for the operation is stored in the buffer. Therefore, the result of the multiplication of the even-numbered pixel data p (2i + 1) and the filter coefficients is always 0, so it is not stored in the buffer. Only the multiplication result of the odd-numbered pixel data p (2i) and the filter coefficients is stored in the buffer. Therefore, the multiplication results to be stored are 4 * N (line size) → 4 * (N / 2) for low band filter operation, 5 * N (line size) → 5 * (N / 2) for high band filter operation Will be reduced by. That is, the product to be stored per pixel data is reduced to 7 * N → 2 * N in the low band filter operation, and 9 * N → 5 * (N / 2) in the high band filter operation. . Therefore, the redundant multiplication result (Product) is reused during the addition operation, thereby avoiding unnecessary multiplication operation (about 40%), thereby reducing processing time and power consumption.

As described above, in order to increase the efficiency of the line-level two-stage pipeline between the multiplication operation and the addition operation, the throughput of the multiplication operation and the addition operation should be similar. The multiplication operation processes the parallel multiplication of one pixel data and the filter coefficients in one cycle regardless of the filter, so it takes N cycles when the line size is N. In addition, the low-pass filter operation requires retrieving seven multiplication results (Product) from the buffer, and the high-band filter operation requires retrieving nine multiplication results (Product) from the buffer. Thus, because low-pass filter operation during addition operations is N / 2 (line size) x 7 (multiplication results) as in claim 7 also takes about 3.5N cycle. In the high-band filter operation, the addition operation takes about 4.5N cycles since N / 2 (line size) x 9 (multiplication result). Therefore, in order to balance the throughput of the addition operation with the multiplication operation, the parallelization of the addition operation is required. The addition operator needs to retrieve the product from each buffer at the same time, so buffer parallelism is required. Also, in order to speed up the buffer search of the addition operator, the multiplication results are sequentially sorted and stored in the buffer. As a result, the speeding up of the addition operator increases the efficiency of using the pipeline between the multiplication operation and the addition operation, thereby increasing the throughput of the entire operation.

According to the present invention, the performance of the multi-line multi-stage pipeline operation of multiplication, storage, retrieval and addition is improved. First, only the necessary multiplication results (Product) among the generated multiplication results (Product) are stored in the buffer, and the redundant multiplication results (Product) are reused to reduce the storage space, operation time and power consumption of the buffer. The multiplication result (Product) needed by the parallel addition operator is rearranged and stored for fast sequential retrieval. As a result, we increased the efficiency of the convolutional two-stage pipeline of multiplication, storage, retrieval, and addition.

As described above, the operation of the line-level two-stage pipeline between the multiplication operation and the addition operation is shown in FIG . 8 . First, multiply the pixel data of the first line to be processed with the filter coefficients to generate the multiplication results. The generated multiplication results are stored in the buffer A. The pixel data of the next line is multiplied with the filter coefficients and stored in the buffer B. At the same time, the addition operator retrieves the necessary multiplication results from the buffer A and adds them to process the convolution operation. In the processing of the next line, the multiplication results are stored in the buffer A again, and the search is performed in the buffer B. In this way, the two buffers operate in an interleaving manner, thereby improving operation processing performance by a line-by-line two-stage pipeline operation of multiplication, storage, retrieval, and addition.

As described above, in the Daubechies (9/7) filter operation, 9/7 multiplication results (Product) are generated for each pixel data. Using symmetry of filter coefficients, redundant multiplications can be reduced by storing and reusing multiplication results in a buffer. FIG. 9 compares the sizes of the buffers required for the low pass filter operation. When N is the size of a line, a 7 * N size buffer is required to store all the product of the pixel data and the seven filter coefficients. And for the interleaving operation of the two-stage pipeline, a buffer for storing the multiplication result and a buffer for retrieving the addition operation are needed. Therefore, as in ① of FIG. 9, the buffer size for the pipeline is 14 * N. And multiplication with the symmetry of the pixel data and the filter coefficient results are stored as shown in (a) in FIG. 9 ② juleoseo 7 → 4 pieces as in FIG. 5. At this time, if all the multiplication results of the N (line size) pixel data are stored, the buffer size of 8 * N can be reduced as shown in ② of FIG. Since the odd-numbered pixel data is always zero by upsampling, the multiplication result with the filter coefficient is zero. Therefore, only the multiplication result of the even-numbered pixel data and the filter coefficient is stored in the buffer, so that (b) in ( 9) of FIG. 9 is not stored. The multiplication results ⓐ, ⓑ, ⓒ, ⓓ to be stored in FIG . 5 are stored as shown in (c), (d), (e) and (f) in FIG. 9 , and are multiplied by N (line size) pixel data. If you save all the results, you can reduce it to 4 * N size buffer as ③ of Figure 9 . Therefore, using the symmetry of the filter coefficients and the characteristics of upsampling, a buffer size of about 72% can be reduced. FIG. 10 compares the size of a buffer for pipeline operation in high-band filter operation. When N is the size of a line, a 9 * N size buffer is required to store all the product of the pixel data and the nine filter coefficients. And for the interleaving operation of the two-stage pipeline, a buffer for storing the multiplication result and a buffer for retrieving the addition operation are needed. Therefore, as in ① of FIG. 10, the size of the buffer for the pipeline is 18 * N. And multiplying the result by the symmetry of the first pixel data and the filter coefficients are stored as shown in ② (a) in claim 10 is also juleoseo 9 → 5 pieces, as in the Figure 6. At this time, if all the multiplication results of the N (line size) pixel data are stored, the size of the buffer may be reduced to 10 * N size as shown in ② of FIG. Since the even-numbered pixel data is always zero by upsampling, the multiplication result with the filter coefficient is zero. Therefore, only the multiplication result of the odd-numbered pixel data and the filter coefficient is stored in the buffer, so that in (b) of FIG. 10 , (b) is not stored. The multiplication results ⓐ, ⓑ, ⓒ, ⓓ, ⓔ to be stored in FIG . 6 are stored as (c), (d), (e), (f) and (g) in FIG. 10 , and N (line size). Storing all the multiplication results of the pixel data can reduce the size of the buffer to a size of 5 * N as shown in ③ of FIG. 10, thereby reducing the buffer size of about 72%. As described above, the buffer size is reduced through symmetry and upsampling of the filter coefficients in the low / high band filter operation.

As described above, a table relating to the multiplication results to be stored in each buffer when the line size is N (= 240) during the low pass filter operation is shown in FIG . The structure for multi-line pipeline of multiplication, storage, retrieval, and addition is shown in FIG . In FIG . 11, since the pixel data is calculated by up-sampling among p (0) to p (239), odd pixel data has a value of '0', and thus the generated multiplication result is always '0' and thus no input is received. . Therefore, only even pixel data is sequentially input. The multiplication result between the pixel data and the filter coefficients is (c) in Fig. 9 → the multiplication result [1] in Fig. 9 (d) → the multiplication result [2] in Fig. 9 (e) in Fig. 9 multiplication results [3], 9 are created in view of the (f) → multiplication result [4]. Four input multiplication results [1], [2], [3], and [4] are rearranged in five buffers so that the addition operator for the final transform pixel data p '(i) can search the multiplication results in parallel. do. Of the Convolved products of the first input pixel data p (0) in the table, p (0) * c (0), which is a multiplication result [1], is stored in the buffer 1 because it is required for the filter operation of p '(0). P (0) * c (1), which is a multiplication result [2], is required for the filter operation of p '(1) and p' (239) and stored in buffer 2 and buffer 5. P (0) * c (2), which is a multiplication result [3], is stored in the buffer 3 because it is required for the filter operation of p '(2) and p' (238). P (0) * c (3), which is a multiplication result [4], is stored in the buffer 4 because it is required for the filter operation of p '(3) and p' (237). In the same way, the convolved product multiplication results [1], [2], [3], and [4] of p (2) to p (238) are rearranged to allow parallel retrieval in five buffers during the addition operation. As a result, the multiplication results stored in buffer 1, buffer 2, buffer 3, buffer 4, and buffer 5 are sequentially ordered for fast searching in the addition operation to obtain p '(i). The sorting for parallel storage and sequential search shows a storage rule (6) repeated every 6 pixels. Therefore, the multiplication results in the <Rearization of Multiplication Results> block of FIG. 12 are rearranged by controlling 4 DEMUXs and 5 MUXs using the iterative storage rule (⑥). In the table of FIG. 11 , boundary area processing such as p '(0), p' (1), p '(237), p' (238), and p '(239) is solved as follows. The first input of the multiplication result and <Parallel Buffer> blocks rearranged in claim 12 also ①, ②, ③, ④, ⑤, respectively buffer 1, buffer 2, a buffer 3, a buffer 4, and stored in the buffer 5, and to store the multiplication result Write addresses of ①, ②, ③, ④, and ⑤ are allocated as ⓐ, ⓑ, ⓒ, ⓓ, ⓔ in the table of FIG. 11 to process the boundary area. In the parallel buffer block of FIG. 12, the multiplication results for p '(i) are rapidly output to the <add operation> block through the sequential search of the read address. The <addition operation> block is a block for calculating p '(i), which is the final transformed pixel data by accumulating the multiplication results sequentially searched. The parallel buffer block consists of five input buffers to store the multiplication result and five search buffers to be used for the addition operation to perform the interleaving operation for the two-stage pipeline. The input buffer of multiplication & storage and the search buffer of search & addition are interleaved by the phase signal. As described above, the input multiplication results are rearranged and stored in parallel in five buffers A for parallel search of the addition operator, and the five buffers B are sequentially stored in order to enable fast sequential search of the parallel addition operator. As a result, by reducing the difference in computation speed between multiplication and addition, the efficiency of the convolution pipeline is increased and the computational performance of the discrete wavelet transformer is increased.

As described above, a table relating to the multiplication results to be stored in each buffer when the line size is N (= 240) during the high pass filter operation is shown in FIG . And the structure for multi-line pipeline of multiplication, storage, retrieval, and addition is shown in FIG . The pixel data in FIG. 13 does not receive input because the even multiplication result is always '0' because the even pixel data has '0' during upsampling from p (0) to p (239). . Therefore, only odd pixel data is sequentially input. Multiplying the result of the pixel data and the filter coefficients (c) of claim 10, also by the symmetry → multiplication results [1], (d) → multiplied result of the 10 ° [2], of the 10 degrees (e) → The multiplication result [3], (f) of FIG. 10 → multiplication result [4], (g) of FIG. 10 → multiplication result [5]. The five multiplication results [1], [2], [3], [4], and [5] are inputted so that the addition operator for the final converted pixel data p '(i) can search the multiplication results in parallel. It is reordered in the buffer. P (1) * c (0), which is a multiplication result [1] of the convolved products of the first input pixel data p (1) in the table, is stored in the buffer 2 because it is required for the filter operation of p '(1). P (1) * c (1), which is a multiplication result [2], is stored in buffer 1 and buffer 3 because it is required for the filter operation of p '(0) and p' (2). P (1) * c (2), which is a multiplication result [3], is stored in buffers 4 and 7 because it is required for the filter operation of p '(3) and p' (239). P (1) * c (3), which is a multiplication result [4], is stored in buffer 5 because it is required for the filter operation of p '(4) and p' (238). P (1) * c (4), which is a multiplication result [5], is stored in the buffer 6 because it is required for the filter operation of p '(5) and p' (237). In the same way, Convolved product multiplication results [1], [2], [3], [4], and [5] of p (3) to p (239) can be parallelized in seven buffers during the addition operation. Reordering is saved. As a result, the multiplication results stored in buffer 1, buffer 2, buffer 3, buffer 4, buffer 5, buffer 6, and buffer 7 are sequentially ordered for fast searching in the addition operation to obtain p '(i). In the parallel storage and the sequential search, the multiplication result [1] is repeatedly stored in the order of Buffer 2 → Buffer 4 → Buffer 6 → Buffer 7 as ⑧. The multiplication result [2] is repeatedly stored in the order of (buffer 1, buffer 3) → (buffer 3, buffer 5) → (buffer 1, buffer 5) as shown in (9). The multiplication result [3] is repeatedly stored in the order of (buffer 4, buffer 7) → (buffer 2, buffer 6) as shown in FIG. The multiplication result [4] is repeatedly stored in the order of buffer 5? Buffer 1? The multiplication result [5] shows the rule of repeated storage in the order of buffer 6 → buffer 7 → buffer 2 → buffer 4 as shown in FIG. Therefore, the multiplication results in the <Rearization of Multiplication Results> block of FIG. 14 are rearranged by controlling 5 DEMUXs and 7 MUXs using the iterative storage rule (⑧ ~ ⑫). And a boundary such as p '(0), p' (1), p '(2), p' (3), p '(237), p' (238) and p '(239) in the FIG. Area processing is solved as follows. First, the results of the rearranged multiplication of FIG. 14 and input of the <Parallel Buffer> blocks ①, ②, ③, ④, ⑤, ⑥, and ⑦ are respectively Buffer 1, Buffer 2, Buffer 3, Buffer 4, Buffer 5, Buffer 6 , stored in the buffer 7, and storing the multiplication result of ①, ②, ③, ④, ⑤, ⑥, write addresses (write address) of ⑦ is the 13 degree ⓐ of the table, ⓑ, ⓒ, ⓓ, ⓔ , ⓕ, ⓖ , and Allocate them together to process the boundary area. In the parallel buffer block of FIG. 14, the multiplication results for p '(i) are quickly output to the <add operation> block through the sequential search of the read address. The <addition operation> block is a block for calculating p '(i), which is the final transformed pixel data by accumulating the multiplication results sequentially searched. The parallel buffer block consists of seven input buffers to store multiplication results and seven search buffers to be used for the addition operation. The input buffer of multiplication & storage and the search buffer of search & addition are interleaved by the phase signal. As described above, the input multiplication results are rearranged and stored in seven buffers A for parallel search of the addition operator, and the seven buffers B are sequentially stored to enable fast sequential search of the parallel addition operator. As a result, by reducing the difference in computation speed between multiplication and addition, the efficiency of the convolution pipeline is increased and the computational performance of the discrete wavelet transformer is increased.

Buffer management method for reuse of convolution multiplication result (product), buffer management method of backward discrete wavelet transformer and filter coefficient symmetry and downsampling to reduce multiplication operation in convolutional backward discrete wavelet transformer In addition, the present invention can provide a two-dimensional backward discrete wavelet converter which increases the throughput by increasing the use efficiency of hardware while having a small buffer area and low power consumption.

In addition, the present invention is not limited to two dimensions, but may also be provided by a one-dimensional and three-dimensional inverse discrete wavelet converter, and in the case of using a filter other than the Daubechies (9/7) filter in the inverse discrete wavelet transformation, Various modifications and improvements can be made without departing from the scope thereof.

In addition, the present invention includes a digital camera, a camera phone, a DVR (Digital Video Recoding), a digital TV, a laser printer, a fax, a scanner, and a digital copy machine using JPEG2000 or MPEG-4 of the reverse discrete wavelet converter panel to which the present invention is applied. The reverse discrete wavelet transform technique used can be provided in all applications and systems.

1 is an operation block diagram up to three levels of two-dimensional discrete wavelet transform, where HPF means a high band filter, LPF a low band filter, and ↓ 2 means downsampling;

2 is an operation block diagram up to three levels of two-dimensional inverse discrete wavelet transform, where HPF means low band filter, LPF means high band filter, and ↑ 2 means upsampling;

3 is a process of performing low-band filter operation when the size of the line is 320, showing that the calculation is performed while the filter coefficient is shifted to the right;

4 shows the symmetry of the filter coefficients of the Daubechies (9/7) filter;

FIG. 5 shows the filter operation except for the product of the odd pixel data and the filter coefficient that are not necessary for the operation through upsampling, except for the overlapped product due to the filter coefficient symmetry of the low pass filter. A picture of only necessary multiplication results;

FIG. 6 shows the filter operation except for the product of the odd pixel data and the filter coefficient that are not necessary for the operation through upsampling, except for the overlapped product (Product) due to the filter coefficient symmetry of the high-band filter. A picture of only the required multiplication results;

7 is a comparison of the processing speeds of multiplication and addition operations accelerated according to a high band / low band filter;

8 illustrates the two-stage pipeline operation of multiplication, storage, retrieval, and addition using two interleaving line buffers;

FIG. 9 illustrates a case in which all of the product results of the pixel data and all the filter coefficients are stored in one buffer when the low-band filter operation is performed, and when the product results overlapping the symmetry of the filter coefficients are not stored. And the size of the buffer when the multiplication result (Product) which is not necessary for the operation due to the symmetry of the filter coefficient and the upsampling are not compared;

FIG. 10 illustrates a case in which all of the product results of the pixel data and all the filter coefficients are stored in one buffer when the high-band filter operation is performed, and when the product results overlapping the symmetry of the filter coefficients are not stored. And the size of the buffer when the multiplication result (Product) which is not necessary for the operation due to the symmetry of the filter coefficient and the upsampling are not compared;

11 is a table relating to the multiplication results to be stored in each buffer when the size of the line in the low pass filter operation is 240;

12 is an overall structure of parallel retrieval of the stored multiplication results in the parallel adder after rearranging four input multiplication results in five buffers during low-band filter operation;

13 is a table relating to the multiplication results to be stored in each buffer when the size of the line in the high band filter operation is 240;

14 shows the overall structure of parallel retrieval of stored multiplication results in a parallel adder after rearranging five input multiplication results in seven buffers in a high-band filter operation;

Claims (6)

A line-by-line two-stage pipeline operation method of multiplication, storage, retrieval, and addition to increase throughput in a convolution-based two-dimensional inverse discrete wavelet transformer. A method of buffer management that reduces the size and power consumption of a buffer by reusing the multiplication result of Daubechies (9/7) filter without symmetry and upsampling in convolution-based two-dimensional backward discrete wavelet converter without storing unnecessary multiplication results. The buffer management method of claim 2, wherein the multiplication result overlapped by the symmetry of the filter coefficients is reused in the search buffer during the addition operation to reduce the multiplication operation amount and power consumption. The interleaving operation buffer according to claim 1, wherein the multiplication result inputted is stored in the input buffer by a line-level two-stage pipeline of a convolution-based two-dimensional discrete wavelet converter, and the addition operator retrieves the multiplication result stored in the search buffer. A method of reordering and storing the generated products of the pixel data and the filter coefficients in a buffer so that the products required by the addition operator can be sequentially searched. The method of claim 5, wherein the multiplication result of the boundary portion in the line-by-line storage buffer is assigned an address when the multiplication result is stored.

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