KR20100022275A - On die termination device - Google Patents

On die termination device Download PDF

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Publication number
KR20100022275A
KR20100022275A KR1020080080877A KR20080080877A KR20100022275A KR 20100022275 A KR20100022275 A KR 20100022275A KR 1020080080877 A KR1020080080877 A KR 1020080080877A KR 20080080877 A KR20080080877 A KR 20080080877A KR 20100022275 A KR20100022275 A KR 20100022275A
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South Korea
Prior art keywords
resistance
resistor
termination
resistors
calibration code
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KR1020080080877A
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Korean (ko)
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윤승환
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주식회사 하이닉스반도체
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Priority to KR1020080080877A priority Critical patent/KR20100022275A/en
Publication of KR20100022275A publication Critical patent/KR20100022275A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance

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  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The present invention relates to an on-die termination device, by connecting a series of resistive layers having different specific resistances in series to form a termination resistor, even when a resistance value of each resistive layer is changed due to a process or the like. To prevent the phenomenon, a technique for stably adjusting the termination resistance is disclosed.

Description

On Die Termination Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an on die termination device, and more particularly to an on die termination device of a binary weighting method.

As the operation speed of a semiconductor device is increased, the swing width of an interface signal is gradually reduced to minimize delay time for signal transmission. However, when the swing width is reduced, the influence of external noise on the interface signal is increased, resulting in impedance mismatching at the interface stage. When mismatching of impedance occurs, high-speed data transfer is difficult, and output data output from the data output terminal of the semiconductor memory device may be distorted. In other words, if the impedance is not properly matched, the transmitted signal is reflected and a signal transmission error is likely to occur.

Accordingly, a technique of matching impedance by adjusting the number of transistors turned on among a plurality of transistors connected in parallel to adjust the resistance of the termination stage has been proposed. As described above, the technology is called on-chip termination or on-die termination (ODT), and has been applied to DDR2 or higher semiconductor memory devices that require faster operation speeds.

1 is a circuit diagram illustrating an on die termination (ODT) device according to the prior art.

The conventional ODT device includes a plurality of termination resistance adjusting units 10 to 13. Here, the number of the termination resistance adjusting units 10 to 13 is added or subtracted according to the number of bits of the calibration code. Hereinafter, the case where the number of bits of the calibration code is four will be described. Here, the calibration code is a binary code generated during the ZQ calibration process, and the termination resistance is controlled by using the calibration code.

Each of the termination resistance adjusting units 10 to 13 is connected in parallel between a supply voltage VDD supply terminal and a ground voltage VSS supply terminal. The termination resistance controller 10 includes a resistor R1 and an NMOS transistor N1. The resistor R1 and the NMOS transistor N1 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N1 receives a gate voltage Vg corresponding to bit <bit0> of the calibration code through the gate terminal. In addition, the termination resistance adjusting unit 11 includes a resistor R2 and an NMOS transistor N2. The resistor R2 and the NMOS transistor N2 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N2 receives a gate voltage Vg corresponding to bit <bit1> of the calibration code through the gate terminal.

The termination resistance adjuster 12 includes a resistor R3 and an NMOS transistor N3. The resistor R3 and the NMOS transistor N3 are connected in series between the supply voltage VDD supply terminal and the ground terminal VSS. The NMOS transistor N3 receives a gate voltage Vg corresponding to bit <bit2> of the calibration code through the gate terminal. The termination resistance adjusting unit 13 includes a resistor R4 and an NMOS transistor N4. The resistor R4 and the NMOS transistor N4 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N4 receives a gate voltage Vg corresponding to bit <bit3> of the calibration code through the gate terminal.

Here, the relative resistance ratios of the resistors R1 to R4 are determined by the setting method. A typical method is an equal weighting method in which the resistance of each bit <bit0> to <bit3> has the same value. The equal weighting method has the advantage that the resistance value fluctuations due to process variables are small because the resistors R1 to R4 are formed of the same resistive layer, but the number of resistance values generated when N resistors are connected in parallel is N. There is only a disadvantage.

To compensate for this drawback, the binary weighting method reduces the resistance of each bit <bit0> to <bit3> by 1/2. That is, if the resistance value of the resistor R1 is R, the resistor R2 has 1 / 2R, the resistor R3 has 1 / 4R, and the resistor R4 has a resistance value of 1 / 8R. This binary weighting method has the advantage of making 2 N -1 resistance values with N resistors, but it is difficult to construct with only one resistor because it has to generate resistances of various values.

That is, when different resistance values are formed by adjusting the area or length of the resistive layer having the same specific resistance, the resistance having the smallest resistance value becomes too small compared to the resistance having the largest resistance value, or conversely, In comparison, the resistance with the largest resistance value becomes too large. Therefore, it is efficient in terms of area and cost to form a resistor having a small resistance value with a resistive layer having a low specific resistance, and a resistor having a large resistivity with a large resistivity.

 FIG. 2 is a graph illustrating characteristics of a termination resistor formed by a calibration code in the on-die termination apparatus shown in FIG. 1, (a) illustrates an equal weighting scheme, and (b) shows a binary weighting scheme. It is shown.

Referring to FIG. 2, the NMOS transistors N1 to N4 are selectively turned on according to a calibration code, and the total sum parallel resistance value of the resistors R1 to R4 in which the current path is formed becomes the termination resistor. Using a 4-bit calibration code, 15 binary codes from '0001' to '1111' are used to sequentially short or open resistors R1 to R4. For example, when the calibration code is '0001', only the NMOS transistor N1 is turned on so that the termination resistor is R1. When the calibration code is '0011', the NMOS transistors N3 and N4 are turned on, and the termination resistance is R3 and R4. do.

Here, in the equal weighting method, since the resistors R1 to R4 are formed of the same resistive layer with the same resistivity ρ, the resistance value changes according to the change in the process and the like are the same, and as shown in (a), the calibration code is As it increases, the termination resistance decreases sequentially. However, in the binary weighting method, when the resistors R1 to R4 are formed of two or more resistive layers having different specific resistances, the resistance may vary due to the change of the process, such that the termination resistance may vary. For example, when the resistors R1 and R2 are composed of a first resistive layer having a first specific resistance, and the resistors R3 and R4 are composed of a second resistive layer having a second specific resistance, ideally, each resistance value of the first and second resistive layers If this is not changed, as with the equalization method, the termination resistance will decrease sequentially as the calibration code increases.

However, when the resistance value of the first resistance layer is reduced by 15% and the resistance value of the second resistance layer is increased by 15% due to a process or the like, for example, the termination resistance is changed to the second resistance layer (or the first resistance layer). A resistance reversal phenomenon occurs when a switch is made from a point connected only by the configured resistance to a point connected to a resistor composed of the first resistor layer (or the second resistor layer).

That is, as shown in (b), when the calibration code is changed from '0011' to '0100', the termination should be reduced due to the reduced resistance value of the first resistance layer and the increased resistance value of the second resistance layer. Resistance reversal may occur with increasing resistance. Here, it does not matter when the resistance values of the first and second resistance layers increase or decrease together, but when the change of the resistance layers is opposite, that is, the resistance value of the first resistance layer increases (or decreases) When the resistance value of the second resistance layer decreases (or increases), the above-mentioned resistance reversal phenomenon occurs.

The present invention has the following object.

First, by connecting the resistive layers having different resistivity in series to form the termination resistor, it is possible to stably terminate the termination resistor by preventing the resistance reversal of the termination resistor even when the resistance value of each resistive layer is changed due to the process and other variables. It can be adjusted for this purpose.

Second, it is possible to reduce the area and cost of the chip by using a resistive layer having a different resistivity.

Third, by applying the binary weighting method, 2 N -1 resistance values can be made of N resistors, and thus the termination resistance can be precisely adjusted.

The on die termination device according to the present invention comprises: a plurality of resistance means corresponding to each bit of a calibration code and having different specific resistances; And a plurality of switching means for selectively connecting the plurality of resistance means according to the calibration code, wherein at least one of the plurality of resistance means has a different specific resistance and includes a plurality of resistors connected in series. Characterized in that.

Here, the plurality of resistance means may include first resistance means having a first specific resistance; And second resistance means having a second specific resistance, wherein the plurality of resistors are included in the second resistance means at a position switched from the first resistance means to the second resistance means, and the plurality of resistors Is included in the first resistance means and the second resistance means, respectively.

The plurality of resistance means and the plurality of switching means are respectively connected in series between a power supply voltage supply terminal and a ground voltage application terminal in a one-to-one correspondence, and each resistance value of the plurality of resistance means is 1/2 N times (here, N is a natural number), each resistance value of the plurality of resistance means sequentially decreases from the least significant bit of the calibration code to the most significant bit direction, and the plurality of switching means are selectively selected by the calibration code. It is turned on to connect the plurality of resistance means in parallel.

The present invention provides the following effects.

First, by connecting the resistive layers having different resistivity in series to form the termination resistor, it is possible to stably terminate the termination resistor by preventing the resistance reversal of the termination resistor even when the resistance value of each resistive layer is changed due to the process and other variables. Provides an adjustable effect.

Second, it provides an effect that can reduce the area and cost of the chip by using a resistive layer having a different specific resistance.

Third, by applying the binary weighting method, 2 N -1 resistance values can be made of N resistors, thereby providing an effect of precisely adjusting the termination resistance.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram illustrating an on die termination (ODT) device according to an embodiment of the present invention.

The ODT device according to the present invention includes a plurality of termination resistance adjusting units 20 to 23. Here, the number of termination resistance adjusting units 20 to 23 is added or subtracted according to the number of bits of the calibration code. Hereinafter, the case where the number of bits of the calibration code is four will be described. In addition, the termination resistance adjusting unit 20 to 23 of the present invention is preferably implemented by a binary weighting method.

Each of the termination resistance adjusting units 20 to 23 is connected in parallel between a supply voltage VDD supply terminal and a ground voltage VSS supply terminal. The termination resistance controller 20 includes a resistor R11 and an NMOS transistor N11. The resistor R11 and the NMOS transistor N11 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N11 receives a gate voltage Vg corresponding to bit <bit0> of the calibration code through the gate terminal. The termination resistance adjusting unit 21 includes a resistor R12 and an NMOS transistor N12. The resistor R12 and the NMOS transistor N12 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N12 receives a gate voltage Vg corresponding to bit <bit1> of the calibration code through the gate terminal.

In addition, the termination resistance adjusting unit 22 includes a resistor R15 and an NMOS transistor N13. The resistor R15 and the NMOS transistor N13 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N13 receives a gate voltage Vg corresponding to bit <bit2> of the calibration code through the gate terminal. Here, the resistor R15 is preferably composed of a resistor R13 and a resistor R14. The resistor R13 and the resistor R14 are connected in series between the power supply voltage VDD applying stage and the NMOS transistor N13, and are preferably formed of a resistive layer having different specific resistances. A method of connecting the resistor R13 and the resistor R14 in series will be described in detail later with reference to FIGS. 4 and 5.

Herein, the resistor R15 comprises resistors R1 and R2 corresponding to bits <bit0> and <bit1> of the calibration code in the prior art (FIG. 1) as the first resistor layer, and correspond to bits <bit2> and <bit3>. Compared with the case where the resistors R3 and R4 are formed of the second resistor layer, the resistance is a bit corresponding to a bit in which a resistance reversal phenomenon may occur, that is, a resistor corresponding to <bit2>. Therefore, in the exemplary embodiment of the present invention, the case in which the resistor R15 is configured by the resistors R13 and R14 has been described as an example. However, the present invention is not limited thereto. The resistance corresponding to the bit can be configured as the resistor R15. That is, for example, when the resistors R11, R12, and R15 are composed of the first resistor layer and the resistor R16 is composed of the second resistor layer, the resistors R16 can be composed of the resistors R13, R14.

In addition, the termination resistance adjusting unit 23 includes a resistor R16 and an NMOS transistor N14. The resistor R16 and the NMOS transistor N14 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N14 receives a gate voltage Vg corresponding to bit <bit3> of the calibration code through the gate terminal.

Here, when the binary weighting method is applied, the resistance value of the resistor R11 is R, the resistor R12 is 1 / 2R, the resistor R15 is 1 / 4R, and the resistor R16 has a resistance value of 1 / 8R. At this time, since the resistor R15 is configured by series connection of the resistor R13 and the resistor R14, the resistor R13 and the resistor R14 preferably have a resistance value of 1 / 8R. Herein, the case of configuring the resistance values of the resistors R13 and R14 as 1 / 8R has been described as an example, but the present invention is not limited thereto, and the ratio of the resistance values is adjusted according to the characteristics of the resistors R13 and R14. Can be.

In addition, in the following description, the case where the resistors R11, R12, R14 are comprised by the 1st resistive layer which has a 1st specific resistance, and the resistors R13, R16 are comprised by the 2nd resistive layer which has a 2nd specific resistance is demonstrated, for example. Here, the first specific resistance is defined as having a value larger than the second specific resistance. At this time, each resistance value of the resistors R11, R12, R13, R14, and R16 may be set by adjusting the area or length of the first or second resistor layer.

4 and 5 are cross-sectional views illustrating a series connection method of the resistors R13 and R14 shown in FIG. 3.

As shown in FIG. 4, the resistor R15 directly connects the resistor R14 formed of the first resistive layer having the first specific resistance and the resistor R13 formed of the second resistive layer having the second specific resistance through the first contact plug 24. Can be formed. 5, the resistor R14 and the resistor R13 may be formed through the resistor R17 formed of the third resistor layer having the third specific resistance. At this time, the resistor R14 and the resistor R17 are connected through the second contact plug 25, and the resistor R15 and the resistor R17 are connected through the third contact plug 26.

FIG. 6 is a graph illustrating characteristics of a termination resistor formed by a calibration code in the on die termination apparatus shown in FIG. 3.

Referring to FIG. 6, when the resistance value of the first resistance layer is reduced by 15% and the resistance value of the second resistance layer is increased by 15% due to variables such as a process, the resistor R15 is formed of the resistor R14 and the first resistance layer. Since the resistors R13 formed of the two resistance layers are connected in series, the change in the resistance value of the resistor R13 and the resistor R14 cancels each other so that the total resistance of the resistor R15 is not changed. Therefore, unlike the conventional case, it can be seen that the reversal phenomenon of the termination resistor does not occur when the calibration code is changed from '0011' to '0100'.

7 is a circuit diagram illustrating an on-die termination (ODT) device according to another embodiment of the present invention.

The ODT apparatus of the present invention includes a plurality of termination resistance adjusting units 30 to 33. Here, each of the termination resistance adjusting units 30 to 33 is connected in parallel between the power supply voltage VDD supply terminal and the ground voltage VSS application terminal. The termination resistance adjuster 30 includes a resistor R23 and an NMOS transistor N21. The resistor R23 and the NMOS transistor N21 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N21 receives a gate voltage Vg corresponding to bit <bit0> of the calibration code through the gate terminal. Here, the resistor R23 is preferably constituted by the resistor R21 and the resistor R22. The resistor R21 and the resistor R22 are connected in series between the power supply voltage VDD applying stage and the NMOS transistor N21, and are preferably formed of a resistive layer having different specific resistances.

In addition, the termination resistance adjusting unit 31 includes a resistor R26 and an NMOS transistor N22. The resistor R26 and the NMOS transistor N22 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N22 receives a gate voltage Vg corresponding to the bit <bit1> of the calibration code through the gate terminal. Here, the resistor R26 is preferably composed of a resistor R24 and a resistor R25. The resistor R24 and the resistor R25 are connected in series between the power supply voltage VDD applying stage and the NMOS transistor N22, and are preferably formed of a resistive layer having different specific resistances.

In addition, the termination resistance controller 32 includes a resistor R29 and an NMOS transistor N23. The resistor R29 and the NMOS transistor N23 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N23 receives a gate voltage Vg corresponding to bit <bit2> of the calibration code through the gate terminal. Here, the resistor R29 is preferably composed of a resistor R27 and a resistor R28. The resistor R27 and the resistor R28 are preferably connected in series between the power supply voltage VDD applying stage and the NMOS transistor N23, and formed of a resistive layer having different specific resistances.

The termination resistance adjusting unit 33 includes a resistor R32 and an NMOS transistor N24. The resistor R32 and the NMOS transistor N24 are connected in series between the supply voltage VDD supply terminal and the ground voltage VSS supply terminal. The NMOS transistor N24 receives a gate voltage Vg corresponding to bit <bit3> of the calibration code through the gate terminal. Here, the resistor R32 is preferably composed of a resistor R30 and a resistor R31. In addition, the resistor R30 and the resistor R31 are preferably connected in series between the power supply voltage VDD applying stage and the NMOS transistor N24, and formed of a resistive layer having different specific resistances.

Here, when the binary weighting method is applied, the resistance value of the resistor R23 has R, the resistor R26 has 1 / 2R, the resistor R29 has 1 / 4R, and the resistor R32 has a resistance value of 1 / 8R. At this time, since the resistors R23, R26, R29, and R32 each consist of two resistors connected in series, the resistance of each resistor has half of the resistance of the corresponding resistors R23, R26, R29, and R32. The resistors R22, R25, R28, and R31 are preferably composed of a first resistive layer having a first specific resistance, and the resistors R21, R24, R27, and R30 are preferably composed of a second resistive layer having a second specific resistance.

That is, another embodiment of the present invention consists of two resistors R23, R26, R29, and R32 all connected in series so that all of the resistors R23, R26, R29, and R32 may be canceled even if the resistance values of the first and second resistor layers are changed due to a process or the like. To help. Therefore, by applying the binary weighting method, 2 N -1 resistance values can be made of N resistors, and the termination resistance can be stably adjusted regardless of a change in the resistance value (where N is a natural number).

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1 is a circuit diagram illustrating an on die termination (ODT) device according to the prior art.

FIG. 2 is a graph showing characteristics of a termination resistor formed by a calibration code in the on die termination apparatus shown in FIG. 1. FIG.

3 is a circuit diagram illustrating an on die termination (ODT) device according to an embodiment of the present invention.

4 and 5 are cross-sectional views illustrating a series connection method of the resistors R13 and R14 shown in FIG. 3.

FIG. 6 is a graph showing the characteristics of a termination resistor formed by a calibration code in the on die termination apparatus shown in FIG. 3. FIG.

FIG. 7 is a circuit diagram illustrating an on die termination (ODT) device according to another embodiment of the present invention. FIG.

Claims (8)

A plurality of resistance means corresponding to each bit of the calibration code and having different specific resistances; And A plurality of switching means for selectively connecting the plurality of resistance means in accordance with the calibration code, At least one of the plurality of resistance means has a different specific resistance and includes a plurality of resistors connected in series. The method of claim 1, wherein the plurality of resistance means First resistance means having a first specific resistance; And Second resistance means having a second resistivity On die termination device comprising a. 3. The on die termination apparatus of claim 2, wherein the plurality of resistors are included in the second resistor means at a position to switch from the first resistor means to the second resistor means. 3. The on die termination apparatus of claim 2, wherein the plurality of resistors are included in the first resistance means and the second resistance means, respectively. The on-die termination device of claim 1, wherein the plurality of resistance means and the plurality of switching means are connected in series between a power supply voltage supply terminal and a ground voltage application terminal in a one-to-one correspondence. The on-die termination apparatus according to claim 1, wherein each resistance value of said plurality of resistance means is 1/2 N times (where N is a natural number). 7. The on-die termination apparatus according to claim 6, wherein each resistance value of said plurality of resistance means sequentially decreases from the least significant bit of said calibration code to the most significant bit direction. 2. The on die termination apparatus of claim 1, wherein the plurality of switching means are selectively turned on by the calibration code to connect the plurality of resistance means in parallel.
KR1020080080877A 2008-08-19 2008-08-19 On die termination device KR20100022275A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9438232B2 (en) 2013-12-12 2016-09-06 Samsung Electronics Co., Ltd. Buffer circuit for compensating for a mismatch between on-die termination resistors and semiconductor device including the same, and operating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9438232B2 (en) 2013-12-12 2016-09-06 Samsung Electronics Co., Ltd. Buffer circuit for compensating for a mismatch between on-die termination resistors and semiconductor device including the same, and operating method thereof

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